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Daniel Walkerda6df072010-04-23 16:04:20 -07001/* include/linux/msm_mdp.h
2 *
3 * Copyright (C) 2007 Google Incorporated
Ken Zhang6affa8a2013-01-14 20:55:00 -05004 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
Daniel Walkerda6df072010-04-23 16:04:20 -07005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MSM_MDP_H_
16#define _MSM_MDP_H_
17
18#include <linux/types.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/fb.h>
Daniel Walkerda6df072010-04-23 16:04:20 -070020
21#define MSMFB_IOCTL_MAGIC 'm'
22#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
23#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070024#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
25#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
26#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
27#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
Carl Vanderlipba093a22011-11-22 13:59:59 -080028#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029/* new ioctls's for set/get ccs matrix */
30#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
31#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
32#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \
33 struct mdp_overlay)
34#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080035
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \
37 struct msmfb_overlay_data)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080038#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
39
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070040#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
41 struct mdp_page_protection)
42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
43 struct mdp_page_protection)
44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \
45 struct mdp_overlay)
46#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
47#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \
48 struct msmfb_overlay_blt)
49#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
Carl Vanderlipba093a22011-11-22 13:59:59 -080050#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \
51 struct mdp_histogram_start_req)
52#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070053#define MSMFB_NOTIFY_UPDATE _IOW(MSMFB_IOCTL_MAGIC, 146, unsigned int)
54
55#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \
56 struct msmfb_overlay_3d)
57
kuogee hsieh405dc302011-07-21 15:06:59 -070058#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
59 struct msmfb_mixer_info_req)
Nagamalleswararao Ganji0737d652011-10-14 02:02:33 -070060#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
61 struct msmfb_overlay_data)
Vinay Kalia27020d12011-10-14 17:50:29 -070062#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
Vinay Kaliae1ba2702011-12-21 16:24:52 -080063#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
64#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
Vinay Kalia27020d12011-10-14 17:50:29 -070065#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
66 struct msmfb_data)
67#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
68 struct msmfb_data)
69#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
Pravin Tamkhane02a40682011-11-29 14:17:01 -080070#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
Padmanabhan Komanduruf3b0c232012-07-27 20:46:06 +053071#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
72#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
Kinjal Bhavsardf5f3c82012-09-18 20:49:02 -070073#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
Naseer Ahmed76f0c662012-10-01 19:00:30 -040074#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \
75 struct mdp_display_commit)
Ken Zhange4d09e52013-01-08 14:28:20 -050076#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
Saurabh Shahbf14cc62012-09-27 12:47:10 -070077
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070078#define FB_TYPE_3D_PANEL 0x10101010
79#define MDP_IMGTYPE2_START 0x10000
80#define MSMFB_DRIVER_VERSION 0xF9E8D701
Daniel Walkerda6df072010-04-23 16:04:20 -070081
82enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070083 NOTIFY_UPDATE_START,
84 NOTIFY_UPDATE_STOP,
85};
86
87enum {
88 MDP_RGB_565, /* RGB 565 planer */
89 MDP_XRGB_8888, /* RGB 888 padded */
90 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */
Padmanabhan Komandurud9f38b02012-02-02 18:57:03 +053091 MDP_Y_CBCR_H2V2_ADRENO,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070092 MDP_ARGB_8888, /* ARGB 888 */
93 MDP_RGB_888, /* RGB 888 planer */
94 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */
95 MDP_YCRYCB_H2V1, /* YCrYCb interleave */
96 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
97 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -070098 MDP_Y_CRCB_H1V2,
99 MDP_Y_CBCR_H1V2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700100 MDP_RGBA_8888, /* ARGB 888 */
101 MDP_BGRA_8888, /* ABGR 888 */
102 MDP_RGBX_8888, /* RGBX 888 */
103 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
104 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
105 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
Pradeep Jilagam9b4a6be2011-10-03 17:19:20 +0530106 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700107 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
108 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
109 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
Adrian Salido-Moreno2b410482011-08-15 10:40:40 -0700110 MDP_YCRCB_H1V1, /* YCrCb interleave */
111 MDP_YCBCR_H1V1, /* YCbCr interleave */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700112 MDP_BGR_565, /* BGR 565 planer */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700113 MDP_IMGTYPE_LIMIT,
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800114 MDP_RGB_BORDERFILL, /* border fill pipe */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700115 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700116 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
Daniel Walkerda6df072010-04-23 16:04:20 -0700117};
118
119enum {
120 PMEM_IMG,
121 FB_IMG,
122};
123
Liyuan Lid9736632011-11-11 13:47:59 -0800124enum {
125 HSIC_HUE = 0,
126 HSIC_SAT,
127 HSIC_INT,
128 HSIC_CON,
129 NUM_HSIC_PARAM,
130};
131
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700132#define MDSS_MDP_ROT_ONLY 0x80
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700133#define MDSS_MDP_RIGHT_MIXER 0x100
134
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700135/* mdp_blit_req flag values */
136#define MDP_ROT_NOP 0
137#define MDP_FLIP_LR 0x1
138#define MDP_FLIP_UD 0x2
139#define MDP_ROT_90 0x4
140#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
141#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
142#define MDP_DITHER 0x8
143#define MDP_BLUR 0x10
144#define MDP_BLEND_FG_PREMULT 0x20000
145#define MDP_DEINTERLACE 0x80000000
146#define MDP_SHARPENING 0x40000000
147#define MDP_NO_DMA_BARRIER_START 0x20000000
148#define MDP_NO_DMA_BARRIER_END 0x10000000
149#define MDP_NO_BLIT 0x08000000
150#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
151#define MDP_BLIT_WITH_NO_DMA_BARRIERS \
152 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
153#define MDP_BLIT_SRC_GEM 0x04000000
154#define MDP_BLIT_DST_GEM 0x02000000
155#define MDP_BLIT_NON_CACHED 0x01000000
156#define MDP_OV_PIPE_SHARE 0x00800000
157#define MDP_DEINTERLACE_ODD 0x00400000
158#define MDP_OV_PLAY_NOWAIT 0x00200000
159#define MDP_SOURCE_ROTATED_90 0x00100000
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700160#define MDP_OVERLAY_PP_CFG_EN 0x00080000
Ajay Singh Parmar4c7ccb32012-02-21 12:56:04 +0530161#define MDP_BACKEND_COMPOSITION 0x00040000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800162#define MDP_BORDERFILL_SUPPORTED 0x00010000
163#define MDP_SECURE_OVERLAY_SESSION 0x00008000
164#define MDP_MEMORY_ID_TYPE_FB 0x00001000
Daniel Walkerda6df072010-04-23 16:04:20 -0700165
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700166#define MDP_TRANSP_NOP 0xffffffff
167#define MDP_ALPHA_NOP 0xff
168
169#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
170#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
171#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
172#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
173#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
174/* Sentinel: Don't use! */
175#define MDP_FB_PAGE_PROTECTION_INVALID (5)
176/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
177#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
Daniel Walkerda6df072010-04-23 16:04:20 -0700178
179struct mdp_rect {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700180 uint32_t x;
181 uint32_t y;
182 uint32_t w;
183 uint32_t h;
Daniel Walkerda6df072010-04-23 16:04:20 -0700184};
185
186struct mdp_img {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700187 uint32_t width;
188 uint32_t height;
189 uint32_t format;
190 uint32_t offset;
Daniel Walkerda6df072010-04-23 16:04:20 -0700191 int memory_id; /* the file descriptor */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700192 uint32_t priv;
Daniel Walkerda6df072010-04-23 16:04:20 -0700193};
194
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700195/*
196 * {3x3} + {3} ccs matrix
197 */
198
199#define MDP_CCS_RGB2YUV 0
200#define MDP_CCS_YUV2RGB 1
201
202#define MDP_CCS_SIZE 9
203#define MDP_BV_SIZE 3
204
205struct mdp_ccs {
206 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */
207 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */
208 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
209};
210
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800211struct mdp_csc {
212 int id;
213 uint32_t csc_mv[9];
214 uint32_t csc_pre_bv[3];
215 uint32_t csc_post_bv[3];
216 uint32_t csc_pre_lv[6];
217 uint32_t csc_post_lv[6];
218};
219
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700220/* The version of the mdp_blit_req structure so that
221 * user applications can selectively decide which functionality
222 * to include
223 */
224
225#define MDP_BLIT_REQ_VERSION 2
226
Daniel Walkerda6df072010-04-23 16:04:20 -0700227struct mdp_blit_req {
228 struct mdp_img src;
229 struct mdp_img dst;
230 struct mdp_rect src_rect;
231 struct mdp_rect dst_rect;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700232 uint32_t alpha;
233 uint32_t transp_mask;
234 uint32_t flags;
235 int sharpening_strength; /* -127 <--> 127, default 64 */
Daniel Walkerda6df072010-04-23 16:04:20 -0700236};
237
238struct mdp_blit_req_list {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700239 uint32_t count;
Daniel Walkerda6df072010-04-23 16:04:20 -0700240 struct mdp_blit_req req[];
241};
242
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700243#define MSMFB_DATA_VERSION 2
244
245struct msmfb_data {
246 uint32_t offset;
247 int memory_id;
248 int id;
249 uint32_t flags;
250 uint32_t priv;
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800251 uint32_t iova;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700252};
253
254#define MSMFB_NEW_REQUEST -1
255
256struct msmfb_overlay_data {
257 uint32_t id;
258 struct msmfb_data data;
259 uint32_t version_key;
260 struct msmfb_data plane1_data;
261 struct msmfb_data plane2_data;
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700262 struct msmfb_data dst_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700263};
264
265struct msmfb_img {
266 uint32_t width;
267 uint32_t height;
268 uint32_t format;
269};
270
Vinay Kalia27020d12011-10-14 17:50:29 -0700271#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
272struct msmfb_writeback_data {
273 struct msmfb_data buf_info;
274 struct msmfb_img img;
275};
276
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700277#define MDP_PP_OPS_READ 0x2
278#define MDP_PP_OPS_WRITE 0x4
279
280struct mdp_qseed_cfg {
281 uint32_t table_num;
282 uint32_t ops;
283 uint32_t len;
284 uint32_t *data;
285};
286
287struct mdp_qseed_cfg_data {
288 uint32_t block;
289 struct mdp_qseed_cfg qseed_data;
290};
291
292#define MDP_OVERLAY_PP_CSC_CFG 0x1
293#define MDP_OVERLAY_PP_QSEED_CFG 0x2
294
295#define MDP_CSC_FLAG_ENABLE 0x1
296#define MDP_CSC_FLAG_YUV_IN 0x2
297#define MDP_CSC_FLAG_YUV_OUT 0x4
298
299struct mdp_csc_cfg {
300 /* flags for enable CSC, toggling RGB,YUV input/output */
301 uint32_t flags;
302 uint32_t csc_mv[9];
303 uint32_t csc_pre_bv[3];
304 uint32_t csc_post_bv[3];
305 uint32_t csc_pre_lv[6];
306 uint32_t csc_post_lv[6];
307};
308
309struct mdp_csc_cfg_data {
310 uint32_t block;
311 struct mdp_csc_cfg csc_data;
312};
313
314struct mdp_overlay_pp_params {
315 uint32_t config_ops;
316 struct mdp_csc_cfg csc_cfg;
317 struct mdp_qseed_cfg qseed_cfg[2];
318};
319
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700320struct mdp_overlay {
321 struct msmfb_img src;
322 struct mdp_rect src_rect;
323 struct mdp_rect dst_rect;
324 uint32_t z_order; /* stage number */
325 uint32_t is_fg; /* control alpha & transp */
326 uint32_t alpha;
327 uint32_t transp_mask;
328 uint32_t flags;
329 uint32_t id;
330 uint32_t user_data[8];
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700331 struct mdp_overlay_pp_params overlay_pp_cfg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700332};
333
334struct msmfb_overlay_3d {
335 uint32_t is_3d;
336 uint32_t width;
337 uint32_t height;
338};
339
340
341struct msmfb_overlay_blt {
342 uint32_t enable;
343 uint32_t offset;
344 uint32_t width;
345 uint32_t height;
346 uint32_t bpp;
347};
348
349struct mdp_histogram {
350 uint32_t frame_cnt;
351 uint32_t bin_cnt;
352 uint32_t *r;
353 uint32_t *g;
354 uint32_t *b;
355};
356
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800357
358/*
359
Ken Zhangce8b2602012-08-08 16:46:22 -0400360 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800361
362 MDP_BLOCK_RESERVED is provided for backward compatibility and is
363 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
364 instead.
365
Ken Zhangce8b2602012-08-08 16:46:22 -0400366 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
367 same for others.
368
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800369*/
370
371enum {
372 MDP_BLOCK_RESERVED = 0,
373 MDP_BLOCK_OVERLAY_0,
374 MDP_BLOCK_OVERLAY_1,
375 MDP_BLOCK_VG_1,
376 MDP_BLOCK_VG_2,
377 MDP_BLOCK_RGB_1,
378 MDP_BLOCK_RGB_2,
379 MDP_BLOCK_DMA_P,
380 MDP_BLOCK_DMA_S,
381 MDP_BLOCK_DMA_E,
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700382 MDP_BLOCK_OVERLAY_2,
Ken Zhangce8b2602012-08-08 16:46:22 -0400383 MDP_LOGICAL_BLOCK_DISP_0 = 0x1000,
384 MDP_LOGICAL_BLOCK_DISP_1,
385 MDP_LOGICAL_BLOCK_DISP_2,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800386 MDP_BLOCK_MAX,
387};
388
Carl Vanderlipba093a22011-11-22 13:59:59 -0800389/*
390 * mdp_histogram_start_req is used to provide the parameters for
391 * histogram start request
392 */
393
394struct mdp_histogram_start_req {
395 uint32_t block;
396 uint8_t frame_cnt;
397 uint8_t bit_mask;
398 uint8_t num_bins;
399};
400
401/*
402 * mdp_histogram_data is used to return the histogram data, once
403 * the histogram is done/stopped/cance
404 */
405
406struct mdp_histogram_data {
407 uint32_t block;
408 uint8_t bin_cnt;
409 uint32_t *c0;
410 uint32_t *c1;
411 uint32_t *c2;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800412 uint32_t *extra_info;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800413};
414
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800415struct mdp_pcc_coeff {
416 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
417};
418
419struct mdp_pcc_cfg_data {
420 uint32_t block;
421 uint32_t ops;
422 struct mdp_pcc_coeff r, g, b;
423};
424
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800425enum {
426 mdp_lut_igc,
427 mdp_lut_pgc,
428 mdp_lut_hist,
429 mdp_lut_max,
430};
431
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800432struct mdp_igc_lut_data {
433 uint32_t block;
434 uint32_t len, ops;
435 uint32_t *c0_c1_data;
436 uint32_t *c2_data;
437};
438
439struct mdp_ar_gc_lut_data {
440 uint32_t x_start;
441 uint32_t slope;
442 uint32_t offset;
443};
444
445struct mdp_pgc_lut_data {
446 uint32_t block;
447 uint32_t flags;
448 uint8_t num_r_stages;
449 uint8_t num_g_stages;
450 uint8_t num_b_stages;
451 struct mdp_ar_gc_lut_data *r_data;
452 struct mdp_ar_gc_lut_data *g_data;
453 struct mdp_ar_gc_lut_data *b_data;
454};
455
456
457struct mdp_hist_lut_data {
458 uint32_t block;
459 uint32_t ops;
460 uint32_t len;
461 uint32_t *data;
462};
463
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800464struct mdp_lut_cfg_data {
465 uint32_t lut_type;
466 union {
467 struct mdp_igc_lut_data igc_lut_data;
468 struct mdp_pgc_lut_data pgc_lut_data;
469 struct mdp_hist_lut_data hist_lut_data;
470 } data;
471};
472
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700473struct mdp_bl_scale_data {
474 uint32_t min_lvl;
475 uint32_t scale;
476};
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700477
Carl Vanderlip1fd82442012-09-28 16:04:10 -0700478struct mdp_calib_config_data {
479 uint32_t ops;
480 uint32_t addr;
481 uint32_t data;
482};
483
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800484enum {
485 mdp_op_pcc_cfg,
486 mdp_op_csc_cfg,
487 mdp_op_lut_cfg,
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700488 mdp_op_qseed_cfg,
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700489 mdp_bl_scale_cfg,
Carl Vanderlip1fd82442012-09-28 16:04:10 -0700490 mdp_op_calib_cfg,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800491 mdp_op_max,
492};
493
494struct msmfb_mdp_pp {
495 uint32_t op;
496 union {
497 struct mdp_pcc_cfg_data pcc_cfg_data;
498 struct mdp_csc_cfg_data csc_cfg_data;
499 struct mdp_lut_cfg_data lut_cfg_data;
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700500 struct mdp_qseed_cfg_data qseed_cfg_data;
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700501 struct mdp_bl_scale_data bl_scale_data;
Carl Vanderlip1fd82442012-09-28 16:04:10 -0700502 struct mdp_calib_config_data calib_cfg;
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800503 } data;
504};
505
Ken Zhange4d09e52013-01-08 14:28:20 -0500506enum {
507 metadata_op_none,
508 metadata_op_base_blend,
509 metadata_op_frame_rate,
510 metadata_op_max
511};
512
513struct mdp_blend_cfg {
514 uint32_t is_premultiplied;
515};
516
517struct msmfb_metadata {
518 uint32_t op;
519 uint32_t flags;
520 union {
521 struct mdp_blend_cfg blend_cfg;
522 uint32_t panel_frame_rate;
523 } data;
524};
525
Naseer Ahmed76f0c662012-10-01 19:00:30 -0400526#define MDP_MAX_FENCE_FD 10
Naseer Ahmed2f3c4382012-10-02 21:00:10 -0400527#define MDP_BUF_SYNC_FLAG_WAIT 1
Kinjal Bhavsardf5f3c82012-09-18 20:49:02 -0700528
529struct mdp_buf_sync {
530 uint32_t flags;
531 uint32_t acq_fen_fd_cnt;
532 int *acq_fen_fd;
533 int *rel_fen_fd;
534};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800535
Naseer Ahmed76f0c662012-10-01 19:00:30 -0400536struct mdp_buf_fence {
537 uint32_t flags;
538 uint32_t acq_fen_fd_cnt;
539 int acq_fen_fd[MDP_MAX_FENCE_FD];
540 int rel_fen_fd[MDP_MAX_FENCE_FD];
541};
542
Naseer Ahmed309c0ca2012-11-19 19:22:02 -0500543#define MDP_DISPLAY_COMMIT_OVERLAY 0x00000001
544
Naseer Ahmed76f0c662012-10-01 19:00:30 -0400545struct mdp_display_commit {
546 uint32_t flags;
547 uint32_t wait_for_finish;
548 struct fb_var_screeninfo var;
Naseer Ahmed76f0c662012-10-01 19:00:30 -0400549};
550
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700551struct mdp_page_protection {
552 uint32_t page_protection;
553};
554
kuogee hsieh405dc302011-07-21 15:06:59 -0700555
556struct mdp_mixer_info {
557 int pndx;
558 int pnum;
559 int ptype;
560 int mixer_num;
561 int z_order;
562};
563
564#define MAX_PIPE_PER_MIXER 4
565
566struct msmfb_mixer_info_req {
567 int mixer_num;
568 int cnt;
569 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
570};
571
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700572enum {
573 DISPLAY_SUBSYSTEM_ID,
574 ROTATOR_SUBSYSTEM_ID,
575};
kuogee hsieh405dc302011-07-21 15:06:59 -0700576
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700577#ifdef __KERNEL__
578
579/* get the framebuffer physical address information */
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700580int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num,
581 int subsys_id);
Vinay Kalia27020d12011-10-14 17:50:29 -0700582struct fb_info *msm_fb_get_writeback_fb(void);
583int msm_fb_writeback_init(struct fb_info *info);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800584int msm_fb_writeback_start(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700585int msm_fb_writeback_queue_buffer(struct fb_info *info,
586 struct msmfb_data *data);
587int msm_fb_writeback_dequeue_buffer(struct fb_info *info,
588 struct msmfb_data *data);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800589int msm_fb_writeback_stop(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700590int msm_fb_writeback_terminate(struct fb_info *info);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700591#endif
592
593#endif /*_MSM_MDP_H_*/