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Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001Introduction:
2=============
3
4Qualcomm Crypto (qcrypto) driver is a Linux crypto driver which interfaces
5with the Linux kernel crypto API layer to provide the HW crypto functions.
6This driver is accessed by kernel space apps via the kernel crypto API layer.
7At present there is no means for user space apps to access this module.
8
9Hardware description:
10=====================
11
12Qualcomm Crypto HW device family provides a series of algorithms implemented
13in the device.
14
15Crypto 2 hardware provides hashing - SHA-1, SHA-256, ciphering - DES, 3DES, AES
16algorithms, and concurrent operations of hashing, and ciphering.
17
18In addition to those functions provided by Crypto 2 HW, Crypto 3 provides fast
19AES algorithms.
20
21In addition to those functions provided by Crypto 3 HW, Crypto 3E provides
22HMAC-SHA1 hashing algorithm.
23
24In addition to those functions provided by Crypto 3 HW, Crypto 4.0 provides
25HMAC-SHA1/SHA256, AES CBC-MAC hashing algorithm and AES XTS/CCM cipher
26algorithms.
27
28
29Software description
30====================
31
32The module init function (_qcrypto_init()), does a platform_register(),
33to register the driver. As the result, the driver probe function,
34_qcrypto_probe(), will be invoked for each registered device.
35
36In the probe function, driver opens the low level CE (qce_open), and
37registers the supported algorithms to the kernel crypto API layer.
38Currently, qcrypto supports the following algorithms.
39
40 ablkcipher -
41 cbc(aes),ecb(aes),ctr(aes)
42 ahash -
43 sha1, sha256
44 aead -
45 authenc(hmac(sha1),cbc(aes))
46
47 The hmac(sha1), hmac(sha256, authenc(hmac(sha1),cbc(aes)), ccm(aes)
48 and xts(aes) algorithms are registered for some platforms that
49 support these in the CE hardware
50
51The HW device can support various algorithms. However, the most important
52algorithms to gain the performance using a HW crypto accelerator are
53AEAD, and ABLKCIPHER.
54
55AEAD stands for "authentication encryption with association data".
56ABLKCIPHER stands of "asynchronous block cipher".
57
58The AEAD structure is described in the following header file
59 LINUX/opensource/kernel/include/crypto/aead.h
60
61The design of the driver is to allow multiple requests
62issued from kernel client SW (eg IPSec).
63Therefore, the driver will have to internally queue the requests, and
64serialize the requests to the low level qce driver.
65
66When a request is received from the client, if there is no outstanding
67request, a qce (or qce40) request is issued, otherwise, the request is
68queued in the driver queue.
69
70On completion of a request, the qce (or qce40) invokes the registered
71callback from the qcrypto. The internal tasklet (done_tasklet) is scheduled
72in this callback function. The sole purpose of done_tasklet is
73to call the completion of the current active request, and
74issue more requests to the qce (or qce40), if any exists.
75
76A spin lock is used to protect the critical section of internal queue to
77be accessed from multiple tasks, SMP, and completion callback
78from qce.
79
80The driver maintains a set of statistics using debug fs. The files are
81in /debug/qcrypto/stats1, /debug/qcrypto/stats2, /debug/qcrypto/stats3;
82one for each instance of device. Reading the file associated with
83a device will retrieve the driver statistics for that device.
84Any write to the file will clear the statistics.
85
86Test vectors for authenc(hmac(sha1),cbc(aes)) algorithm are
87developed offline, and imported to crypto/testmgr.c, and crypto/testmgr.h.
88
89
90Power Management
91================
92 none
93
94
95Interface:
96==========
97The kernel interface is defined in
98 LINUX/opensource/kernel/include/linux/crypto.h.
99
100
101Module parameters:
102==================
103
104All the platform specific parameters are defined in the board init
105file, eg. arch/arm/mach-msm/board-mssm7x30.c for msm7x30.
106
107Dependencies:
108=============
109qce driver.
110
111
112User space utilities:
113=====================
114 n/a
115
116Known issues:
117=============
118 n/a
119
120To do:
121======
122 Add Hashing algorithms.
123
124
125Limitations:
126===============
127(1) Each packet transfer size (for cipher and hash) is limited to maximum of
128 32KB. This is a limitation in the crypto engine hardware. Client will
129 have to break packets larger than 32KB into multiple requests of smaller
130 size data packets.
131
132(2) Do not load this driver if your device has user space apps that needs to
133 access the crypto hardware. Please make sure to have the qcrypto module
134 disabled/unloaded.
135 Not having the driver loaded, will result in the kernel space apps to use
136 the registered software implementation of the crypto algorithms.
137
138(3) If your device has Playready application enabled and uses the qcedev module
139 to access the crypto hardware accelarator, please be informed that for
140 performance reasons, the CE hardware will need to be dedicated to playready
141 application. Any other user space or kernel application should be implemented
142 to use the software implemenation of the crypto algorithms.
143
144 (NOTE: Please refer to details on the limitations listed in qce/40.txt)