blob: b0434f89e8deac8c1da4413b6dbc307c5b375fae [file] [log] [blame]
Michael Hennerich2714d9a2007-10-11 00:29:49 +08001/*
2 * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/interrupt.h>
10#include <asm/bfin-global.h>
11#include <asm/reboot.h>
Mike Frysingercdbf4c32008-10-13 11:33:43 +080012#include <asm/bfrom.h>
Michael Hennerich2714d9a2007-10-11 00:29:49 +080013
Mike Frysinger6a42a912008-04-23 08:01:31 +080014/* A system soft reset makes external memory unusable so force
15 * this function into L1. We use the compiler ssync here rather
16 * than SSYNC() because it's safe (no interrupts and such) and
17 * we save some L1. We do not need to force sanity in the SYSCR
18 * register as the BMODE selection bit is cleared by the soft
19 * reset while the Core B bit (on dual core parts) is cleared by
20 * the core reset.
Michael Hennerich2714d9a2007-10-11 00:29:49 +080021 */
Mike Frysingeradab7eb2009-02-04 16:49:45 +080022__attribute__ ((__l1_text__, __noreturn__))
Mike Frysingera6595bf2009-02-04 16:49:45 +080023static void bfin_reset(void)
Michael Hennerich2714d9a2007-10-11 00:29:49 +080024{
Mike Frysinger80310392011-05-02 00:00:35 -040025 if (!ANOMALY_05000353 && !ANOMALY_05000386)
26 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
27
Mike Frysinger6a42a912008-04-23 08:01:31 +080028 /* Wait for completion of "system" events such as cache line
29 * line fills so that we avoid infinite stalls later on as
30 * much as possible. This code is in L1, so it won't trigger
31 * any such event after this point in time.
32 */
33 __builtin_bfin_ssync();
Michael Hennerich2714d9a2007-10-11 00:29:49 +080034
Mike Frysinger80310392011-05-02 00:00:35 -040035 /* Initiate System software reset. */
36 bfin_write_SWRST(0x7);
37
38 /* Due to the way reset is handled in the hardware, we need
39 * to delay for 10 SCLKS. The only reliable way to do this is
40 * to calculate the CCLK/SCLK ratio and multiply 10. For now,
41 * we'll assume worse case which is a 1:15 ratio.
Mike Frysingeradab7eb2009-02-04 16:49:45 +080042 */
Mike Frysinger80310392011-05-02 00:00:35 -040043 asm(
44 "LSETUP (1f, 1f) LC0 = %0\n"
45 "1: nop;"
46 :
47 : "a" (15 * 10)
48 : "LC0", "LB0", "LT0"
49 );
Michael Hennerich444ad822008-01-22 18:38:02 +080050
Mike Frysinger80310392011-05-02 00:00:35 -040051 /* Clear System software reset */
52 bfin_write_SWRST(0);
Michael Hennerich444ad822008-01-22 18:38:02 +080053
Mike Frysinger80310392011-05-02 00:00:35 -040054 /* The BF526 ROM will crash during reset */
Mike Frysingeradab7eb2009-02-04 16:49:45 +080055#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
Mike Frysingerb0d3dc12011-06-30 00:49:30 -040056 /* Seems to be fixed with newer parts though ... */
57 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
58 bfin_read_SWRST();
Mike Frysingeradab7eb2009-02-04 16:49:45 +080059#endif
60
Mike Frysinger80310392011-05-02 00:00:35 -040061 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
62 * though as the System state is all reset now.
63 */
64 asm(
65 "LSETUP (1f, 1f) LC1 = %0\n"
66 "1: nop;"
67 :
68 : "a" (15 * 1)
69 : "LC1", "LB1", "LT1"
70 );
Mike Frysinger6a42a912008-04-23 08:01:31 +080071
Mike Frysingeradab7eb2009-02-04 16:49:45 +080072 while (1)
Mike Frysinger6a42a912008-04-23 08:01:31 +080073 /* Issue core reset */
Michael Hennerich2714d9a2007-10-11 00:29:49 +080074 asm("raise 1");
Michael Hennerich2714d9a2007-10-11 00:29:49 +080075}
76
77__attribute__((weak))
78void native_machine_restart(char *cmd)
79{
80}
81
82void machine_restart(char *cmd)
83{
84 native_machine_restart(cmd);
85 local_irq_disable();
Graf Yang8f658732008-11-18 17:48:22 +080086 if (smp_processor_id())
87 smp_call_function((void *)bfin_reset, 0, 1);
Mike Frysingercdbf4c32008-10-13 11:33:43 +080088 else
Graf Yang8f658732008-11-18 17:48:22 +080089 bfin_reset();
Michael Hennerich2714d9a2007-10-11 00:29:49 +080090}
91
92__attribute__((weak))
93void native_machine_halt(void)
94{
95 idle_with_irq_disabled();
96}
97
98void machine_halt(void)
99{
100 native_machine_halt();
101}
102
103__attribute__((weak))
104void native_machine_power_off(void)
105{
106 idle_with_irq_disabled();
107}
108
109void machine_power_off(void)
110{
111 native_machine_power_off();
112}