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review.evervolv.com / android_kernel_htc_msm8960 / 02a4ed4a5b0febad6f129e65ab9ae4794b51a61b / . / arch / sparc / kernel / trampoline_64.S
blob: 8fa84a3897cbb6f87eadd8583e411d02a779e6cf [file] [log] [blame]
Adrian Bunkb00dc832008-05-19 16:52:27 -0700[diff] [blame]1/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2 * trampoline.S: Jump start slave processors on sparc64.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
Sam Ravnborg0f7f22d2008-02-20 22:22:16 -0800[diff] [blame]7#include <linux/init.h>
8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]9#include <asm/head.h>
10#include <asm/asi.h>
11#include <asm/lsu.h>
12#include <asm/dcr.h>
13#include <asm/dcu.h>
14#include <asm/pstate.h>
15#include <asm/page.h>
16#include <asm/pgtable.h>
17#include <asm/spitfire.h>
18#include <asm/processor.h>
19#include <asm/thread_info.h>
20#include <asm/mmu.h>
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]21#include <asm/hypervisor.h>
David S. Miller3af6e012006-02-14 00:55:49 -0800[diff] [blame]22#include <asm/cpudata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]23
24 .data
25 .align 8
26call_method:
27 .asciz "call-method"
28 .align 8
29itlb_load:
30 .asciz "SUNW,itlb-load"
31 .align 8
32dtlb_load:
33 .asciz "SUNW,dtlb-load"
34
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]35 /* XXX __cpuinit this thing XXX */
36#define TRAMP_STACK_SIZE 1024
37 .align 16
38tramp_stack:
39 .skip TRAMP_STACK_SIZE
40
Sam Ravnborg0f7f22d2008-02-20 22:22:16 -0800[diff] [blame]41 __CPUINIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]42 .align 8
43 .globl sparc64_cpu_startup, sparc64_cpu_startup_end
44sparc64_cpu_startup:
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]45 BRANCH_IF_SUN4V(g1, niagara_startup)
46 BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
47 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]48
49 ba,pt %xcc, spitfire_startup
50 nop
51
52cheetah_plus_startup:
53 /* Preserve OBP chosen DCU and DCR register settings. */
54 ba,pt %xcc, cheetah_generic_startup
55 nop
56
57cheetah_startup:
58 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
59 wr %g1, %asr18
60
61 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
62 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
63 sllx %g5, 32, %g5
64 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
65 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
66 membar #Sync
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]67 /* fallthru */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]68
69cheetah_generic_startup:
70 mov TSB_EXTENSION_P, %g3
71 stxa %g0, [%g3] ASI_DMMU
72 stxa %g0, [%g3] ASI_IMMU
73 membar #Sync
74
75 mov TSB_EXTENSION_S, %g3
76 stxa %g0, [%g3] ASI_DMMU
77 membar #Sync
78
79 mov TSB_EXTENSION_N, %g3
80 stxa %g0, [%g3] ASI_DMMU
81 stxa %g0, [%g3] ASI_IMMU
82 membar #Sync
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]83 /* fallthru */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]84
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]85niagara_startup:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]86 /* Disable STICK_INT interrupts. */
87 sethi %hi(0x80000000), %g5
88 sllx %g5, 32, %g5
89 wr %g5, %asr25
90
91 ba,pt %xcc, startup_continue
92 nop
93
94spitfire_startup:
95 mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
96 stxa %g1, [%g0] ASI_LSU_CONTROL
97 membar #Sync
98
99startup_continue:
David S. Miller7dc40882007-08-16 01:56:00 -0700[diff] [blame]100 mov %o0, %l0
101 BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
102
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]103 sethi %hi(0x80000000), %g2
104 sllx %g2, 32, %g2
105 wr %g2, 0, %tick_cmpr
106
107 /* Call OBP by hand to lock KERNBASE into i/d tlbs.
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]108 * We lock 'num_kernel_image_mappings' consequetive entries.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]109 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]110 sethi %hi(prom_entry_lock), %g2
1111: ldstub [%g2 + %lo(prom_entry_lock)], %g1
112 brnz,pn %g1, 1b
David S. Millerb445e262005-06-27 15:42:04 -0700[diff] [blame]113 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]114
115 sethi %hi(p1275buf), %g2
116 or %g2, %lo(p1275buf), %g2
117 ldx [%g2 + 0x10], %l2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]118 add %l2, -(192 + 128), %sp
119 flushw
120
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]121 /* Setup the loop variables:
122 * %l3: VADDR base
123 * %l4: TTE base
124 * %l5: Loop iterator, iterates from 0 to 'num_kernel_image_mappings'
125 * %l6: Number of TTE entries to map
126 * %l7: Highest TTE entry number, we count down
127 */
128 sethi %hi(KERNBASE), %l3
129 sethi %hi(kern_locked_tte_data), %l4
130 ldx [%l4 + %lo(kern_locked_tte_data)], %l4
131 clr %l5
132 sethi %hi(num_kernel_image_mappings), %l6
133 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]134
135 mov 15, %l7
136 BRANCH_IF_ANY_CHEETAH(g1,g5,2f)
137
138 mov 63, %l7
1392:
140
1413:
142 /* Lock into I-MMU */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]143 sethi %hi(call_method), %g2
144 or %g2, %lo(call_method), %g2
145 stx %g2, [%sp + 2047 + 128 + 0x00]
146 mov 5, %g2
147 stx %g2, [%sp + 2047 + 128 + 0x08]
148 mov 1, %g2
149 stx %g2, [%sp + 2047 + 128 + 0x10]
150 sethi %hi(itlb_load), %g2
151 or %g2, %lo(itlb_load), %g2
152 stx %g2, [%sp + 2047 + 128 + 0x18]
David S. Millerbff06d52005-09-22 20:11:33 -0700[diff] [blame]153 sethi %hi(prom_mmu_ihandle_cache), %g2
154 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]155 stx %g2, [%sp + 2047 + 128 + 0x20]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]156
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]157 /* Each TTE maps 4MB, convert index to offset. */
158 sllx %l5, 22, %g1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]159
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]160 add %l3, %g1, %g2
161 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
162 add %l4, %g1, %g2
163 stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
164
165 /* TTE index is highest minus loop index. */
166 sub %l7, %l5, %g2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]167 stx %g2, [%sp + 2047 + 128 + 0x38]
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]169 sethi %hi(p1275buf), %g2
170 or %g2, %lo(p1275buf), %g2
171 ldx [%g2 + 0x08], %o1
172 call %o1
173 add %sp, (2047 + 128), %o0
174
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]175 /* Lock into D-MMU */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]176 sethi %hi(call_method), %g2
177 or %g2, %lo(call_method), %g2
178 stx %g2, [%sp + 2047 + 128 + 0x00]
179 mov 5, %g2
180 stx %g2, [%sp + 2047 + 128 + 0x08]
181 mov 1, %g2
182 stx %g2, [%sp + 2047 + 128 + 0x10]
183 sethi %hi(dtlb_load), %g2
184 or %g2, %lo(dtlb_load), %g2
185 stx %g2, [%sp + 2047 + 128 + 0x18]
David S. Millerbff06d52005-09-22 20:11:33 -0700[diff] [blame]186 sethi %hi(prom_mmu_ihandle_cache), %g2
187 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]188 stx %g2, [%sp + 2047 + 128 + 0x20]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]189
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]190 /* Each TTE maps 4MB, convert index to offset. */
191 sllx %l5, 22, %g1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]192
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]193 add %l3, %g1, %g2
194 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
195 add %l4, %g1, %g2
196 stx %g2, [%sp + 2047 + 128 + 0x30] ! TTE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]197
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]198 /* TTE index is highest minus loop index. */
199 sub %l7, %l5, %g2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]200 stx %g2, [%sp + 2047 + 128 + 0x38]
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]201
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]202 sethi %hi(p1275buf), %g2
203 or %g2, %lo(p1275buf), %g2
204 ldx [%g2 + 0x08], %o1
205 call %o1
206 add %sp, (2047 + 128), %o0
207
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]208 add %l5, 1, %l5
209 cmp %l5, %l6
210 bne,pt %xcc, 3b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]211 nop
212
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]213 sethi %hi(prom_entry_lock), %g2
214 stb %g0, [%g2 + %lo(prom_entry_lock)]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]215
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]216 ba,pt %xcc, after_lock_tlb
217 nop
218
219niagara_lock_tlb:
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]220 sethi %hi(KERNBASE), %l3
221 sethi %hi(kern_locked_tte_data), %l4
222 ldx [%l4 + %lo(kern_locked_tte_data)], %l4
223 clr %l5
224 sethi %hi(num_kernel_image_mappings), %l6
225 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]226
2271:
David S. Miller164c2202006-02-09 22:57:21 -0800[diff] [blame]228 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]229 sllx %l5, 22, %g2
230 add %l3, %g2, %o0
David S. Miller164c2202006-02-09 22:57:21 -0800[diff] [blame]231 clr %o1
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]232 add %l4, %g2, %o2
David S. Miller164c2202006-02-09 22:57:21 -0800[diff] [blame]233 mov HV_MMU_IMMU, %o3
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]234 ta HV_FAST_TRAP
235
David S. Miller164c2202006-02-09 22:57:21 -0800[diff] [blame]236 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]237 sllx %l5, 22, %g2
238 add %l3, %g2, %o0
David S. Miller164c2202006-02-09 22:57:21 -0800[diff] [blame]239 clr %o1
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]240 add %l4, %g2, %o2
David S. Miller164c2202006-02-09 22:57:21 -0800[diff] [blame]241 mov HV_MMU_DMMU, %o3
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]242 ta HV_FAST_TRAP
243
David S. Miller64658742008-03-21 17:01:38 -0700[diff] [blame]244 add %l5, 1, %l5
245 cmp %l5, %l6
246 bne,pt %xcc, 1b
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]247 nop
248
David S. Millerd82ace72006-02-09 02:52:44 -0800[diff] [blame]249after_lock_tlb:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]250 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
251 wr %g0, 0, %fprs
252
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]253 wr %g0, ASI_P, %asi
254
255 mov PRIMARY_CONTEXT, %g7
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]256
257661: stxa %g0, [%g7] ASI_DMMU
258 .section .sun4v_1insn_patch, "ax"
259 .word 661b
260 stxa %g0, [%g7] ASI_MMU
261 .previous
262
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]263 membar #Sync
264 mov SECONDARY_CONTEXT, %g7
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]265
266661: stxa %g0, [%g7] ASI_DMMU
267 .section .sun4v_1insn_patch, "ax"
268 .word 661b
269 stxa %g0, [%g7] ASI_MMU
270 .previous
271
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]272 membar #Sync
273
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]274 /* Everything we do here, until we properly take over the
275 * trap table, must be done with extreme care. We cannot
276 * make any references to %g6 (current thread pointer),
277 * %g4 (current task pointer), or %g5 (base of current cpu's
278 * per-cpu area) until we properly take over the trap table
279 * from the firmware and hypervisor.
280 *
281 * Get onto temporary stack which is in the locked kernel image.
282 */
283 sethi %hi(tramp_stack), %g1
284 or %g1, %lo(tramp_stack), %g1
285 add %g1, TRAMP_STACK_SIZE, %g1
David S. Miller301feb62007-09-16 11:51:15 -0700[diff] [blame]286 sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]287 mov 0, %fp
288
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]289 /* Put garbage in these registers to trap any access to them. */
290 set 0xdeadbeef, %g4
291 set 0xdeadbeef, %g5
292 set 0xdeadbeef, %g6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]293
294 call init_irqwork_curcpu
295 nop
David S. Millerac29c112006-02-08 00:08:23 -0800[diff] [blame]296
297 sethi %hi(tlb_type), %g3
298 lduw [%g3 + %lo(tlb_type)], %g2
299 cmp %g2, 3
300 bne,pt %icc, 1f
301 nop
302
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]303 call hard_smp_processor_id
304 nop
305
David S. Millerb434e712007-08-08 17:32:33 -0700[diff] [blame]306 call sun4v_register_mondo_queues
307 nop
David S. Millerac29c112006-02-08 00:08:23 -0800[diff] [blame]308
3091: call init_cur_cpu_trap
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]310 ldx [%l0], %o0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]311
David S. Miller0835ae02005-10-04 15:23:20 -0700[diff] [blame]312 /* Start using proper page size encodings in ctx register. */
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]313 sethi %hi(sparc64_kern_pri_context), %g3
314 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
315 mov PRIMARY_CONTEXT, %g1
316
317661: stxa %g2, [%g1] ASI_DMMU
318 .section .sun4v_1insn_patch, "ax"
319 .word 661b
320 stxa %g2, [%g1] ASI_MMU
321 .previous
322
323 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]324
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]325 wrpr %g0, 0, %wstate
326
Andrea Sheparde0037df2008-10-19 23:33:03 -0700[diff] [blame]327 sethi %hi(prom_entry_lock), %g2
3281: ldstub [%g2 + %lo(prom_entry_lock)], %g1
Andrea Sheparde0037df2008-10-19 23:33:03 -0700[diff] [blame]329 brnz,pn %g1, 1b
330 nop
331
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]332 /* As a hack, put &init_thread_union into %g6.
333 * prom_world() loads from here to restore the %asi
334 * register.
335 */
336 sethi %hi(init_thread_union), %g6
337 or %g6, %lo(init_thread_union), %g6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]338
David S. Miller12eaa322006-02-10 15:39:51 -0800[diff] [blame]339 sethi %hi(is_sun4v), %o0
340 lduw [%o0 + %lo(is_sun4v)], %o0
Andrea Sheparde0037df2008-10-19 23:33:03 -0700[diff] [blame]341 brz,pt %o0, 2f
David S. Miller12eaa322006-02-10 15:39:51 -0800[diff] [blame]342 nop
343
344 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
345 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
346 stxa %g2, [%g0] ASI_SCRATCHPAD
347
348 /* Compute physical address:
349 *
350 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
351 */
352 sethi %hi(KERNBASE), %g3
353 sub %g2, %g3, %g2
354 sethi %hi(kern_base), %g3
355 ldx [%g3 + %lo(kern_base)], %g3
356 add %g2, %g3, %o1
David S. Miller301feb62007-09-16 11:51:15 -0700[diff] [blame]357 sethi %hi(sparc64_ttable_tl0), %o0
David S. Miller12eaa322006-02-10 15:39:51 -0800[diff] [blame]358
David S. Miller301feb62007-09-16 11:51:15 -0700[diff] [blame]359 set prom_set_trap_table_name, %g2
360 stx %g2, [%sp + 2047 + 128 + 0x00]
361 mov 2, %g2
362 stx %g2, [%sp + 2047 + 128 + 0x08]
363 mov 0, %g2
364 stx %g2, [%sp + 2047 + 128 + 0x10]
365 stx %o0, [%sp + 2047 + 128 + 0x18]
366 stx %o1, [%sp + 2047 + 128 + 0x20]
367 sethi %hi(p1275buf), %g2
368 or %g2, %lo(p1275buf), %g2
369 ldx [%g2 + 0x08], %o1
370 call %o1
371 add %sp, (2047 + 128), %o0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]372
Andrea Sheparde0037df2008-10-19 23:33:03 -0700[diff] [blame]373 ba,pt %xcc, 3f
David S. Miller12eaa322006-02-10 15:39:51 -0800[diff] [blame]374 nop
375
Andrea Sheparde0037df2008-10-19 23:33:03 -0700[diff] [blame]3762: sethi %hi(sparc64_ttable_tl0), %o0
David S. Miller301feb62007-09-16 11:51:15 -0700[diff] [blame]377 set prom_set_trap_table_name, %g2
378 stx %g2, [%sp + 2047 + 128 + 0x00]
379 mov 1, %g2
380 stx %g2, [%sp + 2047 + 128 + 0x08]
381 mov 0, %g2
382 stx %g2, [%sp + 2047 + 128 + 0x10]
383 stx %o0, [%sp + 2047 + 128 + 0x18]
384 sethi %hi(p1275buf), %g2
385 or %g2, %lo(p1275buf), %g2
386 ldx [%g2 + 0x08], %o1
387 call %o1
388 add %sp, (2047 + 128), %o0
David S. Miller12eaa322006-02-10 15:39:51 -0800[diff] [blame]389
Andrea Sheparde0037df2008-10-19 23:33:03 -0700[diff] [blame]3903: sethi %hi(prom_entry_lock), %g2
391 stb %g0, [%g2 + %lo(prom_entry_lock)]
Andrea Sheparde0037df2008-10-19 23:33:03 -0700[diff] [blame]392
393 ldx [%l0], %g6
David S. Miller72aff532006-02-17 01:29:17 -0800[diff] [blame]394 ldx [%g6 + TI_TASK], %g4
395
396 mov 1, %g5
397 sllx %g5, THREAD_SHIFT, %g5
398 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
399 add %g6, %g5, %sp
400 mov 0, %fp
401
402 rdpr %pstate, %o1
403 or %o1, PSTATE_IE, %o1
404 wrpr %o1, 0, %pstate
405
406 call smp_callin
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]407 nop
408 call cpu_idle
409 mov 0, %o0
410 call cpu_panic
411 nop
4121: b,a,pt %xcc, 1b
413
414 .align 8
415sparc64_cpu_startup_end: