| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 1 | #ifndef __SOUND_AZT3328_H | 
 | 2 | #define __SOUND_AZT3328_H | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 |  | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 4 | /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10 */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 |  | 
 | 6 | /*** main I/O area port indices ***/ | 
 | 7 | /* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 8 | /* the driver initialisation suggests a layout of 4 main areas: | 
 | 9 |  * from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe MPU401??). | 
 | 10 |  * And another area from 0x60 to 0x6f (DirectX timer, IRQ management, | 
 | 11 |  * power management etc.???). */ | 
 | 12 |  | 
 | 13 | /** playback area **/ | 
 | 14 | #define IDX_IO_PLAY_FLAGS       0x00 /* PU:0x0000 */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 |      /* able to reactivate output after output muting due to 8/16bit | 
 | 16 |       * output change, just like 0x0002. | 
 | 17 |       * 0x0001 is the only bit that's able to start the DMA counter */ | 
 | 18 |   #define DMA_RESUME			0x0001 /* paused if cleared ? */ | 
 | 19 |      /* 0x0002 *temporarily* set during DMA stopping. hmm | 
 | 20 |       * both 0x0002 and 0x0004 set in playback setup. */ | 
 | 21 |      /* able to reactivate output after output muting due to 8/16bit | 
 | 22 |       * output change, just like 0x0001. */ | 
 | 23 |   #define DMA_PLAY_SOMETHING1		0x0002 /* \ alternated (toggled) */ | 
 | 24 |      /* 0x0004: NOT able to reactivate output */ | 
 | 25 |   #define DMA_PLAY_SOMETHING2		0x0004 /* / bits */ | 
 | 26 |   #define SOMETHING_ALMOST_ALWAYS_SET	0x0008 /* ???; can be modified */ | 
 | 27 |   #define DMA_EPILOGUE_SOMETHING	0x0010 | 
 | 28 |   #define DMA_SOMETHING_ELSE		0x0020 /* ??? */ | 
 | 29 |   #define SOMETHING_UNMODIFIABLE	0xffc0 /* unused ? not modifiable */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 30 | #define IDX_IO_PLAY_IRQTYPE     0x02 /* PU:0x0001 */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 |   /* write back to flags in case flags are set, in order to ACK IRQ in handler | 
 | 32 |    * (bit 1 of port 0x64 indicates interrupt for one of these three types) | 
 | 33 |    * sometimes in this case it just writes 0xffff to globally ACK all IRQs | 
 | 34 |    * settings written are not reflected when reading back, though. | 
 | 35 |    * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows ? */ | 
 | 36 |   #define IRQ_PLAY_SOMETHING		0x0001 /* something & ACK */ | 
 | 37 |   #define IRQ_FINISHED_PLAYBUF_1	0x0002 /* 1st dmabuf finished & ACK */ | 
 | 38 |   #define IRQ_FINISHED_PLAYBUF_2	0x0004 /* 2nd dmabuf finished & ACK */ | 
 | 39 |   #define IRQMASK_SOME_STATUS_1		0x0008 /* \ related bits */ | 
 | 40 |   #define IRQMASK_SOME_STATUS_2		0x0010 /* / (checked together in loop) */ | 
 | 41 |   #define IRQMASK_UNMODIFIABLE		0xffe0 /* unused ? not modifiable */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 42 | #define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area, PU:0x00000000 */ | 
 | 43 | #define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area, PU:0x00000000 */ | 
 | 44 | #define IDX_IO_PLAY_DMA_LEN_1   0x0c /* length of 1st DMA play area, PU:0x0000 */ | 
 | 45 | #define IDX_IO_PLAY_DMA_LEN_2   0x0e /* length of 2nd DMA play area, PU:0x0000 */ | 
 | 46 | #define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */ | 
 | 47 | #define IDX_IO_PLAY_DMA_CURROFS	0x14 /* offset within current DMA play area, PU:0x0000 */ | 
 | 48 | #define IDX_IO_PLAY_SOUNDFORMAT 0x16 /* PU:0x0010 */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 |   /* all unspecified bits can't be modified */ | 
 | 50 |   #define SOUNDFORMAT_FREQUENCY_MASK	0x000f | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 51 |   #define SOUNDFORMAT_XTAL1		0x00 | 
 | 52 |   #define SOUNDFORMAT_XTAL2		0x01 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 |     /* all _SUSPECTED_ values are not used by Windows drivers, so we don't | 
 | 54 |      * have any hard facts, only rough measurements */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 55 |     #define SOUNDFORMAT_FREQ_SUSPECTED_4000	0x0c | SOUNDFORMAT_XTAL1 | 
 | 56 |     #define SOUNDFORMAT_FREQ_SUSPECTED_4800	0x0a | SOUNDFORMAT_XTAL1 | 
 | 57 |     #define SOUNDFORMAT_FREQ_5510		0x0c | SOUNDFORMAT_XTAL2 | 
 | 58 |     #define SOUNDFORMAT_FREQ_6620		0x0a | SOUNDFORMAT_XTAL2 | 
 | 59 |     #define SOUNDFORMAT_FREQ_8000		0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */ | 
 | 60 |     #define SOUNDFORMAT_FREQ_9600		0x08 | SOUNDFORMAT_XTAL1 | 
 | 61 |     #define SOUNDFORMAT_FREQ_11025		0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */ | 
 | 62 |     #define SOUNDFORMAT_FREQ_SUSPECTED_13240	0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */ | 
 | 63 |     #define SOUNDFORMAT_FREQ_16000		0x02 | SOUNDFORMAT_XTAL1 | 
 | 64 |     #define SOUNDFORMAT_FREQ_22050		0x02 | SOUNDFORMAT_XTAL2 | 
 | 65 |     #define SOUNDFORMAT_FREQ_32000		0x04 | SOUNDFORMAT_XTAL1 | 
 | 66 |     #define SOUNDFORMAT_FREQ_44100		0x04 | SOUNDFORMAT_XTAL2 | 
 | 67 |     #define SOUNDFORMAT_FREQ_48000		0x06 | SOUNDFORMAT_XTAL1 | 
 | 68 |     #define SOUNDFORMAT_FREQ_SUSPECTED_66200	0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 |   #define SOUNDFORMAT_FLAG_16BIT	0x0010 | 
 | 70 |   #define SOUNDFORMAT_FLAG_2CHANNELS	0x0020 | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 71 |  | 
 | 72 | /** recording area (see also: playback bit flag definitions) **/ | 
 | 73 | #define IDX_IO_REC_FLAGS	0x20 /* ??, PU:0x0000 */ | 
 | 74 | #define IDX_IO_REC_IRQTYPE	0x22 /* ??, PU:0x0000 */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 |   #define IRQ_REC_SOMETHING		0x0001 /* something & ACK */ | 
 | 76 |   #define IRQ_FINISHED_RECBUF_1		0x0002 /* 1st dmabuf finished & ACK */ | 
 | 77 |   #define IRQ_FINISHED_RECBUF_2		0x0004 /* 2nd dmabuf finished & ACK */ | 
 | 78 |   /* hmm, maybe these are just the corresponding *recording* flags ? | 
 | 79 |    * but OTOH they are most likely at port 0x22 instead */ | 
 | 80 |   #define IRQMASK_SOME_STATUS_1		0x0008 /* \ related bits */ | 
 | 81 |   #define IRQMASK_SOME_STATUS_2		0x0010 /* / (checked together in loop) */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 82 | #define IDX_IO_REC_DMA_START_1  0x24 /* PU:0x00000000 */ | 
 | 83 | #define IDX_IO_REC_DMA_START_2  0x28 /* PU:0x00000000 */ | 
 | 84 | #define IDX_IO_REC_DMA_LEN_1    0x2c /* PU:0x0000 */ | 
 | 85 | #define IDX_IO_REC_DMA_LEN_2    0x2e /* PU:0x0000 */ | 
 | 86 | #define IDX_IO_REC_DMA_CURRPOS  0x30 /* PU:0x00000000 */ | 
 | 87 | #define IDX_IO_REC_DMA_CURROFS  0x34 /* PU:0x00000000 */ | 
 | 88 | #define IDX_IO_REC_SOUNDFORMAT  0x36 /* PU:0x0000 */ | 
 | 89 |  | 
 | 90 | /** hmm, what is this I/O area for? MPU401?? (after playback, recording, ???, timer) **/ | 
 | 91 | #define IDX_IO_SOMETHING_FLAGS	0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init, PU:0x0000 */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | /* general */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 93 | #define IDX_IO_42H		0x42 /* PU:0x0001 */ | 
 | 94 |  | 
 | 95 | /** DirectX timer, main interrupt area (FIXME: and something else?) **/  | 
 | 96 | #define IDX_IO_TIMER_VALUE	0x60 /* found this timer area by pure luck :-) */ | 
 | 97 |   #define TIMER_VALUE_MASK		0x000fffffUL /* timer countdown value; triggers IRQ when timer is finished */ | 
 | 98 |   #define TIMER_ENABLE_COUNTDOWN	0x01000000UL /* activate the timer countdown */ | 
 | 99 |   #define TIMER_ENABLE_IRQ		0x02000000UL /* trigger timer IRQ on zero transition */ | 
 | 100 |   #define TIMER_ACK_IRQ			0x04000000UL /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?) had 0x0020 set upon IRQ handler */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | #define IDX_IO_IRQSTATUS        0x64 | 
 | 102 |   #define IRQ_PLAYBACK			0x0001 | 
 | 103 |   #define IRQ_RECORDING			0x0002 | 
 | 104 |   #define IRQ_MPU401			0x0010 | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 105 |   #define IRQ_TIMER			0x0020 /* DirectX timer */ | 
 | 106 |   #define IRQ_UNKNOWN1			0x0040 /* probably unused */ | 
 | 107 |   #define IRQ_UNKNOWN2			0x0080 /* probably unused */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | #define IDX_IO_66H		0x66    /* writing 0xffff returns 0x0000 */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 109 | #define IDX_IO_SOME_VALUE	0x68	/* this is set to e.g. 0x3ff or 0x300, and writable; maybe some buffer limit, but I couldn't find out more, PU:0x00ff */ | 
 | 110 | #define IDX_IO_6AH		0x6A	/* this WORD can be set to have bits 0x0028 activated; actually inhibits PCM playback!!! maybe power management?? */ | 
 | 111 | #define IDX_IO_6CH		0x6C | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | #define IDX_IO_6EH		0x6E	/* writing 0xffff returns 0x83fe */ | 
 | 113 | /* further I/O indices not saved/restored, so probably not used */ | 
 | 114 |  | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 115 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | /*** I/O 2 area port indices ***/ | 
 | 117 | /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */  | 
 | 118 | #define IDX_IO2_LEGACY_ADDR	0x04 | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 119 |   #define LEGACY_SOMETHING		0x01 /* OPL3?? */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 |   #define LEGACY_JOY			0x08 | 
 | 121 |  | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 122 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | /*** mixer I/O area port indices ***/ | 
 | 124 | /* (only 0x22 of 0x40 bytes saved/restored by Windows driver) | 
 | 125 |  * generally spoken: AC97 register index = AZF3328 mixer reg index + 2 | 
 | 126 |  * (in other words: AZF3328 NOT fully AC97 compliant) */ | 
 | 127 |   #define MIXER_VOLUME_RIGHT_MASK	0x001f | 
 | 128 |   #define MIXER_VOLUME_LEFT_MASK	0x1f00 | 
 | 129 |   #define MIXER_MUTE_MASK		0x8000 | 
 | 130 | #define IDX_MIXER_RESET		0x00 /* does NOT seem to have AC97 ID bits */ | 
 | 131 | #define IDX_MIXER_PLAY_MASTER   0x02 | 
 | 132 | #define IDX_MIXER_MODEMOUT      0x04 | 
 | 133 | #define IDX_MIXER_BASSTREBLE    0x06 | 
 | 134 |   #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK	0x000e | 
 | 135 |   #define MIXER_BASSTREBLE_BASS_VOLUME_MASK	0x0e00 | 
 | 136 | #define IDX_MIXER_PCBEEP        0x08 | 
 | 137 | #define IDX_MIXER_MODEMIN       0x0a | 
 | 138 | #define IDX_MIXER_MIC           0x0c | 
 | 139 |   #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK	0x0040 | 
 | 140 | #define IDX_MIXER_LINEIN        0x0e | 
 | 141 | #define IDX_MIXER_CDAUDIO       0x10 | 
 | 142 | #define IDX_MIXER_VIDEO         0x12 | 
 | 143 | #define IDX_MIXER_AUX           0x14 | 
 | 144 | #define IDX_MIXER_WAVEOUT       0x16 | 
 | 145 | #define IDX_MIXER_FMSYNTH       0x18 | 
 | 146 | #define IDX_MIXER_REC_SELECT    0x1a | 
 | 147 |   #define MIXER_REC_SELECT_MIC		0x00 | 
 | 148 |   #define MIXER_REC_SELECT_CD		0x01 | 
 | 149 |   #define MIXER_REC_SELECT_VIDEO	0x02 | 
 | 150 |   #define MIXER_REC_SELECT_AUX		0x03 | 
 | 151 |   #define MIXER_REC_SELECT_LINEIN	0x04 | 
 | 152 |   #define MIXER_REC_SELECT_MIXSTEREO	0x05 | 
 | 153 |   #define MIXER_REC_SELECT_MIXMONO	0x06 | 
 | 154 |   #define MIXER_REC_SELECT_MONOIN	0x07 | 
 | 155 | #define IDX_MIXER_REC_VOLUME    0x1c | 
 | 156 | #define IDX_MIXER_ADVCTL1       0x1e | 
 | 157 |   /* unlisted bits are unmodifiable */ | 
 | 158 |   #define MIXER_ADVCTL1_3DWIDTH_MASK	0x000e | 
 | 159 |   #define MIXER_ADVCTL1_HIFI3D_MASK	0x0300 | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 160 | #define IDX_MIXER_ADVCTL2       0x20 /* resembles AC97_GENERAL_PURPOSE reg! */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 |   /* unlisted bits are unmodifiable */ | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 162 |   #define MIXER_ADVCTL2_BIT7		0x0080 /* WaveOut 3D Bypass? mutes WaveOut at LineOut */ | 
 | 163 |   #define MIXER_ADVCTL2_BIT8		0x0100 /* is this Modem Out Select? */ | 
 | 164 |   #define MIXER_ADVCTL2_BIT9		0x0200 /* Mono Select Source? */ | 
 | 165 |   #define MIXER_ADVCTL2_BIT13		0x2000 /* 3D enable? */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 |   #define MIXER_ADVCTL2_BIT15		0x8000 /* unknown */ | 
 | 167 |    | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 168 | #define IDX_MIXER_SOMETHING30H	0x30 /* used, but unknown??? */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 |  | 
 | 170 | /* driver internal flags */ | 
 | 171 | #define SET_CHAN_LEFT	1 | 
 | 172 | #define SET_CHAN_RIGHT	2 | 
 | 173 |  | 
| Andreas Mohr | d91c64c | 2005-10-25 11:17:45 +0200 | [diff] [blame] | 174 | #endif /* __SOUND_AZT3328_H  */ |