blob: 36d22b9413b897bb8e3f345d954a5f9d3e7ea2af [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
5 * ahennessy@mvista.com
6 *
7 * Based on arch/mips/ddb5xxx/ddb5477/setup.c
8 *
9 * Setup file for JMR3927.
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 ***********************************************************************
34 */
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <linux/init.h>
37#include <linux/kernel.h>
38#include <linux/kdev_t.h>
39#include <linux/types.h>
40#include <linux/sched.h>
41#include <linux/pci.h>
42#include <linux/ide.h>
Ralf Baechle046f8f72006-07-09 20:49:41 +010043#include <linux/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <linux/ioport.h>
45#include <linux/param.h> /* for HZ */
46#include <linux/delay.h>
Ralf Baechlefcdb27a2006-01-18 17:37:07 +000047#include <linux/pm.h>
Ralf Baechle5eaf7a22005-03-04 17:24:32 +000048#ifdef CONFIG_SERIAL_TXX9
49#include <linux/tty.h>
50#include <linux/serial.h>
51#include <linux/serial_core.h>
52#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54#include <asm/addrspace.h>
55#include <asm/time.h>
56#include <asm/bcache.h>
57#include <asm/irq.h>
58#include <asm/reboot.h>
59#include <asm/gdb-stub.h>
60#include <asm/jmr3927/jmr3927.h>
61#include <asm/mipsregs.h>
62#include <asm/traps.h>
63
Ralf Baechle380b9252005-11-19 21:51:56 +000064extern void puts(unsigned char *cp);
65
Linus Torvalds1da177e2005-04-16 15:20:36 -070066/* Tick Timer divider */
67#define JMR3927_TIMER_CCD 0 /* 1/2 */
68#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
69
70unsigned char led_state = 0xf;
71
72struct {
73 struct resource ram0;
74 struct resource ram1;
75 struct resource pcimem;
76 struct resource iob;
77 struct resource ioc;
78 struct resource pciio;
79 struct resource jmy1394;
80 struct resource rom1;
81 struct resource rom0;
82 struct resource sio0;
83 struct resource sio1;
84} jmr3927_resources = {
Ralf Baechle5e46c3a2006-06-04 15:14:05 -070085 {
86 .start = 0,
87 .end = 0x01FFFFFF,
88 .name = "RAM0",
89 .flags = IORESOURCE_MEM
90 }, {
91 .start = 0x02000000,
92 .end = 0x03FFFFFF,
93 .name = "RAM1",
94 .flags = IORESOURCE_MEM
95 }, {
96 .start = 0x08000000,
97 .end = 0x07FFFFFF,
98 .name = "PCIMEM",
99 .flags = IORESOURCE_MEM
100 }, {
101 .start = 0x10000000,
102 .end = 0x13FFFFFF,
103 .name = "IOB"
104 }, {
105 .start = 0x14000000,
106 .end = 0x14FFFFFF,
107 .name = "IOC"
108 }, {
109 .start = 0x15000000,
110 .end = 0x15FFFFFF,
111 .name = "PCIIO"
112 }, {
113 .start = 0x1D000000,
114 .end = 0x1D3FFFFF,
115 .name = "JMY1394"
116 }, {
117 .start = 0x1E000000,
118 .end = 0x1E3FFFFF,
119 .name = "ROM1"
120 }, {
121 .start = 0x1FC00000,
122 .end = 0x1FFFFFFF,
123 .name = "ROM0"
124 }, {
125 .start = 0xFFFEF300,
126 .end = 0xFFFEF3FF,
127 .name = "SIO0"
128 }, {
129 .start = 0xFFFEF400,
130 .end = 0xFFFEF4FF,
131 .name = "SIO1"
132 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133};
134
135/* don't enable - see errata */
136int jmr3927_ccfg_toeon = 0;
137
138static inline void do_reset(void)
139{
140#ifdef CONFIG_TC35815
141 extern void tc35815_killall(void);
142 tc35815_killall();
143#endif
144#if 1 /* Resetting PCI bus */
145 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
146 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
147 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
148 mdelay(1);
149 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
150#endif
151 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
152}
153
154static void jmr3927_machine_restart(char *command)
155{
156 local_irq_disable();
157 puts("Rebooting...");
158 do_reset();
159}
160
161static void jmr3927_machine_halt(void)
162{
163 puts("JMR-TX3927 halted.\n");
164 while (1);
165}
166
167static void jmr3927_machine_power_off(void)
168{
169 puts("JMR-TX3927 halted. Please turn off the power.\n");
170 while (1);
171}
172
173#define USE_RTC_DS1742
174#ifdef USE_RTC_DS1742
175extern void rtc_ds1742_init(unsigned long base);
176#endif
177static void __init jmr3927_time_init(void)
178{
179#ifdef USE_RTC_DS1742
180 if (jmr3927_have_nvram()) {
181 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
182 }
183#endif
184}
185
186unsigned long jmr3927_do_gettimeoffset(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187
188static void __init jmr3927_timer_setup(struct irqaction *irq)
189{
190 do_gettimeoffset = jmr3927_do_gettimeoffset;
191
192 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
193 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
194 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
195 jmr3927_tmrptr->tcr =
196 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
197
198 setup_irq(JMR3927_IRQ_TICK, irq);
199}
200
201#define USECS_PER_JIFFY (1000000/HZ)
202
203unsigned long jmr3927_do_gettimeoffset(void)
204{
205 unsigned long count;
206 unsigned long res = 0;
207
208 /* MUST read TRR before TISR. */
209 count = jmr3927_tmrptr->trr;
210
211 if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
212 /* timer interrupt is pending. use Max value. */
213 res = USECS_PER_JIFFY - 1;
214 } else {
215 /* convert to usec */
216 /* res = count / (JMR3927_TIMER_CLK / 1000000); */
217 res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
218
219 /*
220 * Due to possible jiffies inconsistencies, we need to check
221 * the result so that we'll get a timer that is monotonic.
222 */
223 if (res >= USECS_PER_JIFFY)
224 res = USECS_PER_JIFFY-1;
225 }
226
227 return res;
228}
229
230
231//#undef DO_WRITE_THROUGH
232#define DO_WRITE_THROUGH
233#define DO_ENABLE_CACHE
234
235extern char * __init prom_getcmdline(void);
236static void jmr3927_board_init(void);
237extern struct resource pci_io_resource;
238extern struct resource pci_mem_resource;
239
Ralf Baechle2925aba2006-06-18 01:32:22 +0100240void __init plat_mem_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241{
242 char *argptr;
243
244 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
245
246 board_time_init = jmr3927_time_init;
247 board_timer_setup = jmr3927_timer_setup;
248
249 _machine_restart = jmr3927_machine_restart;
250 _machine_halt = jmr3927_machine_halt;
Ralf Baechlefcdb27a2006-01-18 17:37:07 +0000251 pm_power_off = jmr3927_machine_power_off;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252
253 /*
254 * IO/MEM resources.
255 */
256 ioport_resource.start = pci_io_resource.start;
257 ioport_resource.end = pci_io_resource.end;
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000258 iomem_resource.start = 0;
259 iomem_resource.end = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260
261 /* Reboot on panic */
262 panic_timeout = 180;
263
264 {
265 unsigned int conf;
266 conf = read_c0_conf();
267 }
268
269#if 1
270 /* cache setup */
271 {
272 unsigned int conf;
273#ifdef DO_ENABLE_CACHE
274 int mips_ic_disable = 0, mips_dc_disable = 0;
275#else
276 int mips_ic_disable = 1, mips_dc_disable = 1;
277#endif
278#ifdef DO_WRITE_THROUGH
279 int mips_config_cwfon = 0;
280 int mips_config_wbon = 0;
281#else
282 int mips_config_cwfon = 1;
283 int mips_config_wbon = 1;
284#endif
285
286 conf = read_c0_conf();
287 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
288 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
289 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
290 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
291 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
292
293 write_c0_conf(conf);
294 write_c0_cache(0);
295 }
296#endif
297
298 /* initialize board */
299 jmr3927_board_init();
300
301 argptr = prom_getcmdline();
302
303 if ((argptr = strstr(argptr, "toeon")) != NULL) {
304 jmr3927_ccfg_toeon = 1;
305 }
306 argptr = prom_getcmdline();
307 if ((argptr = strstr(argptr, "ip=")) == NULL) {
308 argptr = prom_getcmdline();
309 strcat(argptr, " ip=bootp");
310 }
311
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000312#ifdef CONFIG_SERIAL_TXX9
313 {
314 extern int early_serial_txx9_setup(struct uart_port *port);
315 int i;
316 struct uart_port req;
317 for(i = 0; i < 2; i++) {
318 memset(&req, 0, sizeof(req));
319 req.line = i;
320 req.iotype = UPIO_MEM;
321 req.membase = (char *)TX3927_SIO_REG(i);
322 req.mapbase = TX3927_SIO_REG(i);
323 req.irq = i == 0 ?
324 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
325 if (i == 0)
326 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
327 req.uartclk = JMR3927_IMCLK;
328 early_serial_txx9_setup(&req);
329 }
330 }
331#ifdef CONFIG_SERIAL_TXX9_CONSOLE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 argptr = prom_getcmdline();
333 if ((argptr = strstr(argptr, "console=")) == NULL) {
334 argptr = prom_getcmdline();
335 strcat(argptr, " console=ttyS1,115200");
336 }
337#endif
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000338#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339}
340
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341static void tx3927_setup(void);
342
343#ifdef CONFIG_PCI
344unsigned long mips_pci_io_base;
345unsigned long mips_pci_io_size;
346unsigned long mips_pci_mem_base;
347unsigned long mips_pci_mem_size;
348/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
349unsigned long mips_pci_io_pciaddr = 0;
350#endif
351
352static void __init jmr3927_board_init(void)
353{
354 char *argptr;
355
356#ifdef CONFIG_PCI
357 mips_pci_io_base = JMR3927_PCIIO;
358 mips_pci_io_size = JMR3927_PCIIO_SIZE;
359 mips_pci_mem_base = JMR3927_PCIMEM;
360 mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
361#endif
362
363 tx3927_setup();
364
365 if (jmr3927_have_isac()) {
366
367#ifdef CONFIG_FB_E1355
368 argptr = prom_getcmdline();
369 if ((argptr = strstr(argptr, "video=")) == NULL) {
370 argptr = prom_getcmdline();
371 strcat(argptr, " video=e1355fb:crt16h");
372 }
373#endif
374
375#ifdef CONFIG_BLK_DEV_IDE
376 /* overrides PCI-IDE */
377#endif
378 }
379
380 /* SIO0 DTR on */
381 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
382
383 jmr3927_led_set(0);
384
385
386 if (jmr3927_have_isac())
387 jmr3927_io_led_set(0);
388 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
389 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
390 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
391 jmr3927_dipsw1(), jmr3927_dipsw2(),
392 jmr3927_dipsw3(), jmr3927_dipsw4());
393 if (jmr3927_have_isac())
394 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
395 jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
396 jmr3927_io_dipsw());
397}
398
Ralf Baechleefd94122005-11-11 11:46:25 +0000399void __init tx3927_setup(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400{
401 int i;
402
403 /* SDRAMC are configured by PROM */
404
405 /* ROMC */
406 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
407 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
408 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
409 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
410
411 /* CCFG */
412 /* enable Timeout BusError */
413 if (jmr3927_ccfg_toeon)
414 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
415
416 /* clear BusErrorOnWrite flag */
417 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
418 /* Disable PCI snoop */
419 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
420
421#ifdef DO_WRITE_THROUGH
422 /* Enable PCI SNOOP - with write through only */
423 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
424#endif
425
426 /* Pin selection */
427 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
428 tx3927_ccfgptr->pcfg |=
429 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
430 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
431
432 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
433 tx3927_ccfgptr->crir,
434 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
435
436 /* IRC */
437 /* disable interrupt control */
438 tx3927_ircptr->cer = 0;
439 /* mask all IRC interrupts */
440 tx3927_ircptr->imr = 0;
441 for (i = 0; i < TX3927_NUM_IR / 2; i++) {
442 tx3927_ircptr->ilr[i] = 0;
443 }
444 /* setup IRC interrupt mode (Low Active) */
445 for (i = 0; i < TX3927_NUM_IR / 8; i++) {
446 tx3927_ircptr->cr[i] = 0;
447 }
448
449 /* TMR */
450 /* disable all timers */
451 for (i = 0; i < TX3927_NR_TMR; i++) {
452 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
453 tx3927_tmrptr(i)->tisr = 0;
454 tx3927_tmrptr(i)->cpra = 0xffffffff;
455 tx3927_tmrptr(i)->itmr = 0;
456 tx3927_tmrptr(i)->ccdr = 0;
457 tx3927_tmrptr(i)->pgmr = 0;
458 }
459
460 /* DMA */
461 tx3927_dmaptr->mcr = 0;
462 for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
463 /* reset channel */
464 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
465 tx3927_dmaptr->ch[i].ccr = 0;
466 }
467 /* enable DMA */
468#ifdef __BIG_ENDIAN
469 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
470#else
471 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
472#endif
473
474#ifdef CONFIG_PCI
475 /* PCIC */
476 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
477 tx3927_pcicptr->did, tx3927_pcicptr->vid,
478 tx3927_pcicptr->rid);
479 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
480 printk("External\n");
481 /* XXX */
482 } else {
483 printk("Internal\n");
484
485 /* Reset PCI Bus */
486 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
487 udelay(100);
488 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
489 JMR3927_IOC_RESET_ADDR);
490 udelay(100);
491 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
492
493
494 /* Disable External PCI Config. Access */
495 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
496#ifdef __BIG_ENDIAN
497 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
498 TX3927_PCIC_LBC_TIBSE |
499 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
500#endif
501 /* LB->PCI mappings */
502 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
503 tx3927_pcicptr->ilbioma = mips_pci_io_base;
504 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
505 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
506 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
507 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
508 /* PCI->LB mappings */
509 tx3927_pcicptr->iobas = 0xffffffff;
510 tx3927_pcicptr->ioba = 0;
511 tx3927_pcicptr->tlbioma = 0;
512 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
513 tx3927_pcicptr->mba = 0;
514 tx3927_pcicptr->tlbmma = 0;
515#ifndef JMR3927_INIT_INDIRECT_PCI
516 /* Enable Direct mapping Address Space Decoder */
517 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
518#endif
519
520 /* Clear All Local Bus Status */
521 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
522 /* Enable All Local Bus Interrupts */
523 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
524 /* Clear All PCI Status Error */
525 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
526 /* Enable All PCI Status Error Interrupts */
527 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
528
529 /* PCIC Int => IRC IRQ10 */
530 tx3927_pcicptr->il = TX3927_IR_PCI;
531#if 1
532 /* Target Control (per errata) */
533 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
534#endif
535
536 /* Enable Bus Arbiter */
537#if 0
538 tx3927_pcicptr->req_trace = 0x73737373;
539#endif
540 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
541
542 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
543 PCI_COMMAND_MEMORY |
544#if 1
545 PCI_COMMAND_IO |
546#endif
547 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
548 }
549#endif /* CONFIG_PCI */
550
551 /* PIO */
552 /* PIO[15:12] connected to LEDs */
553 tx3927_pioptr->dir = 0x0000f000;
554 tx3927_pioptr->maskcpu = 0;
555 tx3927_pioptr->maskext = 0;
556 {
557 unsigned int conf;
558
559 conf = read_c0_conf();
560 if (!(conf & TX39_CONF_ICE))
561 printk("TX3927 I-Cache disabled.\n");
562 if (!(conf & TX39_CONF_DCE))
563 printk("TX3927 D-Cache disabled.\n");
564 else if (!(conf & TX39_CONF_WBON))
565 printk("TX3927 D-Cache WriteThrough.\n");
566 else if (!(conf & TX39_CONF_CWFON))
567 printk("TX3927 D-Cache WriteBack.\n");
568 else
569 printk("TX3927 D-Cache WriteBack (CWF) .\n");
570 }
571}