Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / 052d014485d2ce5bb7fa8dd0df875dafd1db77df / . / include / asm-mips / tx4927 / tx4927_pci.h
blob: 0be77df70f2bf1943748f0995fd4de7f22ec6f6b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 */
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]8#ifndef __ASM_TX4927_TX4927_PCI_H
9#define __ASM_TX4927_TX4927_PCI_H
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]10
11#define TX4927_CCFG_TOE 0x00004000
Atsushi Nemoto2064ba22007-11-24 01:20:27 +0900[diff] [blame]12#define TX4927_CCFG_WR 0x00008000
Atsushi Nemoto229f7732007-10-25 01:34:09 +0900[diff] [blame]13#define TX4927_CCFG_TINTDIS 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]14
15#define TX4927_PCIMEM 0x08000000
16#define TX4927_PCIMEM_SIZE 0x08000000
17#define TX4927_PCIIO 0x16000000
18#define TX4927_PCIIO_SIZE 0x01000000
19
20#define TX4927_SDRAMC_REG 0xff1f8000
21#define TX4927_EBUSC_REG 0xff1f9000
22#define TX4927_PCIC_REG 0xff1fd000
23#define TX4927_CCFG_REG 0xff1fe000
24#define TX4927_IRC_REG 0xff1ff600
Atsushi Nemoto229f7732007-10-25 01:34:09 +0900[diff] [blame]25#define TX4927_NR_TMR 3
26#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]27#define TX4927_CE3 0x17f00000 /* 1M */
28#define TX4927_PCIRESET_ADDR 0xbc00f006
29#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
30
31#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
32#define tx4927_imstat_ptr(n) \
33 ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
34
35/* bits for ISTAT3/IMASK3/IMSTAT3 */
36#define TX4927_INT3B_PCID 0
37#define TX4927_INT3B_PCIC 1
38#define TX4927_INT3B_PCIB 2
39#define TX4927_INT3B_PCIA 3
40#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
41#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
42#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
43#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
44
45/* bits for PCI_CLK (S6) */
46#define TX4927_PCI_CLK_HOST 0x80
47#define TX4927_PCI_CLK_MASK (0x0f << 3)
48#define TX4927_PCI_CLK_33 (0x01 << 3)
49#define TX4927_PCI_CLK_25 (0x04 << 3)
50#define TX4927_PCI_CLK_66 (0x09 << 3)
51#define TX4927_PCI_CLK_50 (0x0c << 3)
52#define TX4927_PCI_CLK_ACK 0x04
53#define TX4927_PCI_CLK_ACE 0x02
54#define TX4927_PCI_CLK_ENDIAN 0x01
Atsushi Nemotoc87abd72007-08-02 23:36:02 +0900[diff] [blame]55#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]56#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
57
58#define TX4927_IR_PCIC 16
59#define TX4927_IR_PCIERR 22
60#define TX4927_IR_PCIPMA 23
61#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
62#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
63#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
64#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
65#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
66#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
67#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
68
69#ifdef _LANGUAGE_ASSEMBLY
70#define _CONST64(c) c
71#else
72#define _CONST64(c) c##ull
73
74#include <asm/byteorder.h>
75
76#define tx4927_pcireset_ptr \
77 ((volatile unsigned char *)TX4927_PCIRESET_ADDR)
78#define tx4927_pci_clk_ptr \
79 ((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
80
81struct tx4927_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87};
88
89struct tx4927_ebusc_reg {
90 volatile unsigned long long cr[8];
91};
92
93struct tx4927_ccfg_reg {
94 volatile unsigned long long ccfg;
95 volatile unsigned long long crir;
96 volatile unsigned long long pcfg;
97 volatile unsigned long long tear;
98 volatile unsigned long long clkctr;
99 volatile unsigned long long unused0;
100 volatile unsigned long long garbc;
101 volatile unsigned long long unused1;
102 volatile unsigned long long unused2;
103 volatile unsigned long long ramp;
104};
105
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]106struct tx4927_pcic_reg {
107 volatile unsigned long pciid;
108 volatile unsigned long pcistatus;
109 volatile unsigned long pciccrev;
110 volatile unsigned long pcicfg1;
111 volatile unsigned long p2gm0plbase; /* +10 */
112 volatile unsigned long p2gm0pubase;
113 volatile unsigned long p2gm1plbase;
114 volatile unsigned long p2gm1pubase;
115 volatile unsigned long p2gm2pbase; /* +20 */
116 volatile unsigned long p2giopbase;
117 volatile unsigned long unused0;
118 volatile unsigned long pcisid;
119 volatile unsigned long unused1; /* +30 */
120 volatile unsigned long pcicapptr;
121 volatile unsigned long unused2;
122 volatile unsigned long pcicfg2;
123 volatile unsigned long g2ptocnt; /* +40 */
124 volatile unsigned long unused3[15];
125 volatile unsigned long g2pstatus; /* +80 */
126 volatile unsigned long g2pmask;
127 volatile unsigned long pcisstatus;
128 volatile unsigned long pcimask;
129 volatile unsigned long p2gcfg; /* +90 */
130 volatile unsigned long p2gstatus;
131 volatile unsigned long p2gmask;
132 volatile unsigned long p2gccmd;
133 volatile unsigned long unused4[24]; /* +a0 */
134 volatile unsigned long pbareqport; /* +100 */
135 volatile unsigned long pbacfg;
136 volatile unsigned long pbastatus;
137 volatile unsigned long pbamask;
138 volatile unsigned long pbabm; /* +110 */
139 volatile unsigned long pbacreq;
140 volatile unsigned long pbacgnt;
141 volatile unsigned long pbacstate;
142 volatile unsigned long long g2pmgbase[3]; /* +120 */
143 volatile unsigned long long g2piogbase;
144 volatile unsigned long g2pmmask[3]; /* +140 */
145 volatile unsigned long g2piomask;
146 volatile unsigned long long g2pmpbase[3]; /* +150 */
147 volatile unsigned long long g2piopbase;
148 volatile unsigned long pciccfg; /* +170 */
149 volatile unsigned long pcicstatus;
150 volatile unsigned long pcicmask;
151 volatile unsigned long unused5;
152 volatile unsigned long long p2gmgbase[3]; /* +180 */
153 volatile unsigned long long p2giogbase;
154 volatile unsigned long g2pcfgadrs; /* +1a0 */
155 volatile unsigned long g2pcfgdata;
156 volatile unsigned long unused6[8];
157 volatile unsigned long g2pintack;
158 volatile unsigned long g2pspc;
159 volatile unsigned long unused7[12]; /* +1d0 */
160 volatile unsigned long long pdmca; /* +200 */
161 volatile unsigned long long pdmga;
162 volatile unsigned long long pdmpa;
163 volatile unsigned long long pdmcut;
164 volatile unsigned long long pdmcnt; /* +220 */
165 volatile unsigned long long pdmsts;
166 volatile unsigned long long unused8[2];
167 volatile unsigned long long pdmdb[4]; /* +240 */
168 volatile unsigned long long pdmtdh; /* +260 */
169 volatile unsigned long long pdmdms;
170};
171
172#endif /* _LANGUAGE_ASSEMBLY */
173
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]174/*
175 * PCIC
176 */
177
178/* bits for G2PSTATUS/G2PMASK */
179#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
180#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
181#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
182
183/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
184#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
185
186/* bits for PBACFG */
187#define TX4927_PCIC_PBACFG_RPBA 0x00000004
188#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
189#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
190
191/* bits for G2PMnGBASE */
192#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
193#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
194
195/* bits for G2PIOGBASE */
196#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
197#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
198
199/* bits for PCICSTATUS/PCICMASK */
200#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
201
202/* bits for PCICCFG */
203#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
204#define TX4927_PCIC_PCICCFG_HRST 0x00000800
205#define TX4927_PCIC_PCICCFG_SRST 0x00000400
206#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
207#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
208#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
209#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
210#define TX4927_PCIC_PCICCFG_IISE 0x00000020
211#define TX4927_PCIC_PCICCFG_ATR 0x00000010
212#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
213
214/* bits for P2GMnGBASE */
215#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
216#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
217#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
218
219/* bits for P2GIOGBASE */
220#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
221#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
222#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
223
224#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
225#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
226
227/*
228 * CCFG
229 */
230/* CCFG : Chip Configuration */
231#define TX4927_CCFG_PCI66 0x00800000
232#define TX4927_CCFG_PCIMIDE 0x00400000
233#define TX4927_CCFG_PCIXARB 0x00002000
234#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
235#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
236#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
237#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
238#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
239
Sergei Shtylylovf09678a2006-02-04 15:11:14 +0300[diff] [blame]240#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
241#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
242#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
243#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
244#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
245#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
246#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
247#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
248#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
249
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]250/* PCFG : Pin Configuration */
251#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
252#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
253
254/* CLKCTR : Clock Control */
255#define TX4927_CLKCTR_PCICKD 0x00400000
256#define TX4927_CLKCTR_PCIRST 0x00000040
257
258
259#ifndef _LANGUAGE_ASSEMBLY
260
261#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
262#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
263#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
264#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]265
266#endif /* _LANGUAGE_ASSEMBLY */
267
268#endif /* __ASM_TX4927_TX4927_PCI_H */