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Rasesh Mody8b230ed2010-08-23 20:24:12 -07001/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include "bna.h"
19#include "bfa_sm.h"
20#include "bfa_wc.h"
21
Rasesh Modyb7ee31c2010-10-05 15:46:05 +000022static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
23
24static void
25bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
26 int status)
27{
28 int i;
29 u8 prio_map;
30
31 port->llport.link_status = BNA_LINK_UP;
32 if (aen->cee_linkup)
33 port->llport.link_status = BNA_CEE_UP;
34
35 /* Compute the priority */
36 prio_map = aen->prio_map;
37 if (prio_map) {
38 for (i = 0; i < 8; i++) {
39 if ((prio_map >> i) & 0x1)
40 break;
41 }
42 port->priority = i;
43 } else
44 port->priority = 0;
45
46 /* Dispatch events */
47 bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
48 bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
49 port->link_cbfn(port->bna->bnad, port->llport.link_status);
50}
51
52static void
53bna_port_cb_link_down(struct bna_port *port, int status)
54{
55 port->llport.link_status = BNA_LINK_DOWN;
56
57 /* Dispatch events */
58 bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
59 port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
60}
61
Rasesh Mody0613ecf2010-12-23 21:45:02 +000062static inline int
63llport_can_be_up(struct bna_llport *llport)
64{
65 int ready = 0;
66 if (llport->type == BNA_PORT_T_REGULAR)
67 ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
68 (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
69 (llport->flags & BNA_LLPORT_F_PORT_ENABLED));
70 else
71 ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
72 (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
73 !(llport->flags & BNA_LLPORT_F_PORT_ENABLED));
74 return ready;
75}
76
77#define llport_is_up llport_can_be_up
78
79enum bna_llport_event {
80 LLPORT_E_START = 1,
81 LLPORT_E_STOP = 2,
82 LLPORT_E_FAIL = 3,
83 LLPORT_E_UP = 4,
84 LLPORT_E_DOWN = 5,
85 LLPORT_E_FWRESP_UP_OK = 6,
86 LLPORT_E_FWRESP_UP_FAIL = 7,
87 LLPORT_E_FWRESP_DOWN = 8
88};
89
90static void
91bna_llport_cb_port_enabled(struct bna_llport *llport)
92{
93 llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
94
95 if (llport_can_be_up(llport))
96 bfa_fsm_send_event(llport, LLPORT_E_UP);
97}
98
99static void
100bna_llport_cb_port_disabled(struct bna_llport *llport)
101{
102 int llport_up = llport_is_up(llport);
103
104 llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
105
106 if (llport_up)
107 bfa_fsm_send_event(llport, LLPORT_E_DOWN);
108}
109
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700110/**
111 * MBOX
112 */
113static int
114bna_is_aen(u8 msg_id)
115{
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000116 switch (msg_id) {
117 case BFI_LL_I2H_LINK_DOWN_AEN:
118 case BFI_LL_I2H_LINK_UP_AEN:
119 case BFI_LL_I2H_PORT_ENABLE_AEN:
120 case BFI_LL_I2H_PORT_DISABLE_AEN:
121 return 1;
122
123 default:
124 return 0;
125 }
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700126}
127
128static void
129bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
130{
131 struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
132
133 switch (aen->mh.msg_id) {
134 case BFI_LL_I2H_LINK_UP_AEN:
135 bna_port_cb_link_up(&bna->port, aen, aen->reason);
136 break;
137 case BFI_LL_I2H_LINK_DOWN_AEN:
138 bna_port_cb_link_down(&bna->port, aen->reason);
139 break;
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000140 case BFI_LL_I2H_PORT_ENABLE_AEN:
141 bna_llport_cb_port_enabled(&bna->port.llport);
142 break;
143 case BFI_LL_I2H_PORT_DISABLE_AEN:
144 bna_llport_cb_port_disabled(&bna->port.llport);
145 break;
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700146 default:
147 break;
148 }
149}
150
151static void
152bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
153{
154 struct bna *bna = (struct bna *)(llarg);
155 struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
156 struct bfi_mhdr *cmd_h, *rsp_h;
157 struct bna_mbox_qe *mb_qe = NULL;
158 int to_post = 0;
159 u8 aen = 0;
160 char message[BNA_MESSAGE_SIZE];
161
162 aen = bna_is_aen(mb_rsp->mh.msg_id);
163
164 if (!aen) {
165 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
166 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
167 rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
168
169 if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
170 (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
171 /* Remove the request from posted_q, update state */
172 list_del(&mb_qe->qe);
173 bna->mbox_mod.msg_pending--;
174 if (list_empty(&bna->mbox_mod.posted_q))
175 bna->mbox_mod.state = BNA_MBOX_FREE;
176 else
177 to_post = 1;
178
179 /* Dispatch the cbfn */
180 if (mb_qe->cbfn)
181 mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
182
183 /* Post the next entry, if needed */
184 if (to_post) {
185 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
Rasesh Mody8a891422010-08-25 23:00:27 -0700186 bfa_nw_ioc_mbox_queue(&bna->device.ioc,
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700187 &mb_qe->cmd);
188 }
189 } else {
190 snprintf(message, BNA_MESSAGE_SIZE,
191 "No matching rsp for [%d:%d:%d]\n",
192 mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
193 mb_rsp->mh.mtag.i2htok);
194 pr_info("%s", message);
195 }
196
197 } else
198 bna_mbox_aen_callback(bna, msg);
199}
200
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000201static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700202bna_err_handler(struct bna *bna, u32 intr_status)
203{
204 u32 init_halt;
205
206 if (intr_status & __HALT_STATUS_BITS) {
207 init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
208 init_halt &= ~__FW_INIT_HALT_P;
209 writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
210 }
211
Rasesh Mody8a891422010-08-25 23:00:27 -0700212 bfa_nw_ioc_error_isr(&bna->device.ioc);
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700213}
214
215void
216bna_mbox_handler(struct bna *bna, u32 intr_status)
217{
218 if (BNA_IS_ERR_INTR(intr_status)) {
219 bna_err_handler(bna, intr_status);
220 return;
221 }
222 if (BNA_IS_MBOX_INTR(intr_status))
Rasesh Mody8a891422010-08-25 23:00:27 -0700223 bfa_nw_ioc_mbox_isr(&bna->device.ioc);
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700224}
225
226void
227bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
228{
229 struct bfi_mhdr *mh;
230
231 mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
232
233 mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
234 bna->mbox_mod.msg_ctr++;
235 bna->mbox_mod.msg_pending++;
236 if (bna->mbox_mod.state == BNA_MBOX_FREE) {
237 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
Rasesh Mody8a891422010-08-25 23:00:27 -0700238 bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd);
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700239 bna->mbox_mod.state = BNA_MBOX_POSTED;
240 } else {
241 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
242 }
243}
244
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000245static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700246bna_mbox_flush_q(struct bna *bna, struct list_head *q)
247{
248 struct bna_mbox_qe *mb_qe = NULL;
249 struct bfi_mhdr *cmd_h;
250 struct list_head *mb_q;
251 void (*cbfn)(void *arg, int status);
252 void *cbarg;
253
254 mb_q = &bna->mbox_mod.posted_q;
255
256 while (!list_empty(mb_q)) {
257 bfa_q_deq(mb_q, &mb_qe);
258 cbfn = mb_qe->cbfn;
259 cbarg = mb_qe->cbarg;
260 bfa_q_qe_init(mb_qe);
261 bna->mbox_mod.msg_pending--;
262
263 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
264 if (cbfn)
265 cbfn(cbarg, BNA_CB_NOT_EXEC);
266 }
267
268 bna->mbox_mod.state = BNA_MBOX_FREE;
269}
270
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000271static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700272bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
273{
274}
275
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000276static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700277bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
278{
279 bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
280}
281
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000282static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700283bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
284{
Rasesh Mody8a891422010-08-25 23:00:27 -0700285 bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700286 mbox_mod->state = BNA_MBOX_FREE;
287 mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
288 INIT_LIST_HEAD(&mbox_mod->posted_q);
289 mbox_mod->bna = bna;
290}
291
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000292static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700293bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
294{
295 mbox_mod->bna = NULL;
296}
297
298/**
299 * LLPORT
300 */
301#define call_llport_stop_cbfn(llport, status)\
302do {\
303 if ((llport)->stop_cbfn)\
304 (llport)->stop_cbfn(&(llport)->bna->port, status);\
305 (llport)->stop_cbfn = NULL;\
306} while (0)
307
308static void bna_fw_llport_up(struct bna_llport *llport);
309static void bna_fw_cb_llport_up(void *arg, int status);
310static void bna_fw_llport_down(struct bna_llport *llport);
311static void bna_fw_cb_llport_down(void *arg, int status);
312static void bna_llport_start(struct bna_llport *llport);
313static void bna_llport_stop(struct bna_llport *llport);
314static void bna_llport_fail(struct bna_llport *llport);
315
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700316enum bna_llport_state {
317 BNA_LLPORT_STOPPED = 1,
318 BNA_LLPORT_DOWN = 2,
319 BNA_LLPORT_UP_RESP_WAIT = 3,
320 BNA_LLPORT_DOWN_RESP_WAIT = 4,
321 BNA_LLPORT_UP = 5,
322 BNA_LLPORT_LAST_RESP_WAIT = 6
323};
324
325bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
326 enum bna_llport_event);
327bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
328 enum bna_llport_event);
329bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
330 enum bna_llport_event);
331bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
332 enum bna_llport_event);
333bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
334 enum bna_llport_event);
335bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
336 enum bna_llport_event);
337
338static struct bfa_sm_table llport_sm_table[] = {
339 {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
340 {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
341 {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
342 {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
343 {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
344 {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
345};
346
347static void
348bna_llport_sm_stopped_entry(struct bna_llport *llport)
349{
350 llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
351 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
352}
353
354static void
355bna_llport_sm_stopped(struct bna_llport *llport,
356 enum bna_llport_event event)
357{
358 switch (event) {
359 case LLPORT_E_START:
360 bfa_fsm_set_state(llport, bna_llport_sm_down);
361 break;
362
363 case LLPORT_E_STOP:
364 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
365 break;
366
367 case LLPORT_E_FAIL:
368 break;
369
370 case LLPORT_E_DOWN:
371 /* This event is received due to Rx objects failing */
372 /* No-op */
373 break;
374
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000375 case LLPORT_E_FWRESP_UP_OK:
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700376 case LLPORT_E_FWRESP_DOWN:
377 /**
378 * These events are received due to flushing of mbox when
379 * device fails
380 */
381 /* No-op */
382 break;
383
384 default:
385 bfa_sm_fault(llport->bna, event);
386 }
387}
388
389static void
390bna_llport_sm_down_entry(struct bna_llport *llport)
391{
392 bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
393}
394
395static void
396bna_llport_sm_down(struct bna_llport *llport,
397 enum bna_llport_event event)
398{
399 switch (event) {
400 case LLPORT_E_STOP:
401 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
402 break;
403
404 case LLPORT_E_FAIL:
405 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
406 break;
407
408 case LLPORT_E_UP:
409 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
410 bna_fw_llport_up(llport);
411 break;
412
413 default:
414 bfa_sm_fault(llport->bna, event);
415 }
416}
417
418static void
419bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
420{
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000421 BUG_ON(!llport_can_be_up(llport));
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700422 /**
423 * NOTE: Do not call bna_fw_llport_up() here. That will over step
424 * mbox due to down_resp_wait -> up_resp_wait transition on event
425 * LLPORT_E_UP
426 */
427}
428
429static void
430bna_llport_sm_up_resp_wait(struct bna_llport *llport,
431 enum bna_llport_event event)
432{
433 switch (event) {
434 case LLPORT_E_STOP:
435 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
436 break;
437
438 case LLPORT_E_FAIL:
439 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
440 break;
441
442 case LLPORT_E_DOWN:
443 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
444 break;
445
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000446 case LLPORT_E_FWRESP_UP_OK:
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700447 bfa_fsm_set_state(llport, bna_llport_sm_up);
448 break;
449
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000450 case LLPORT_E_FWRESP_UP_FAIL:
451 bfa_fsm_set_state(llport, bna_llport_sm_down);
452 break;
453
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700454 case LLPORT_E_FWRESP_DOWN:
455 /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
456 bna_fw_llport_up(llport);
457 break;
458
459 default:
460 bfa_sm_fault(llport->bna, event);
461 }
462}
463
464static void
465bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
466{
467 /**
468 * NOTE: Do not call bna_fw_llport_down() here. That will over step
469 * mbox due to up_resp_wait -> down_resp_wait transition on event
470 * LLPORT_E_DOWN
471 */
472}
473
474static void
475bna_llport_sm_down_resp_wait(struct bna_llport *llport,
476 enum bna_llport_event event)
477{
478 switch (event) {
479 case LLPORT_E_STOP:
480 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
481 break;
482
483 case LLPORT_E_FAIL:
484 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
485 break;
486
487 case LLPORT_E_UP:
488 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
489 break;
490
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000491 case LLPORT_E_FWRESP_UP_OK:
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700492 /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
493 bna_fw_llport_down(llport);
494 break;
495
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000496 case LLPORT_E_FWRESP_UP_FAIL:
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700497 case LLPORT_E_FWRESP_DOWN:
498 bfa_fsm_set_state(llport, bna_llport_sm_down);
499 break;
500
501 default:
502 bfa_sm_fault(llport->bna, event);
503 }
504}
505
506static void
507bna_llport_sm_up_entry(struct bna_llport *llport)
508{
509}
510
511static void
512bna_llport_sm_up(struct bna_llport *llport,
513 enum bna_llport_event event)
514{
515 switch (event) {
516 case LLPORT_E_STOP:
517 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
518 bna_fw_llport_down(llport);
519 break;
520
521 case LLPORT_E_FAIL:
522 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
523 break;
524
525 case LLPORT_E_DOWN:
526 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
527 bna_fw_llport_down(llport);
528 break;
529
530 default:
531 bfa_sm_fault(llport->bna, event);
532 }
533}
534
535static void
536bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
537{
538}
539
540static void
541bna_llport_sm_last_resp_wait(struct bna_llport *llport,
542 enum bna_llport_event event)
543{
544 switch (event) {
545 case LLPORT_E_FAIL:
546 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
547 break;
548
549 case LLPORT_E_DOWN:
550 /**
551 * This event is received due to Rx objects stopping in
552 * parallel to llport
553 */
554 /* No-op */
555 break;
556
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000557 case LLPORT_E_FWRESP_UP_OK:
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700558 /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
559 bna_fw_llport_down(llport);
560 break;
561
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000562 case LLPORT_E_FWRESP_UP_FAIL:
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700563 case LLPORT_E_FWRESP_DOWN:
564 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
565 break;
566
567 default:
568 bfa_sm_fault(llport->bna, event);
569 }
570}
571
572static void
573bna_fw_llport_admin_up(struct bna_llport *llport)
574{
575 struct bfi_ll_port_admin_req ll_req;
576
577 memset(&ll_req, 0, sizeof(ll_req));
578 ll_req.mh.msg_class = BFI_MC_LL;
579 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
580 ll_req.mh.mtag.h2i.lpu_id = 0;
581
582 ll_req.up = BNA_STATUS_T_ENABLED;
583
584 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
585 bna_fw_cb_llport_up, llport);
586
587 bna_mbox_send(llport->bna, &llport->mbox_qe);
588}
589
590static void
591bna_fw_llport_up(struct bna_llport *llport)
592{
593 if (llport->type == BNA_PORT_T_REGULAR)
594 bna_fw_llport_admin_up(llport);
595}
596
597static void
598bna_fw_cb_llport_up(void *arg, int status)
599{
600 struct bna_llport *llport = (struct bna_llport *)arg;
601
602 bfa_q_qe_init(&llport->mbox_qe.qe);
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000603 if (status == BFI_LL_CMD_FAIL) {
604 if (llport->type == BNA_PORT_T_REGULAR)
605 llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
606 else
607 llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
608 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_FAIL);
609 } else
610 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_OK);
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700611}
612
613static void
614bna_fw_llport_admin_down(struct bna_llport *llport)
615{
616 struct bfi_ll_port_admin_req ll_req;
617
618 memset(&ll_req, 0, sizeof(ll_req));
619 ll_req.mh.msg_class = BFI_MC_LL;
620 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
621 ll_req.mh.mtag.h2i.lpu_id = 0;
622
623 ll_req.up = BNA_STATUS_T_DISABLED;
624
625 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
626 bna_fw_cb_llport_down, llport);
627
628 bna_mbox_send(llport->bna, &llport->mbox_qe);
629}
630
631static void
632bna_fw_llport_down(struct bna_llport *llport)
633{
634 if (llport->type == BNA_PORT_T_REGULAR)
635 bna_fw_llport_admin_down(llport);
636}
637
638static void
639bna_fw_cb_llport_down(void *arg, int status)
640{
641 struct bna_llport *llport = (struct bna_llport *)arg;
642
643 bfa_q_qe_init(&llport->mbox_qe.qe);
644 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
645}
646
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000647static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700648bna_port_cb_llport_stopped(struct bna_port *port,
649 enum bna_cb_status status)
650{
651 bfa_wc_down(&port->chld_stop_wc);
652}
653
654static void
655bna_llport_init(struct bna_llport *llport, struct bna *bna)
656{
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000657 llport->flags |= BNA_LLPORT_F_ADMIN_UP;
658 llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700659 llport->type = BNA_PORT_T_REGULAR;
660 llport->bna = bna;
661
662 llport->link_status = BNA_LINK_DOWN;
663
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000664 llport->rx_started_count = 0;
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700665
666 llport->stop_cbfn = NULL;
667
668 bfa_q_qe_init(&llport->mbox_qe.qe);
669
670 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
671}
672
673static void
674bna_llport_uninit(struct bna_llport *llport)
675{
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000676 llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
677 llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700678
679 llport->bna = NULL;
680}
681
682static void
683bna_llport_start(struct bna_llport *llport)
684{
685 bfa_fsm_send_event(llport, LLPORT_E_START);
686}
687
688static void
689bna_llport_stop(struct bna_llport *llport)
690{
691 llport->stop_cbfn = bna_port_cb_llport_stopped;
692
693 bfa_fsm_send_event(llport, LLPORT_E_STOP);
694}
695
696static void
697bna_llport_fail(struct bna_llport *llport)
698{
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000699 /* Reset the physical port status to enabled */
700 llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700701 bfa_fsm_send_event(llport, LLPORT_E_FAIL);
702}
703
Rasesh Modyb7ee31c2010-10-05 15:46:05 +0000704static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700705bna_llport_state_get(struct bna_llport *llport)
706{
707 return bfa_sm_to_state(llport_sm_table, llport->fsm);
708}
709
710void
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000711bna_llport_rx_started(struct bna_llport *llport)
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700712{
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000713 llport->rx_started_count++;
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700714
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000715 if (llport->rx_started_count == 1) {
716
717 llport->flags |= BNA_LLPORT_F_RX_STARTED;
718
719 if (llport_can_be_up(llport))
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700720 bfa_fsm_send_event(llport, LLPORT_E_UP);
721 }
722}
723
724void
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000725bna_llport_rx_stopped(struct bna_llport *llport)
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700726{
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000727 int llport_up = llport_is_up(llport);
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700728
Rasesh Mody0613ecf2010-12-23 21:45:02 +0000729 llport->rx_started_count--;
730
731 if (llport->rx_started_count == 0) {
732
733 llport->flags &= ~BNA_LLPORT_F_RX_STARTED;
734
735 if (llport_up)
Rasesh Mody8b230ed2010-08-23 20:24:12 -0700736 bfa_fsm_send_event(llport, LLPORT_E_DOWN);
737 }
738}
739
740/**
741 * PORT
742 */
743#define bna_port_chld_start(port)\
744do {\
745 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
746 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
747 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
748 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
749 bna_llport_start(&(port)->llport);\
750 bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
751 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
752} while (0)
753
754#define bna_port_chld_stop(port)\
755do {\
756 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
757 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
758 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
759 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
760 bfa_wc_up(&(port)->chld_stop_wc);\
761 bfa_wc_up(&(port)->chld_stop_wc);\
762 bfa_wc_up(&(port)->chld_stop_wc);\
763 bna_llport_stop(&(port)->llport);\
764 bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
765 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
766} while (0)
767
768#define bna_port_chld_fail(port)\
769do {\
770 bna_llport_fail(&(port)->llport);\
771 bna_tx_mod_fail(&(port)->bna->tx_mod);\
772 bna_rx_mod_fail(&(port)->bna->rx_mod);\
773} while (0)
774
775#define bna_port_rx_start(port)\
776do {\
777 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
778 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
779 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
780} while (0)
781
782#define bna_port_rx_stop(port)\
783do {\
784 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
785 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
786 bfa_wc_up(&(port)->chld_stop_wc);\
787 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
788} while (0)
789
790#define call_port_stop_cbfn(port, status)\
791do {\
792 if ((port)->stop_cbfn)\
793 (port)->stop_cbfn((port)->stop_cbarg, status);\
794 (port)->stop_cbfn = NULL;\
795 (port)->stop_cbarg = NULL;\
796} while (0)
797
798#define call_port_pause_cbfn(port, status)\
799do {\
800 if ((port)->pause_cbfn)\
801 (port)->pause_cbfn((port)->bna->bnad, status);\
802 (port)->pause_cbfn = NULL;\
803} while (0)
804
805#define call_port_mtu_cbfn(port, status)\
806do {\
807 if ((port)->mtu_cbfn)\
808 (port)->mtu_cbfn((port)->bna->bnad, status);\
809 (port)->mtu_cbfn = NULL;\
810} while (0)
811
812static void bna_fw_pause_set(struct bna_port *port);
813static void bna_fw_cb_pause_set(void *arg, int status);
814static void bna_fw_mtu_set(struct bna_port *port);
815static void bna_fw_cb_mtu_set(void *arg, int status);
816
817enum bna_port_event {
818 PORT_E_START = 1,
819 PORT_E_STOP = 2,
820 PORT_E_FAIL = 3,
821 PORT_E_PAUSE_CFG = 4,
822 PORT_E_MTU_CFG = 5,
823 PORT_E_CHLD_STOPPED = 6,
824 PORT_E_FWRESP_PAUSE = 7,
825 PORT_E_FWRESP_MTU = 8
826};
827
828enum bna_port_state {
829 BNA_PORT_STOPPED = 1,
830 BNA_PORT_MTU_INIT_WAIT = 2,
831 BNA_PORT_PAUSE_INIT_WAIT = 3,
832 BNA_PORT_LAST_RESP_WAIT = 4,
833 BNA_PORT_STARTED = 5,
834 BNA_PORT_PAUSE_CFG_WAIT = 6,
835 BNA_PORT_RX_STOP_WAIT = 7,
836 BNA_PORT_MTU_CFG_WAIT = 8,
837 BNA_PORT_CHLD_STOP_WAIT = 9
838};
839
840bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
841 enum bna_port_event);
842bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
843 enum bna_port_event);
844bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
845 enum bna_port_event);
846bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
847 enum bna_port_event);
848bfa_fsm_state_decl(bna_port, started, struct bna_port,
849 enum bna_port_event);
850bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
851 enum bna_port_event);
852bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
853 enum bna_port_event);
854bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
855 enum bna_port_event);
856bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
857 enum bna_port_event);
858
859static struct bfa_sm_table port_sm_table[] = {
860 {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
861 {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
862 {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
863 {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
864 {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
865 {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
866 {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
867 {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
868 {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
869};
870
871static void
872bna_port_sm_stopped_entry(struct bna_port *port)
873{
874 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
875 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
876 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
877}
878
879static void
880bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
881{
882 switch (event) {
883 case PORT_E_START:
884 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
885 break;
886
887 case PORT_E_STOP:
888 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
889 break;
890
891 case PORT_E_FAIL:
892 /* No-op */
893 break;
894
895 case PORT_E_PAUSE_CFG:
896 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
897 break;
898
899 case PORT_E_MTU_CFG:
900 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
901 break;
902
903 case PORT_E_CHLD_STOPPED:
904 /**
905 * This event is received due to LLPort, Tx and Rx objects
906 * failing
907 */
908 /* No-op */
909 break;
910
911 case PORT_E_FWRESP_PAUSE:
912 case PORT_E_FWRESP_MTU:
913 /**
914 * These events are received due to flushing of mbox when
915 * device fails
916 */
917 /* No-op */
918 break;
919
920 default:
921 bfa_sm_fault(port->bna, event);
922 }
923}
924
925static void
926bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
927{
928 bna_fw_mtu_set(port);
929}
930
931static void
932bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
933{
934 switch (event) {
935 case PORT_E_STOP:
936 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
937 break;
938
939 case PORT_E_FAIL:
940 bfa_fsm_set_state(port, bna_port_sm_stopped);
941 break;
942
943 case PORT_E_PAUSE_CFG:
944 /* No-op */
945 break;
946
947 case PORT_E_MTU_CFG:
948 port->flags |= BNA_PORT_F_MTU_CHANGED;
949 break;
950
951 case PORT_E_FWRESP_MTU:
952 if (port->flags & BNA_PORT_F_MTU_CHANGED) {
953 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
954 bna_fw_mtu_set(port);
955 } else {
956 bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
957 }
958 break;
959
960 default:
961 bfa_sm_fault(port->bna, event);
962 }
963}
964
965static void
966bna_port_sm_pause_init_wait_entry(struct bna_port *port)
967{
968 bna_fw_pause_set(port);
969}
970
971static void
972bna_port_sm_pause_init_wait(struct bna_port *port,
973 enum bna_port_event event)
974{
975 switch (event) {
976 case PORT_E_STOP:
977 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
978 break;
979
980 case PORT_E_FAIL:
981 bfa_fsm_set_state(port, bna_port_sm_stopped);
982 break;
983
984 case PORT_E_PAUSE_CFG:
985 port->flags |= BNA_PORT_F_PAUSE_CHANGED;
986 break;
987
988 case PORT_E_MTU_CFG:
989 port->flags |= BNA_PORT_F_MTU_CHANGED;
990 break;
991
992 case PORT_E_FWRESP_PAUSE:
993 if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
994 port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
995 bna_fw_pause_set(port);
996 } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
997 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
998 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
999 } else {
1000 bfa_fsm_set_state(port, bna_port_sm_started);
1001 bna_port_chld_start(port);
1002 }
1003 break;
1004
1005 default:
1006 bfa_sm_fault(port->bna, event);
1007 }
1008}
1009
1010static void
1011bna_port_sm_last_resp_wait_entry(struct bna_port *port)
1012{
1013}
1014
1015static void
1016bna_port_sm_last_resp_wait(struct bna_port *port,
1017 enum bna_port_event event)
1018{
1019 switch (event) {
1020 case PORT_E_FAIL:
1021 case PORT_E_FWRESP_PAUSE:
1022 case PORT_E_FWRESP_MTU:
1023 bfa_fsm_set_state(port, bna_port_sm_stopped);
1024 break;
1025
1026 default:
1027 bfa_sm_fault(port->bna, event);
1028 }
1029}
1030
1031static void
1032bna_port_sm_started_entry(struct bna_port *port)
1033{
1034 /**
1035 * NOTE: Do not call bna_port_chld_start() here, since it will be
1036 * inadvertently called during pause_cfg_wait->started transition
1037 * as well
1038 */
1039 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
1040 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
1041}
1042
1043static void
1044bna_port_sm_started(struct bna_port *port,
1045 enum bna_port_event event)
1046{
1047 switch (event) {
1048 case PORT_E_STOP:
1049 bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
1050 break;
1051
1052 case PORT_E_FAIL:
1053 bfa_fsm_set_state(port, bna_port_sm_stopped);
1054 bna_port_chld_fail(port);
1055 break;
1056
1057 case PORT_E_PAUSE_CFG:
1058 bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
1059 break;
1060
1061 case PORT_E_MTU_CFG:
1062 bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
1063 break;
1064
1065 default:
1066 bfa_sm_fault(port->bna, event);
1067 }
1068}
1069
1070static void
1071bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
1072{
1073 bna_fw_pause_set(port);
1074}
1075
1076static void
1077bna_port_sm_pause_cfg_wait(struct bna_port *port,
1078 enum bna_port_event event)
1079{
1080 switch (event) {
1081 case PORT_E_FAIL:
1082 bfa_fsm_set_state(port, bna_port_sm_stopped);
1083 bna_port_chld_fail(port);
1084 break;
1085
1086 case PORT_E_FWRESP_PAUSE:
1087 bfa_fsm_set_state(port, bna_port_sm_started);
1088 break;
1089
1090 default:
1091 bfa_sm_fault(port->bna, event);
1092 }
1093}
1094
1095static void
1096bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
1097{
1098 bna_port_rx_stop(port);
1099}
1100
1101static void
1102bna_port_sm_rx_stop_wait(struct bna_port *port,
1103 enum bna_port_event event)
1104{
1105 switch (event) {
1106 case PORT_E_FAIL:
1107 bfa_fsm_set_state(port, bna_port_sm_stopped);
1108 bna_port_chld_fail(port);
1109 break;
1110
1111 case PORT_E_CHLD_STOPPED:
1112 bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
1113 break;
1114
1115 default:
1116 bfa_sm_fault(port->bna, event);
1117 }
1118}
1119
1120static void
1121bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
1122{
1123 bna_fw_mtu_set(port);
1124}
1125
1126static void
1127bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
1128{
1129 switch (event) {
1130 case PORT_E_FAIL:
1131 bfa_fsm_set_state(port, bna_port_sm_stopped);
1132 bna_port_chld_fail(port);
1133 break;
1134
1135 case PORT_E_FWRESP_MTU:
1136 bfa_fsm_set_state(port, bna_port_sm_started);
1137 bna_port_rx_start(port);
1138 break;
1139
1140 default:
1141 bfa_sm_fault(port->bna, event);
1142 }
1143}
1144
1145static void
1146bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
1147{
1148 bna_port_chld_stop(port);
1149}
1150
1151static void
1152bna_port_sm_chld_stop_wait(struct bna_port *port,
1153 enum bna_port_event event)
1154{
1155 switch (event) {
1156 case PORT_E_FAIL:
1157 bfa_fsm_set_state(port, bna_port_sm_stopped);
1158 bna_port_chld_fail(port);
1159 break;
1160
1161 case PORT_E_CHLD_STOPPED:
1162 bfa_fsm_set_state(port, bna_port_sm_stopped);
1163 break;
1164
1165 default:
1166 bfa_sm_fault(port->bna, event);
1167 }
1168}
1169
1170static void
1171bna_fw_pause_set(struct bna_port *port)
1172{
1173 struct bfi_ll_set_pause_req ll_req;
1174
1175 memset(&ll_req, 0, sizeof(ll_req));
1176 ll_req.mh.msg_class = BFI_MC_LL;
1177 ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
1178 ll_req.mh.mtag.h2i.lpu_id = 0;
1179
1180 ll_req.tx_pause = port->pause_config.tx_pause;
1181 ll_req.rx_pause = port->pause_config.rx_pause;
1182
1183 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1184 bna_fw_cb_pause_set, port);
1185
1186 bna_mbox_send(port->bna, &port->mbox_qe);
1187}
1188
1189static void
1190bna_fw_cb_pause_set(void *arg, int status)
1191{
1192 struct bna_port *port = (struct bna_port *)arg;
1193
1194 bfa_q_qe_init(&port->mbox_qe.qe);
1195 bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
1196}
1197
1198void
1199bna_fw_mtu_set(struct bna_port *port)
1200{
1201 struct bfi_ll_mtu_info_req ll_req;
1202
1203 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
1204 ll_req.mtu = htons((u16)port->mtu);
1205
1206 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1207 bna_fw_cb_mtu_set, port);
1208 bna_mbox_send(port->bna, &port->mbox_qe);
1209}
1210
1211void
1212bna_fw_cb_mtu_set(void *arg, int status)
1213{
1214 struct bna_port *port = (struct bna_port *)arg;
1215
1216 bfa_q_qe_init(&port->mbox_qe.qe);
1217 bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
1218}
1219
1220static void
1221bna_port_cb_chld_stopped(void *arg)
1222{
1223 struct bna_port *port = (struct bna_port *)arg;
1224
1225 bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
1226}
1227
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001228static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001229bna_port_init(struct bna_port *port, struct bna *bna)
1230{
1231 port->bna = bna;
1232 port->flags = 0;
1233 port->mtu = 0;
1234 port->type = BNA_PORT_T_REGULAR;
1235
1236 port->link_cbfn = bnad_cb_port_link_status;
1237
1238 port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
1239 port->chld_stop_wc.wc_cbarg = port;
1240 port->chld_stop_wc.wc_count = 0;
1241
1242 port->stop_cbfn = NULL;
1243 port->stop_cbarg = NULL;
1244
1245 port->pause_cbfn = NULL;
1246
1247 port->mtu_cbfn = NULL;
1248
1249 bfa_q_qe_init(&port->mbox_qe.qe);
1250
1251 bfa_fsm_set_state(port, bna_port_sm_stopped);
1252
1253 bna_llport_init(&port->llport, bna);
1254}
1255
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001256static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001257bna_port_uninit(struct bna_port *port)
1258{
1259 bna_llport_uninit(&port->llport);
1260
1261 port->flags = 0;
1262
1263 port->bna = NULL;
1264}
1265
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001266static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001267bna_port_state_get(struct bna_port *port)
1268{
1269 return bfa_sm_to_state(port_sm_table, port->fsm);
1270}
1271
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001272static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001273bna_port_start(struct bna_port *port)
1274{
1275 port->flags |= BNA_PORT_F_DEVICE_READY;
1276 if (port->flags & BNA_PORT_F_ENABLED)
1277 bfa_fsm_send_event(port, PORT_E_START);
1278}
1279
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001280static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001281bna_port_stop(struct bna_port *port)
1282{
1283 port->stop_cbfn = bna_device_cb_port_stopped;
1284 port->stop_cbarg = &port->bna->device;
1285
1286 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1287 bfa_fsm_send_event(port, PORT_E_STOP);
1288}
1289
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001290static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001291bna_port_fail(struct bna_port *port)
1292{
1293 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1294 bfa_fsm_send_event(port, PORT_E_FAIL);
1295}
1296
1297void
1298bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
1299{
1300 bfa_wc_down(&port->chld_stop_wc);
1301}
1302
1303void
1304bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
1305{
1306 bfa_wc_down(&port->chld_stop_wc);
1307}
1308
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001309int
1310bna_port_mtu_get(struct bna_port *port)
1311{
1312 return port->mtu;
1313}
1314
1315void
1316bna_port_enable(struct bna_port *port)
1317{
1318 if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
1319 return;
1320
1321 port->flags |= BNA_PORT_F_ENABLED;
1322
1323 if (port->flags & BNA_PORT_F_DEVICE_READY)
1324 bfa_fsm_send_event(port, PORT_E_START);
1325}
1326
1327void
1328bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
1329 void (*cbfn)(void *, enum bna_cb_status))
1330{
1331 if (type == BNA_SOFT_CLEANUP) {
1332 (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
1333 return;
1334 }
1335
1336 port->stop_cbfn = cbfn;
1337 port->stop_cbarg = port->bna->bnad;
1338
1339 port->flags &= ~BNA_PORT_F_ENABLED;
1340
1341 bfa_fsm_send_event(port, PORT_E_STOP);
1342}
1343
1344void
1345bna_port_pause_config(struct bna_port *port,
1346 struct bna_pause_config *pause_config,
1347 void (*cbfn)(struct bnad *, enum bna_cb_status))
1348{
1349 port->pause_config = *pause_config;
1350
1351 port->pause_cbfn = cbfn;
1352
1353 bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
1354}
1355
1356void
1357bna_port_mtu_set(struct bna_port *port, int mtu,
1358 void (*cbfn)(struct bnad *, enum bna_cb_status))
1359{
1360 port->mtu = mtu;
1361
1362 port->mtu_cbfn = cbfn;
1363
1364 bfa_fsm_send_event(port, PORT_E_MTU_CFG);
1365}
1366
1367void
1368bna_port_mac_get(struct bna_port *port, mac_t *mac)
1369{
Rasesh Mody8a891422010-08-25 23:00:27 -07001370 *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc);
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001371}
1372
1373/**
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001374 * DEVICE
1375 */
1376#define enable_mbox_intr(_device)\
1377do {\
1378 u32 intr_status;\
1379 bna_intr_status_get((_device)->bna, intr_status);\
1380 bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
1381 bna_mbox_intr_enable((_device)->bna);\
1382} while (0)
1383
1384#define disable_mbox_intr(_device)\
1385do {\
1386 bna_mbox_intr_disable((_device)->bna);\
1387 bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
1388} while (0)
1389
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001390static const struct bna_chip_regs_offset reg_offset[] =
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001391{{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
1392 HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
1393{HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
1394 HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
1395{HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
1396 HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
1397{HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
1398 HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
1399};
1400
1401enum bna_device_event {
1402 DEVICE_E_ENABLE = 1,
1403 DEVICE_E_DISABLE = 2,
1404 DEVICE_E_IOC_READY = 3,
1405 DEVICE_E_IOC_FAILED = 4,
1406 DEVICE_E_IOC_DISABLED = 5,
1407 DEVICE_E_IOC_RESET = 6,
1408 DEVICE_E_PORT_STOPPED = 7,
1409};
1410
1411enum bna_device_state {
1412 BNA_DEVICE_STOPPED = 1,
1413 BNA_DEVICE_IOC_READY_WAIT = 2,
1414 BNA_DEVICE_READY = 3,
1415 BNA_DEVICE_PORT_STOP_WAIT = 4,
1416 BNA_DEVICE_IOC_DISABLE_WAIT = 5,
1417 BNA_DEVICE_FAILED = 6
1418};
1419
1420bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
1421 enum bna_device_event);
1422bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
1423 enum bna_device_event);
1424bfa_fsm_state_decl(bna_device, ready, struct bna_device,
1425 enum bna_device_event);
1426bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
1427 enum bna_device_event);
1428bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
1429 enum bna_device_event);
1430bfa_fsm_state_decl(bna_device, failed, struct bna_device,
1431 enum bna_device_event);
1432
1433static struct bfa_sm_table device_sm_table[] = {
1434 {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
1435 {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
1436 {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
1437 {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
1438 {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
1439 {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
1440};
1441
1442static void
1443bna_device_sm_stopped_entry(struct bna_device *device)
1444{
1445 if (device->stop_cbfn)
1446 device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
1447
1448 device->stop_cbfn = NULL;
1449 device->stop_cbarg = NULL;
1450}
1451
1452static void
1453bna_device_sm_stopped(struct bna_device *device,
1454 enum bna_device_event event)
1455{
1456 switch (event) {
1457 case DEVICE_E_ENABLE:
1458 if (device->intr_type == BNA_INTR_T_MSIX)
1459 bna_mbox_msix_idx_set(device);
Rasesh Mody8a891422010-08-25 23:00:27 -07001460 bfa_nw_ioc_enable(&device->ioc);
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001461 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1462 break;
1463
1464 case DEVICE_E_DISABLE:
1465 bfa_fsm_set_state(device, bna_device_sm_stopped);
1466 break;
1467
1468 case DEVICE_E_IOC_RESET:
1469 enable_mbox_intr(device);
1470 break;
1471
1472 case DEVICE_E_IOC_FAILED:
1473 bfa_fsm_set_state(device, bna_device_sm_failed);
1474 break;
1475
1476 default:
1477 bfa_sm_fault(device->bna, event);
1478 }
1479}
1480
1481static void
1482bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
1483{
1484 /**
1485 * Do not call bfa_ioc_enable() here. It must be called in the
1486 * previous state due to failed -> ioc_ready_wait transition.
1487 */
1488}
1489
1490static void
1491bna_device_sm_ioc_ready_wait(struct bna_device *device,
1492 enum bna_device_event event)
1493{
1494 switch (event) {
1495 case DEVICE_E_DISABLE:
1496 if (device->ready_cbfn)
1497 device->ready_cbfn(device->ready_cbarg,
1498 BNA_CB_INTERRUPT);
1499 device->ready_cbfn = NULL;
1500 device->ready_cbarg = NULL;
1501 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1502 break;
1503
1504 case DEVICE_E_IOC_READY:
1505 bfa_fsm_set_state(device, bna_device_sm_ready);
1506 break;
1507
1508 case DEVICE_E_IOC_FAILED:
1509 bfa_fsm_set_state(device, bna_device_sm_failed);
1510 break;
1511
1512 case DEVICE_E_IOC_RESET:
1513 enable_mbox_intr(device);
1514 break;
1515
1516 default:
1517 bfa_sm_fault(device->bna, event);
1518 }
1519}
1520
1521static void
1522bna_device_sm_ready_entry(struct bna_device *device)
1523{
1524 bna_mbox_mod_start(&device->bna->mbox_mod);
1525 bna_port_start(&device->bna->port);
1526
1527 if (device->ready_cbfn)
1528 device->ready_cbfn(device->ready_cbarg,
1529 BNA_CB_SUCCESS);
1530 device->ready_cbfn = NULL;
1531 device->ready_cbarg = NULL;
1532}
1533
1534static void
1535bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
1536{
1537 switch (event) {
1538 case DEVICE_E_DISABLE:
1539 bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
1540 break;
1541
1542 case DEVICE_E_IOC_FAILED:
1543 bfa_fsm_set_state(device, bna_device_sm_failed);
1544 break;
1545
1546 default:
1547 bfa_sm_fault(device->bna, event);
1548 }
1549}
1550
1551static void
1552bna_device_sm_port_stop_wait_entry(struct bna_device *device)
1553{
1554 bna_port_stop(&device->bna->port);
1555}
1556
1557static void
1558bna_device_sm_port_stop_wait(struct bna_device *device,
1559 enum bna_device_event event)
1560{
1561 switch (event) {
1562 case DEVICE_E_PORT_STOPPED:
1563 bna_mbox_mod_stop(&device->bna->mbox_mod);
1564 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1565 break;
1566
1567 case DEVICE_E_IOC_FAILED:
1568 disable_mbox_intr(device);
1569 bna_port_fail(&device->bna->port);
1570 break;
1571
1572 default:
1573 bfa_sm_fault(device->bna, event);
1574 }
1575}
1576
1577static void
1578bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
1579{
Rasesh Mody8a891422010-08-25 23:00:27 -07001580 bfa_nw_ioc_disable(&device->ioc);
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001581}
1582
1583static void
1584bna_device_sm_ioc_disable_wait(struct bna_device *device,
1585 enum bna_device_event event)
1586{
1587 switch (event) {
1588 case DEVICE_E_IOC_DISABLED:
1589 disable_mbox_intr(device);
1590 bfa_fsm_set_state(device, bna_device_sm_stopped);
1591 break;
1592
1593 default:
1594 bfa_sm_fault(device->bna, event);
1595 }
1596}
1597
1598static void
1599bna_device_sm_failed_entry(struct bna_device *device)
1600{
1601 disable_mbox_intr(device);
1602 bna_port_fail(&device->bna->port);
1603 bna_mbox_mod_stop(&device->bna->mbox_mod);
1604
1605 if (device->ready_cbfn)
1606 device->ready_cbfn(device->ready_cbarg,
1607 BNA_CB_FAIL);
1608 device->ready_cbfn = NULL;
1609 device->ready_cbarg = NULL;
1610}
1611
1612static void
1613bna_device_sm_failed(struct bna_device *device,
1614 enum bna_device_event event)
1615{
1616 switch (event) {
1617 case DEVICE_E_DISABLE:
1618 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1619 break;
1620
1621 case DEVICE_E_IOC_RESET:
1622 enable_mbox_intr(device);
1623 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1624 break;
1625
1626 default:
1627 bfa_sm_fault(device->bna, event);
1628 }
1629}
1630
1631/* IOC callback functions */
1632
1633static void
1634bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
1635{
1636 struct bna_device *device = (struct bna_device *)dev;
1637
1638 if (error)
1639 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1640 else
1641 bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
1642}
1643
1644static void
1645bna_device_cb_iocll_disabled(void *dev)
1646{
1647 struct bna_device *device = (struct bna_device *)dev;
1648
1649 bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
1650}
1651
1652static void
1653bna_device_cb_iocll_failed(void *dev)
1654{
1655 struct bna_device *device = (struct bna_device *)dev;
1656
1657 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1658}
1659
1660static void
1661bna_device_cb_iocll_reset(void *dev)
1662{
1663 struct bna_device *device = (struct bna_device *)dev;
1664
1665 bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
1666}
1667
1668static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
1669 bna_device_cb_iocll_ready,
1670 bna_device_cb_iocll_disabled,
1671 bna_device_cb_iocll_failed,
1672 bna_device_cb_iocll_reset
1673};
1674
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001675/* device */
1676static void
1677bna_adv_device_init(struct bna_device *device, struct bna *bna,
1678 struct bna_res_info *res_info)
1679{
1680 u8 *kva;
1681 u64 dma;
1682
1683 device->bna = bna;
1684
1685 kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
1686
1687 /**
1688 * Attach common modules (Diag, SFP, CEE, Port) and claim respective
1689 * DMA memory.
1690 */
1691 BNA_GET_DMA_ADDR(
1692 &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
1693 kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
1694
1695 bfa_nw_cee_attach(&bna->cee, &device->ioc, bna);
1696 bfa_nw_cee_mem_claim(&bna->cee, kva, dma);
1697 kva += bfa_nw_cee_meminfo();
1698 dma += bfa_nw_cee_meminfo();
1699
1700}
1701
1702static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001703bna_device_init(struct bna_device *device, struct bna *bna,
1704 struct bna_res_info *res_info)
1705{
1706 u64 dma;
1707
1708 device->bna = bna;
1709
1710 /**
1711 * Attach IOC and claim:
1712 * 1. DMA memory for IOC attributes
1713 * 2. Kernel memory for FW trace
1714 */
Rasesh Mody8a891422010-08-25 23:00:27 -07001715 bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
1716 bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001717
1718 BNA_GET_DMA_ADDR(
1719 &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
Rasesh Mody8a891422010-08-25 23:00:27 -07001720 bfa_nw_ioc_mem_claim(&device->ioc,
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001721 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
1722 dma);
1723
1724 bna_adv_device_init(device, bna, res_info);
1725 /*
1726 * Initialize mbox_mod only after IOC, so that mbox handler
1727 * registration goes through
1728 */
1729 device->intr_type =
1730 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
1731 device->vector =
1732 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
1733 bna_mbox_mod_init(&bna->mbox_mod, bna);
1734
1735 device->ready_cbfn = device->stop_cbfn = NULL;
1736 device->ready_cbarg = device->stop_cbarg = NULL;
1737
1738 bfa_fsm_set_state(device, bna_device_sm_stopped);
1739}
1740
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001741static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001742bna_device_uninit(struct bna_device *device)
1743{
1744 bna_mbox_mod_uninit(&device->bna->mbox_mod);
1745
Rasesh Mody8a891422010-08-25 23:00:27 -07001746 bfa_nw_ioc_detach(&device->ioc);
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001747
1748 device->bna = NULL;
1749}
1750
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001751static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001752bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
1753{
1754 struct bna_device *device = (struct bna_device *)arg;
1755
1756 bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
1757}
1758
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001759static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001760bna_device_status_get(struct bna_device *device)
1761{
Eric Dumazet807540b2010-09-23 05:40:09 +00001762 return device->fsm == (bfa_fsm_t)bna_device_sm_ready;
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001763}
1764
1765void
1766bna_device_enable(struct bna_device *device)
1767{
1768 if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
1769 bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
1770 return;
1771 }
1772
1773 device->ready_cbfn = bnad_cb_device_enabled;
1774 device->ready_cbarg = device->bna->bnad;
1775
1776 bfa_fsm_send_event(device, DEVICE_E_ENABLE);
1777}
1778
1779void
1780bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
1781{
1782 if (type == BNA_SOFT_CLEANUP) {
1783 bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
1784 return;
1785 }
1786
1787 device->stop_cbfn = bnad_cb_device_disabled;
1788 device->stop_cbarg = device->bna->bnad;
1789
1790 bfa_fsm_send_event(device, DEVICE_E_DISABLE);
1791}
1792
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001793static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001794bna_device_state_get(struct bna_device *device)
1795{
1796 return bfa_sm_to_state(device_sm_table, device->fsm);
1797}
1798
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001799const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001800 {12, 12},
1801 {6, 10},
1802 {5, 10},
1803 {4, 8},
1804 {3, 6},
1805 {3, 6},
1806 {2, 4},
1807 {1, 2},
1808};
1809
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001810/* utils */
1811
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00001812static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001813bna_adv_res_req(struct bna_res_info *res_info)
1814{
1815 /* DMA memory for COMMON_MODULE */
1816 res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
1817 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1818 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
1819 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
Rasesh Mody8a891422010-08-25 23:00:27 -07001820 bfa_nw_cee_meminfo(), PAGE_SIZE);
Rasesh Mody8b230ed2010-08-23 20:24:12 -07001821
1822 /* Virtual memory for retreiving fw_trc */
1823 res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
1824 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1825 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
1826 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
1827
1828 /* DMA memory for retreiving stats */
1829 res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
1830 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1831 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
1832 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
1833 ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
1834
1835 /* Virtual memory for soft stats */
1836 res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
1837 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1838 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
1839 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
1840 sizeof(struct bna_sw_stats);
1841}
1842
1843static void
1844bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
1845{
1846 struct bna_tx *tx;
1847 struct bna_txq *txq;
1848 struct bna_rx *rx;
1849 struct bna_rxp *rxp;
1850 struct list_head *qe;
1851 struct list_head *txq_qe;
1852 struct list_head *rxp_qe;
1853 struct list_head *mac_qe;
1854 int i;
1855
1856 sw_stats->device_state = bna_device_state_get(&bna->device);
1857 sw_stats->port_state = bna_port_state_get(&bna->port);
1858 sw_stats->port_flags = bna->port.flags;
1859 sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
1860 sw_stats->priority = bna->port.priority;
1861
1862 i = 0;
1863 list_for_each(qe, &bna->tx_mod.tx_active_q) {
1864 tx = (struct bna_tx *)qe;
1865 sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
1866 sw_stats->tx_stats[i].tx_flags = tx->flags;
1867
1868 sw_stats->tx_stats[i].num_txqs = 0;
1869 sw_stats->tx_stats[i].txq_bmap[0] = 0;
1870 sw_stats->tx_stats[i].txq_bmap[1] = 0;
1871 list_for_each(txq_qe, &tx->txq_q) {
1872 txq = (struct bna_txq *)txq_qe;
1873 if (txq->txq_id < 32)
1874 sw_stats->tx_stats[i].txq_bmap[0] |=
1875 ((u32)1 << txq->txq_id);
1876 else
1877 sw_stats->tx_stats[i].txq_bmap[1] |=
1878 ((u32)
1879 1 << (txq->txq_id - 32));
1880 sw_stats->tx_stats[i].num_txqs++;
1881 }
1882
1883 sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
1884
1885 i++;
1886 }
1887 sw_stats->num_active_tx = i;
1888
1889 i = 0;
1890 list_for_each(qe, &bna->rx_mod.rx_active_q) {
1891 rx = (struct bna_rx *)qe;
1892 sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
1893 sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
1894
1895 sw_stats->rx_stats[i].num_rxps = 0;
1896 sw_stats->rx_stats[i].num_rxqs = 0;
1897 sw_stats->rx_stats[i].rxq_bmap[0] = 0;
1898 sw_stats->rx_stats[i].rxq_bmap[1] = 0;
1899 sw_stats->rx_stats[i].cq_bmap[0] = 0;
1900 sw_stats->rx_stats[i].cq_bmap[1] = 0;
1901 list_for_each(rxp_qe, &rx->rxp_q) {
1902 rxp = (struct bna_rxp *)rxp_qe;
1903
1904 sw_stats->rx_stats[i].num_rxqs += 1;
1905
1906 if (rxp->type == BNA_RXP_SINGLE) {
1907 if (rxp->rxq.single.only->rxq_id < 32) {
1908 sw_stats->rx_stats[i].rxq_bmap[0] |=
1909 ((u32)1 <<
1910 rxp->rxq.single.only->rxq_id);
1911 } else {
1912 sw_stats->rx_stats[i].rxq_bmap[1] |=
1913 ((u32)1 <<
1914 (rxp->rxq.single.only->rxq_id - 32));
1915 }
1916 } else {
1917 if (rxp->rxq.slr.large->rxq_id < 32) {
1918 sw_stats->rx_stats[i].rxq_bmap[0] |=
1919 ((u32)1 <<
1920 rxp->rxq.slr.large->rxq_id);
1921 } else {
1922 sw_stats->rx_stats[i].rxq_bmap[1] |=
1923 ((u32)1 <<
1924 (rxp->rxq.slr.large->rxq_id - 32));
1925 }
1926
1927 if (rxp->rxq.slr.small->rxq_id < 32) {
1928 sw_stats->rx_stats[i].rxq_bmap[0] |=
1929 ((u32)1 <<
1930 rxp->rxq.slr.small->rxq_id);
1931 } else {
1932 sw_stats->rx_stats[i].rxq_bmap[1] |=
1933 ((u32)1 <<
1934 (rxp->rxq.slr.small->rxq_id - 32));
1935 }
1936 sw_stats->rx_stats[i].num_rxqs += 1;
1937 }
1938
1939 if (rxp->cq.cq_id < 32)
1940 sw_stats->rx_stats[i].cq_bmap[0] |=
1941 (1 << rxp->cq.cq_id);
1942 else
1943 sw_stats->rx_stats[i].cq_bmap[1] |=
1944 (1 << (rxp->cq.cq_id - 32));
1945
1946 sw_stats->rx_stats[i].num_rxps++;
1947 }
1948
1949 sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
1950 sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
1951 sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
1952
1953 sw_stats->rx_stats[i].num_active_ucast = 0;
1954 if (rx->rxf.ucast_active_mac)
1955 sw_stats->rx_stats[i].num_active_ucast++;
1956 list_for_each(mac_qe, &rx->rxf.ucast_active_q)
1957 sw_stats->rx_stats[i].num_active_ucast++;
1958
1959 sw_stats->rx_stats[i].num_active_mcast = 0;
1960 list_for_each(mac_qe, &rx->rxf.mcast_active_q)
1961 sw_stats->rx_stats[i].num_active_mcast++;
1962
1963 sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
1964 sw_stats->rx_stats[i].vlan_filter_status =
1965 rx->rxf.vlan_filter_status;
1966 memcpy(sw_stats->rx_stats[i].vlan_filter_table,
1967 rx->rxf.vlan_filter_table,
1968 sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
1969
1970 sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
1971 sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
1972
1973 i++;
1974 }
1975 sw_stats->num_active_rx = i;
1976}
1977
1978static void
1979bna_fw_cb_stats_get(void *arg, int status)
1980{
1981 struct bna *bna = (struct bna *)arg;
1982 u64 *p_stats;
1983 int i, count;
1984 int rxf_count, txf_count;
1985 u64 rxf_bmap, txf_bmap;
1986
1987 bfa_q_qe_init(&bna->mbox_qe.qe);
1988
1989 if (status == 0) {
1990 p_stats = (u64 *)bna->stats.hw_stats;
1991 count = sizeof(struct bfi_ll_stats) / sizeof(u64);
1992 for (i = 0; i < count; i++)
1993 p_stats[i] = cpu_to_be64(p_stats[i]);
1994
1995 rxf_count = 0;
1996 rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
1997 ((u64)bna->stats.rxf_bmap[1] << 32);
1998 for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
1999 if (rxf_bmap & ((u64)1 << i))
2000 rxf_count++;
2001
2002 txf_count = 0;
2003 txf_bmap = (u64)bna->stats.txf_bmap[0] |
2004 ((u64)bna->stats.txf_bmap[1] << 32);
2005 for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
2006 if (txf_bmap & ((u64)1 << i))
2007 txf_count++;
2008
2009 p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
2010 ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
2011 txf_count * sizeof(struct bfi_ll_stats_txf))/
2012 sizeof(u64));
2013
2014 /* Populate the TXF stats from the firmware DMAed copy */
2015 for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
2016 if (txf_bmap & ((u64)1 << i)) {
2017 p_stats -= sizeof(struct bfi_ll_stats_txf)/
2018 sizeof(u64);
2019 memcpy(&bna->stats.hw_stats->txf_stats[i],
2020 p_stats,
2021 sizeof(struct bfi_ll_stats_txf));
2022 }
2023
2024 /* Populate the RXF stats from the firmware DMAed copy */
2025 for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
2026 if (rxf_bmap & ((u64)1 << i)) {
2027 p_stats -= sizeof(struct bfi_ll_stats_rxf)/
2028 sizeof(u64);
2029 memcpy(&bna->stats.hw_stats->rxf_stats[i],
2030 p_stats,
2031 sizeof(struct bfi_ll_stats_rxf));
2032 }
2033
2034 bna_sw_stats_get(bna, bna->stats.sw_stats);
2035 bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
2036 } else
2037 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
2038}
2039
2040static void
2041bna_fw_stats_get(struct bna *bna)
2042{
2043 struct bfi_ll_stats_req ll_req;
2044
2045 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
2046 ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
2047
2048 ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
2049 ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
2050 ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
2051 ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
2052
2053 ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
2054 ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
2055
2056 bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
2057 bna_fw_cb_stats_get, bna);
2058 bna_mbox_send(bna, &bna->mbox_qe);
2059
2060 bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
2061 bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
2062 bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
2063 bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
2064}
2065
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002066void
2067bna_stats_get(struct bna *bna)
2068{
2069 if (bna_device_status_get(&bna->device))
2070 bna_fw_stats_get(bna);
2071 else
2072 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
2073}
2074
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002075/* IB */
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002076static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002077bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
2078{
2079 ib->ib_config.coalescing_timeo = coalescing_timeo;
2080
2081 if (ib->start_count)
2082 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
2083 (u32)ib->ib_config.coalescing_timeo, 0);
2084}
2085
2086/* RxF */
2087void
2088bna_rxf_adv_init(struct bna_rxf *rxf,
2089 struct bna_rx *rx,
2090 struct bna_rx_config *q_config)
2091{
2092 switch (q_config->rxp_type) {
2093 case BNA_RXP_SINGLE:
2094 /* No-op */
2095 break;
2096 case BNA_RXP_SLR:
2097 rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
2098 break;
2099 case BNA_RXP_HDS:
2100 rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
2101 rxf->hds_cfg.header_size =
2102 q_config->hds_config.header_size;
2103 rxf->forced_offset = 0;
2104 break;
2105 default:
2106 break;
2107 }
2108
2109 if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
2110 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
2111 rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
2112 rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
2113 memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
2114 &q_config->rss_config.toeplitz_hash_key[0],
2115 sizeof(rxf->rss_cfg.toeplitz_hash_key));
2116 }
2117}
2118
2119static void
2120rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
2121{
2122 struct bfi_ll_rxf_req req;
2123
2124 bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
2125
2126 req.rxf_id = rxf->rxf_id;
2127 req.enable = status;
2128
2129 bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
2130 rxf_cb_cam_fltr_mbox_cmd, rxf);
2131
2132 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
2133}
2134
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002135static void
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002136__rxf_default_function_config(struct bna_rxf *rxf, enum bna_status status)
2137{
2138 struct bna_rx_fndb_ram *rx_fndb_ram;
2139 u32 ctrl_flags;
2140 int i;
2141
2142 rx_fndb_ram = (struct bna_rx_fndb_ram *)
2143 BNA_GET_MEM_BASE_ADDR(rxf->rx->bna->pcidev.pci_bar_kva,
2144 RX_FNDB_RAM_BASE_OFFSET);
2145
2146 for (i = 0; i < BFI_MAX_RXF; i++) {
2147 if (status == BNA_STATUS_T_ENABLED) {
2148 if (i == rxf->rxf_id)
2149 continue;
2150
2151 ctrl_flags =
2152 readl(&rx_fndb_ram[i].control_flags);
2153 ctrl_flags |= BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2154 writel(ctrl_flags,
2155 &rx_fndb_ram[i].control_flags);
2156 } else {
2157 ctrl_flags =
2158 readl(&rx_fndb_ram[i].control_flags);
2159 ctrl_flags &= ~BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2160 writel(ctrl_flags,
2161 &rx_fndb_ram[i].control_flags);
2162 }
2163 }
2164}
2165
2166int
2167rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
2168{
2169 struct bna_mac *mac = NULL;
2170 struct list_head *qe;
2171
2172 /* Add additional MAC entries */
2173 if (!list_empty(&rxf->ucast_pending_add_q)) {
2174 bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
2175 bfa_q_qe_init(qe);
2176 mac = (struct bna_mac *)qe;
2177 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
2178 list_add_tail(&mac->qe, &rxf->ucast_active_q);
2179 return 1;
2180 }
2181
2182 /* Delete MAC addresses previousely added */
2183 if (!list_empty(&rxf->ucast_pending_del_q)) {
2184 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2185 bfa_q_qe_init(qe);
2186 mac = (struct bna_mac *)qe;
2187 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2188 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2189 return 1;
2190 }
2191
2192 return 0;
2193}
2194
2195int
2196rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
2197{
2198 struct bna *bna = rxf->rx->bna;
2199
2200 /* Enable/disable promiscuous mode */
2201 if (is_promisc_enable(rxf->rxmode_pending,
2202 rxf->rxmode_pending_bitmask)) {
2203 /* move promisc configuration from pending -> active */
2204 promisc_inactive(rxf->rxmode_pending,
2205 rxf->rxmode_pending_bitmask);
2206 rxf->rxmode_active |= BNA_RXMODE_PROMISC;
2207
2208 /* Disable VLAN filter to allow all VLANs */
2209 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2210 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2211 BNA_STATUS_T_ENABLED);
2212 return 1;
2213 } else if (is_promisc_disable(rxf->rxmode_pending,
2214 rxf->rxmode_pending_bitmask)) {
2215 /* move promisc configuration from pending -> active */
2216 promisc_inactive(rxf->rxmode_pending,
2217 rxf->rxmode_pending_bitmask);
2218 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2219 bna->rxf_promisc_id = BFI_MAX_RXF;
2220
2221 /* Revert VLAN filter */
2222 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2223 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2224 BNA_STATUS_T_DISABLED);
2225 return 1;
2226 }
2227
2228 return 0;
2229}
2230
2231int
2232rxf_process_packet_filter_default(struct bna_rxf *rxf)
2233{
2234 struct bna *bna = rxf->rx->bna;
2235
2236 /* Enable/disable default mode */
2237 if (is_default_enable(rxf->rxmode_pending,
2238 rxf->rxmode_pending_bitmask)) {
2239 /* move default configuration from pending -> active */
2240 default_inactive(rxf->rxmode_pending,
2241 rxf->rxmode_pending_bitmask);
2242 rxf->rxmode_active |= BNA_RXMODE_DEFAULT;
2243
2244 /* Disable VLAN filter to allow all VLANs */
2245 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2246 /* Redirect all other RxF vlan filtering to this one */
2247 __rxf_default_function_config(rxf, BNA_STATUS_T_ENABLED);
2248 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2249 BNA_STATUS_T_ENABLED);
2250 return 1;
2251 } else if (is_default_disable(rxf->rxmode_pending,
2252 rxf->rxmode_pending_bitmask)) {
2253 /* move default configuration from pending -> active */
2254 default_inactive(rxf->rxmode_pending,
2255 rxf->rxmode_pending_bitmask);
2256 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2257 bna->rxf_default_id = BFI_MAX_RXF;
2258
2259 /* Revert VLAN filter */
2260 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2261 /* Stop RxF vlan filter table redirection */
2262 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2263 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2264 BNA_STATUS_T_DISABLED);
2265 return 1;
2266 }
2267
2268 return 0;
2269}
2270
2271int
2272rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
2273{
2274 /* Enable/disable allmulti mode */
2275 if (is_allmulti_enable(rxf->rxmode_pending,
2276 rxf->rxmode_pending_bitmask)) {
2277 /* move allmulti configuration from pending -> active */
2278 allmulti_inactive(rxf->rxmode_pending,
2279 rxf->rxmode_pending_bitmask);
2280 rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
2281
2282 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2283 BNA_STATUS_T_ENABLED);
2284 return 1;
2285 } else if (is_allmulti_disable(rxf->rxmode_pending,
2286 rxf->rxmode_pending_bitmask)) {
2287 /* move allmulti configuration from pending -> active */
2288 allmulti_inactive(rxf->rxmode_pending,
2289 rxf->rxmode_pending_bitmask);
2290 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2291
2292 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2293 BNA_STATUS_T_DISABLED);
2294 return 1;
2295 }
2296
2297 return 0;
2298}
2299
2300int
2301rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
2302{
2303 struct bna_mac *mac = NULL;
2304 struct list_head *qe;
2305
2306 /* 1. delete pending ucast entries */
2307 if (!list_empty(&rxf->ucast_pending_del_q)) {
2308 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2309 bfa_q_qe_init(qe);
2310 mac = (struct bna_mac *)qe;
2311 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2312 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2313 return 1;
2314 }
2315
2316 /* 2. clear active ucast entries; move them to pending_add_q */
2317 if (!list_empty(&rxf->ucast_active_q)) {
2318 bfa_q_deq(&rxf->ucast_active_q, &qe);
2319 bfa_q_qe_init(qe);
2320 mac = (struct bna_mac *)qe;
2321 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2322 list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
2323 return 1;
2324 }
2325
2326 return 0;
2327}
2328
2329int
2330rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
2331{
2332 struct bna *bna = rxf->rx->bna;
2333
2334 /* 6. Execute pending promisc mode disable command */
2335 if (is_promisc_disable(rxf->rxmode_pending,
2336 rxf->rxmode_pending_bitmask)) {
2337 /* move promisc configuration from pending -> active */
2338 promisc_inactive(rxf->rxmode_pending,
2339 rxf->rxmode_pending_bitmask);
2340 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2341 bna->rxf_promisc_id = BFI_MAX_RXF;
2342
2343 /* Revert VLAN filter */
2344 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2345 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2346 BNA_STATUS_T_DISABLED);
2347 return 1;
2348 }
2349
2350 /* 7. Clear active promisc mode; move it to pending enable */
2351 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2352 /* move promisc configuration from active -> pending */
2353 promisc_enable(rxf->rxmode_pending,
2354 rxf->rxmode_pending_bitmask);
2355 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2356
2357 /* Revert VLAN filter */
2358 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2359 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2360 BNA_STATUS_T_DISABLED);
2361 return 1;
2362 }
2363
2364 return 0;
2365}
2366
2367int
2368rxf_clear_packet_filter_default(struct bna_rxf *rxf)
2369{
2370 struct bna *bna = rxf->rx->bna;
2371
2372 /* 8. Execute pending default mode disable command */
2373 if (is_default_disable(rxf->rxmode_pending,
2374 rxf->rxmode_pending_bitmask)) {
2375 /* move default configuration from pending -> active */
2376 default_inactive(rxf->rxmode_pending,
2377 rxf->rxmode_pending_bitmask);
2378 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2379 bna->rxf_default_id = BFI_MAX_RXF;
2380
2381 /* Revert VLAN filter */
2382 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2383 /* Stop RxF vlan filter table redirection */
2384 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2385 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2386 BNA_STATUS_T_DISABLED);
2387 return 1;
2388 }
2389
2390 /* 9. Clear active default mode; move it to pending enable */
2391 if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2392 /* move default configuration from active -> pending */
2393 default_enable(rxf->rxmode_pending,
2394 rxf->rxmode_pending_bitmask);
2395 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2396
2397 /* Revert VLAN filter */
2398 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2399 /* Stop RxF vlan filter table redirection */
2400 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2401 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2402 BNA_STATUS_T_DISABLED);
2403 return 1;
2404 }
2405
2406 return 0;
2407}
2408
2409int
2410rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
2411{
2412 /* 10. Execute pending allmulti mode disable command */
2413 if (is_allmulti_disable(rxf->rxmode_pending,
2414 rxf->rxmode_pending_bitmask)) {
2415 /* move allmulti configuration from pending -> active */
2416 allmulti_inactive(rxf->rxmode_pending,
2417 rxf->rxmode_pending_bitmask);
2418 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2419 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2420 BNA_STATUS_T_DISABLED);
2421 return 1;
2422 }
2423
2424 /* 11. Clear active allmulti mode; move it to pending enable */
2425 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2426 /* move allmulti configuration from active -> pending */
2427 allmulti_enable(rxf->rxmode_pending,
2428 rxf->rxmode_pending_bitmask);
2429 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2430 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2431 BNA_STATUS_T_DISABLED);
2432 return 1;
2433 }
2434
2435 return 0;
2436}
2437
2438void
2439rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
2440{
2441 struct list_head *qe;
2442 struct bna_mac *mac;
2443
2444 /* 1. Move active ucast entries to pending_add_q */
2445 while (!list_empty(&rxf->ucast_active_q)) {
2446 bfa_q_deq(&rxf->ucast_active_q, &qe);
2447 bfa_q_qe_init(qe);
2448 list_add_tail(qe, &rxf->ucast_pending_add_q);
2449 }
2450
2451 /* 2. Throw away delete pending ucast entries */
2452 while (!list_empty(&rxf->ucast_pending_del_q)) {
2453 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2454 bfa_q_qe_init(qe);
2455 mac = (struct bna_mac *)qe;
2456 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2457 }
2458}
2459
2460void
2461rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
2462{
2463 struct bna *bna = rxf->rx->bna;
2464
2465 /* 6. Clear pending promisc mode disable */
2466 if (is_promisc_disable(rxf->rxmode_pending,
2467 rxf->rxmode_pending_bitmask)) {
2468 promisc_inactive(rxf->rxmode_pending,
2469 rxf->rxmode_pending_bitmask);
2470 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2471 bna->rxf_promisc_id = BFI_MAX_RXF;
2472 }
2473
2474 /* 7. Move promisc mode config from active -> pending */
2475 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2476 promisc_enable(rxf->rxmode_pending,
2477 rxf->rxmode_pending_bitmask);
2478 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2479 }
2480
2481}
2482
2483void
2484rxf_reset_packet_filter_default(struct bna_rxf *rxf)
2485{
2486 struct bna *bna = rxf->rx->bna;
2487
2488 /* 8. Clear pending default mode disable */
2489 if (is_default_disable(rxf->rxmode_pending,
2490 rxf->rxmode_pending_bitmask)) {
2491 default_inactive(rxf->rxmode_pending,
2492 rxf->rxmode_pending_bitmask);
2493 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2494 bna->rxf_default_id = BFI_MAX_RXF;
2495 }
2496
2497 /* 9. Move default mode config from active -> pending */
2498 if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2499 default_enable(rxf->rxmode_pending,
2500 rxf->rxmode_pending_bitmask);
2501 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2502 }
2503}
2504
2505void
2506rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
2507{
2508 /* 10. Clear pending allmulti mode disable */
2509 if (is_allmulti_disable(rxf->rxmode_pending,
2510 rxf->rxmode_pending_bitmask)) {
2511 allmulti_inactive(rxf->rxmode_pending,
2512 rxf->rxmode_pending_bitmask);
2513 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2514 }
2515
2516 /* 11. Move allmulti mode config from active -> pending */
2517 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2518 allmulti_enable(rxf->rxmode_pending,
2519 rxf->rxmode_pending_bitmask);
2520 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2521 }
2522}
2523
2524/**
2525 * Should only be called by bna_rxf_mode_set.
2526 * Helps deciding if h/w configuration is needed or not.
2527 * Returns:
2528 * 0 = no h/w change
2529 * 1 = need h/w change
2530 */
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002531static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002532rxf_promisc_enable(struct bna_rxf *rxf)
2533{
2534 struct bna *bna = rxf->rx->bna;
2535 int ret = 0;
2536
2537 /* There can not be any pending disable command */
2538
2539 /* Do nothing if pending enable or already enabled */
2540 if (is_promisc_enable(rxf->rxmode_pending,
2541 rxf->rxmode_pending_bitmask) ||
2542 (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
2543 /* Schedule enable */
2544 } else {
2545 /* Promisc mode should not be active in the system */
2546 promisc_enable(rxf->rxmode_pending,
2547 rxf->rxmode_pending_bitmask);
2548 bna->rxf_promisc_id = rxf->rxf_id;
2549 ret = 1;
2550 }
2551
2552 return ret;
2553}
2554
2555/**
2556 * Should only be called by bna_rxf_mode_set.
2557 * Helps deciding if h/w configuration is needed or not.
2558 * Returns:
2559 * 0 = no h/w change
2560 * 1 = need h/w change
2561 */
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002562static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002563rxf_promisc_disable(struct bna_rxf *rxf)
2564{
2565 struct bna *bna = rxf->rx->bna;
2566 int ret = 0;
2567
2568 /* There can not be any pending disable */
2569
2570 /* Turn off pending enable command , if any */
2571 if (is_promisc_enable(rxf->rxmode_pending,
2572 rxf->rxmode_pending_bitmask)) {
2573 /* Promisc mode should not be active */
2574 /* system promisc state should be pending */
2575 promisc_inactive(rxf->rxmode_pending,
2576 rxf->rxmode_pending_bitmask);
2577 /* Remove the promisc state from the system */
2578 bna->rxf_promisc_id = BFI_MAX_RXF;
2579
2580 /* Schedule disable */
2581 } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2582 /* Promisc mode should be active in the system */
2583 promisc_disable(rxf->rxmode_pending,
2584 rxf->rxmode_pending_bitmask);
2585 ret = 1;
2586
2587 /* Do nothing if already disabled */
2588 } else {
2589 }
2590
2591 return ret;
2592}
2593
2594/**
2595 * Should only be called by bna_rxf_mode_set.
2596 * Helps deciding if h/w configuration is needed or not.
2597 * Returns:
2598 * 0 = no h/w change
2599 * 1 = need h/w change
2600 */
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002601static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002602rxf_default_enable(struct bna_rxf *rxf)
2603{
2604 struct bna *bna = rxf->rx->bna;
2605 int ret = 0;
2606
2607 /* There can not be any pending disable command */
2608
2609 /* Do nothing if pending enable or already enabled */
2610 if (is_default_enable(rxf->rxmode_pending,
2611 rxf->rxmode_pending_bitmask) ||
2612 (rxf->rxmode_active & BNA_RXMODE_DEFAULT)) {
2613 /* Schedule enable */
2614 } else {
2615 /* Default mode should not be active in the system */
2616 default_enable(rxf->rxmode_pending,
2617 rxf->rxmode_pending_bitmask);
2618 bna->rxf_default_id = rxf->rxf_id;
2619 ret = 1;
2620 }
2621
2622 return ret;
2623}
2624
2625/**
2626 * Should only be called by bna_rxf_mode_set.
2627 * Helps deciding if h/w configuration is needed or not.
2628 * Returns:
2629 * 0 = no h/w change
2630 * 1 = need h/w change
2631 */
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002632static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002633rxf_default_disable(struct bna_rxf *rxf)
2634{
2635 struct bna *bna = rxf->rx->bna;
2636 int ret = 0;
2637
2638 /* There can not be any pending disable */
2639
2640 /* Turn off pending enable command , if any */
2641 if (is_default_enable(rxf->rxmode_pending,
2642 rxf->rxmode_pending_bitmask)) {
2643 /* Promisc mode should not be active */
2644 /* system default state should be pending */
2645 default_inactive(rxf->rxmode_pending,
2646 rxf->rxmode_pending_bitmask);
2647 /* Remove the default state from the system */
2648 bna->rxf_default_id = BFI_MAX_RXF;
2649
2650 /* Schedule disable */
2651 } else if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2652 /* Default mode should be active in the system */
2653 default_disable(rxf->rxmode_pending,
2654 rxf->rxmode_pending_bitmask);
2655 ret = 1;
2656
2657 /* Do nothing if already disabled */
2658 } else {
2659 }
2660
2661 return ret;
2662}
2663
2664/**
2665 * Should only be called by bna_rxf_mode_set.
2666 * Helps deciding if h/w configuration is needed or not.
2667 * Returns:
2668 * 0 = no h/w change
2669 * 1 = need h/w change
2670 */
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002671static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002672rxf_allmulti_enable(struct bna_rxf *rxf)
2673{
2674 int ret = 0;
2675
2676 /* There can not be any pending disable command */
2677
2678 /* Do nothing if pending enable or already enabled */
2679 if (is_allmulti_enable(rxf->rxmode_pending,
2680 rxf->rxmode_pending_bitmask) ||
2681 (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
2682 /* Schedule enable */
2683 } else {
2684 allmulti_enable(rxf->rxmode_pending,
2685 rxf->rxmode_pending_bitmask);
2686 ret = 1;
2687 }
2688
2689 return ret;
2690}
2691
2692/**
2693 * Should only be called by bna_rxf_mode_set.
2694 * Helps deciding if h/w configuration is needed or not.
2695 * Returns:
2696 * 0 = no h/w change
2697 * 1 = need h/w change
2698 */
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002699static int
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002700rxf_allmulti_disable(struct bna_rxf *rxf)
2701{
2702 int ret = 0;
2703
2704 /* There can not be any pending disable */
2705
2706 /* Turn off pending enable command , if any */
2707 if (is_allmulti_enable(rxf->rxmode_pending,
2708 rxf->rxmode_pending_bitmask)) {
2709 /* Allmulti mode should not be active */
2710 allmulti_inactive(rxf->rxmode_pending,
2711 rxf->rxmode_pending_bitmask);
2712
2713 /* Schedule disable */
2714 } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2715 allmulti_disable(rxf->rxmode_pending,
2716 rxf->rxmode_pending_bitmask);
2717 ret = 1;
2718 }
2719
2720 return ret;
2721}
2722
2723/* RxF <- bnad */
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002724enum bna_cb_status
2725bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
2726 enum bna_rxmode bitmask,
2727 void (*cbfn)(struct bnad *, struct bna_rx *,
2728 enum bna_cb_status))
2729{
2730 struct bna_rxf *rxf = &rx->rxf;
2731 int need_hw_config = 0;
2732
2733 /* Error checks */
2734
2735 if (is_promisc_enable(new_mode, bitmask)) {
2736 /* If promisc mode is already enabled elsewhere in the system */
2737 if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
2738 (rx->bna->rxf_promisc_id != rxf->rxf_id))
2739 goto err_return;
2740
2741 /* If default mode is already enabled in the system */
2742 if (rx->bna->rxf_default_id != BFI_MAX_RXF)
2743 goto err_return;
2744
2745 /* Trying to enable promiscuous and default mode together */
2746 if (is_default_enable(new_mode, bitmask))
2747 goto err_return;
2748 }
2749
2750 if (is_default_enable(new_mode, bitmask)) {
2751 /* If default mode is already enabled elsewhere in the system */
2752 if ((rx->bna->rxf_default_id != BFI_MAX_RXF) &&
2753 (rx->bna->rxf_default_id != rxf->rxf_id)) {
2754 goto err_return;
2755 }
2756
2757 /* If promiscuous mode is already enabled in the system */
2758 if (rx->bna->rxf_promisc_id != BFI_MAX_RXF)
2759 goto err_return;
2760 }
2761
2762 /* Process the commands */
2763
2764 if (is_promisc_enable(new_mode, bitmask)) {
2765 if (rxf_promisc_enable(rxf))
2766 need_hw_config = 1;
2767 } else if (is_promisc_disable(new_mode, bitmask)) {
2768 if (rxf_promisc_disable(rxf))
2769 need_hw_config = 1;
2770 }
2771
2772 if (is_default_enable(new_mode, bitmask)) {
2773 if (rxf_default_enable(rxf))
2774 need_hw_config = 1;
2775 } else if (is_default_disable(new_mode, bitmask)) {
2776 if (rxf_default_disable(rxf))
2777 need_hw_config = 1;
2778 }
2779
2780 if (is_allmulti_enable(new_mode, bitmask)) {
2781 if (rxf_allmulti_enable(rxf))
2782 need_hw_config = 1;
2783 } else if (is_allmulti_disable(new_mode, bitmask)) {
2784 if (rxf_allmulti_disable(rxf))
2785 need_hw_config = 1;
2786 }
2787
2788 /* Trigger h/w if needed */
2789
2790 if (need_hw_config) {
2791 rxf->cam_fltr_cbfn = cbfn;
2792 rxf->cam_fltr_cbarg = rx->bna->bnad;
2793 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2794 } else if (cbfn)
2795 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2796
2797 return BNA_CB_SUCCESS;
2798
2799err_return:
2800 return BNA_CB_FAIL;
2801}
2802
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002803void
2804/* RxF <- bnad */
2805bna_rx_vlanfilter_enable(struct bna_rx *rx)
2806{
2807 struct bna_rxf *rxf = &rx->rxf;
2808
2809 if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
2810 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
2811 rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
2812 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2813 }
2814}
2815
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002816/* Rx */
2817
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002818/* Rx <- bnad */
2819void
2820bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
2821{
2822 struct bna_rxp *rxp;
2823 struct list_head *qe;
2824
2825 list_for_each(qe, &rx->rxp_q) {
2826 rxp = (struct bna_rxp *)qe;
2827 rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
2828 bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
2829 }
2830}
2831
2832/* Rx <- bnad */
2833void
Rasesh Modyb7ee31c2010-10-05 15:46:05 +00002834bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002835{
2836 int i, j;
2837
2838 for (i = 0; i < BNA_LOAD_T_MAX; i++)
2839 for (j = 0; j < BNA_BIAS_T_MAX; j++)
2840 bna->rx_mod.dim_vector[i][j] = vector[i][j];
2841}
2842
2843/* Rx <- bnad */
2844void
2845bna_rx_dim_update(struct bna_ccb *ccb)
2846{
2847 struct bna *bna = ccb->cq->rx->bna;
2848 u32 load, bias;
2849 u32 pkt_rt, small_rt, large_rt;
2850 u8 coalescing_timeo;
2851
2852 if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
2853 (ccb->pkt_rate.large_pkt_cnt == 0))
2854 return;
2855
2856 /* Arrive at preconfigured coalescing timeo value based on pkt rate */
2857
2858 small_rt = ccb->pkt_rate.small_pkt_cnt;
2859 large_rt = ccb->pkt_rate.large_pkt_cnt;
2860
2861 pkt_rt = small_rt + large_rt;
2862
2863 if (pkt_rt < BNA_PKT_RATE_10K)
2864 load = BNA_LOAD_T_LOW_4;
2865 else if (pkt_rt < BNA_PKT_RATE_20K)
2866 load = BNA_LOAD_T_LOW_3;
2867 else if (pkt_rt < BNA_PKT_RATE_30K)
2868 load = BNA_LOAD_T_LOW_2;
2869 else if (pkt_rt < BNA_PKT_RATE_40K)
2870 load = BNA_LOAD_T_LOW_1;
2871 else if (pkt_rt < BNA_PKT_RATE_50K)
2872 load = BNA_LOAD_T_HIGH_1;
2873 else if (pkt_rt < BNA_PKT_RATE_60K)
2874 load = BNA_LOAD_T_HIGH_2;
2875 else if (pkt_rt < BNA_PKT_RATE_80K)
2876 load = BNA_LOAD_T_HIGH_3;
2877 else
2878 load = BNA_LOAD_T_HIGH_4;
2879
2880 if (small_rt > (large_rt << 1))
2881 bias = 0;
2882 else
2883 bias = 1;
2884
2885 ccb->pkt_rate.small_pkt_cnt = 0;
2886 ccb->pkt_rate.large_pkt_cnt = 0;
2887
2888 coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
2889 ccb->rx_coalescing_timeo = coalescing_timeo;
2890
2891 /* Set it to IB */
2892 bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
2893}
2894
2895/* Tx */
2896/* TX <- bnad */
Rasesh Mody8b230ed2010-08-23 20:24:12 -07002897void
2898bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
2899{
2900 struct bna_txq *txq;
2901 struct list_head *qe;
2902
2903 list_for_each(qe, &tx->txq_q) {
2904 txq = (struct bna_txq *)qe;
2905 bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
2906 }
2907}
2908
2909/*
2910 * Private data
2911 */
2912
2913struct bna_ritseg_pool_cfg {
2914 u32 pool_size;
2915 u32 pool_entry_size;
2916};
2917init_ritseg_pool(ritseg_pool_cfg);
2918
2919/*
2920 * Private functions
2921 */
2922static void
2923bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
2924 struct bna_res_info *res_info)
2925{
2926 int i;
2927
2928 ucam_mod->ucmac = (struct bna_mac *)
2929 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2930
2931 INIT_LIST_HEAD(&ucam_mod->free_q);
2932 for (i = 0; i < BFI_MAX_UCMAC; i++) {
2933 bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
2934 list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
2935 }
2936
2937 ucam_mod->bna = bna;
2938}
2939
2940static void
2941bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
2942{
2943 struct list_head *qe;
2944 int i = 0;
2945
2946 list_for_each(qe, &ucam_mod->free_q)
2947 i++;
2948
2949 ucam_mod->bna = NULL;
2950}
2951
2952static void
2953bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
2954 struct bna_res_info *res_info)
2955{
2956 int i;
2957
2958 mcam_mod->mcmac = (struct bna_mac *)
2959 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2960
2961 INIT_LIST_HEAD(&mcam_mod->free_q);
2962 for (i = 0; i < BFI_MAX_MCMAC; i++) {
2963 bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
2964 list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
2965 }
2966
2967 mcam_mod->bna = bna;
2968}
2969
2970static void
2971bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
2972{
2973 struct list_head *qe;
2974 int i = 0;
2975
2976 list_for_each(qe, &mcam_mod->free_q)
2977 i++;
2978
2979 mcam_mod->bna = NULL;
2980}
2981
2982static void
2983bna_rit_mod_init(struct bna_rit_mod *rit_mod,
2984 struct bna_res_info *res_info)
2985{
2986 int i;
2987 int j;
2988 int count;
2989 int offset;
2990
2991 rit_mod->rit = (struct bna_rit_entry *)
2992 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
2993 rit_mod->rit_segment = (struct bna_rit_segment *)
2994 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
2995
2996 count = 0;
2997 offset = 0;
2998 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
2999 INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
3000 for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
3001 bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
3002 rit_mod->rit_segment[count].max_rit_size =
3003 ritseg_pool_cfg[i].pool_entry_size;
3004 rit_mod->rit_segment[count].rit_offset = offset;
3005 rit_mod->rit_segment[count].rit =
3006 &rit_mod->rit[offset];
3007 list_add_tail(&rit_mod->rit_segment[count].qe,
3008 &rit_mod->rit_seg_pool[i]);
3009 count++;
3010 offset += ritseg_pool_cfg[i].pool_entry_size;
3011 }
3012 }
3013}
3014
3015static void
3016bna_rit_mod_uninit(struct bna_rit_mod *rit_mod)
3017{
3018 struct bna_rit_segment *rit_segment;
3019 struct list_head *qe;
3020 int i;
3021 int j;
3022
3023 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3024 j = 0;
3025 list_for_each(qe, &rit_mod->rit_seg_pool[i]) {
3026 rit_segment = (struct bna_rit_segment *)qe;
3027 j++;
3028 }
3029 }
3030}
3031
3032/*
3033 * Public functions
3034 */
3035
3036/* Called during probe(), before calling bna_init() */
3037void
3038bna_res_req(struct bna_res_info *res_info)
3039{
3040 bna_adv_res_req(res_info);
3041
3042 /* DMA memory for retrieving IOC attributes */
3043 res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
3044 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
3045 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
3046 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
Rasesh Mody8a891422010-08-25 23:00:27 -07003047 ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE);
Rasesh Mody8b230ed2010-08-23 20:24:12 -07003048
3049 /* DMA memory for index segment of an IB */
3050 res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
3051 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
3052 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
3053 BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
3054 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
3055
3056 /* Virtual memory for IB objects - stored by IB module */
3057 res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
3058 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
3059 BNA_MEM_T_KVA;
3060 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
3061 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
3062 BFI_MAX_IB * sizeof(struct bna_ib);
3063
3064 /* Virtual memory for intr objects - stored by IB module */
3065 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
3066 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
3067 BNA_MEM_T_KVA;
3068 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
3069 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
3070 BFI_MAX_IB * sizeof(struct bna_intr);
3071
3072 /* Virtual memory for idx_seg objects - stored by IB module */
3073 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
3074 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
3075 BNA_MEM_T_KVA;
3076 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
3077 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
3078 BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
3079
3080 /* Virtual memory for Tx objects - stored by Tx module */
3081 res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
3082 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
3083 BNA_MEM_T_KVA;
3084 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
3085 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
3086 BFI_MAX_TXQ * sizeof(struct bna_tx);
3087
3088 /* Virtual memory for TxQ - stored by Tx module */
3089 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
3090 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
3091 BNA_MEM_T_KVA;
3092 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
3093 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
3094 BFI_MAX_TXQ * sizeof(struct bna_txq);
3095
3096 /* Virtual memory for Rx objects - stored by Rx module */
3097 res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
3098 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
3099 BNA_MEM_T_KVA;
3100 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
3101 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
3102 BFI_MAX_RXQ * sizeof(struct bna_rx);
3103
3104 /* Virtual memory for RxPath - stored by Rx module */
3105 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
3106 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
3107 BNA_MEM_T_KVA;
3108 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
3109 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
3110 BFI_MAX_RXQ * sizeof(struct bna_rxp);
3111
3112 /* Virtual memory for RxQ - stored by Rx module */
3113 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
3114 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
3115 BNA_MEM_T_KVA;
3116 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
3117 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
3118 BFI_MAX_RXQ * sizeof(struct bna_rxq);
3119
3120 /* Virtual memory for Unicast MAC address - stored by ucam module */
3121 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3122 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
3123 BNA_MEM_T_KVA;
3124 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
3125 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
3126 BFI_MAX_UCMAC * sizeof(struct bna_mac);
3127
3128 /* Virtual memory for Multicast MAC address - stored by mcam module */
3129 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3130 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
3131 BNA_MEM_T_KVA;
3132 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
3133 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
3134 BFI_MAX_MCMAC * sizeof(struct bna_mac);
3135
3136 /* Virtual memory for RIT entries */
3137 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
3138 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
3139 BNA_MEM_T_KVA;
3140 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
3141 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
3142 BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
3143
3144 /* Virtual memory for RIT segment table */
3145 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
3146 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
3147 BNA_MEM_T_KVA;
3148 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
3149 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
3150 BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
3151
3152 /* Interrupt resource for mailbox interrupt */
3153 res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
3154 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
3155 BNA_INTR_T_MSIX;
3156 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
3157}
3158
3159/* Called during probe() */
3160void
3161bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
3162 struct bna_res_info *res_info)
3163{
3164 bna->bnad = bnad;
3165 bna->pcidev = *pcidev;
3166
3167 bna->stats.hw_stats = (struct bfi_ll_stats *)
3168 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
3169 bna->hw_stats_dma.msb =
3170 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
3171 bna->hw_stats_dma.lsb =
3172 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
3173 bna->stats.sw_stats = (struct bna_sw_stats *)
3174 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
3175
3176 bna->regs.page_addr = bna->pcidev.pci_bar_kva +
3177 reg_offset[bna->pcidev.pci_func].page_addr;
3178 bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
3179 reg_offset[bna->pcidev.pci_func].fn_int_status;
3180 bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
3181 reg_offset[bna->pcidev.pci_func].fn_int_mask;
3182
3183 if (bna->pcidev.pci_func < 3)
3184 bna->port_num = 0;
3185 else
3186 bna->port_num = 1;
3187
3188 /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
3189 bna_device_init(&bna->device, bna, res_info);
3190
3191 bna_port_init(&bna->port, bna);
3192
3193 bna_tx_mod_init(&bna->tx_mod, bna, res_info);
3194
3195 bna_rx_mod_init(&bna->rx_mod, bna, res_info);
3196
3197 bna_ib_mod_init(&bna->ib_mod, bna, res_info);
3198
3199 bna_rit_mod_init(&bna->rit_mod, res_info);
3200
3201 bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
3202
3203 bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
3204
3205 bna->rxf_default_id = BFI_MAX_RXF;
3206 bna->rxf_promisc_id = BFI_MAX_RXF;
3207
3208 /* Mbox q element for posting stat request to f/w */
3209 bfa_q_qe_init(&bna->mbox_qe.qe);
3210}
3211
3212void
3213bna_uninit(struct bna *bna)
3214{
3215 bna_mcam_mod_uninit(&bna->mcam_mod);
3216
3217 bna_ucam_mod_uninit(&bna->ucam_mod);
3218
3219 bna_rit_mod_uninit(&bna->rit_mod);
3220
3221 bna_ib_mod_uninit(&bna->ib_mod);
3222
3223 bna_rx_mod_uninit(&bna->rx_mod);
3224
3225 bna_tx_mod_uninit(&bna->tx_mod);
3226
3227 bna_port_uninit(&bna->port);
3228
3229 bna_device_uninit(&bna->device);
3230
3231 bna->bnad = NULL;
3232}
3233
3234struct bna_mac *
3235bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
3236{
3237 struct list_head *qe;
3238
3239 if (list_empty(&ucam_mod->free_q))
3240 return NULL;
3241
3242 bfa_q_deq(&ucam_mod->free_q, &qe);
3243
3244 return (struct bna_mac *)qe;
3245}
3246
3247void
3248bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
3249{
3250 list_add_tail(&mac->qe, &ucam_mod->free_q);
3251}
3252
3253struct bna_mac *
3254bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
3255{
3256 struct list_head *qe;
3257
3258 if (list_empty(&mcam_mod->free_q))
3259 return NULL;
3260
3261 bfa_q_deq(&mcam_mod->free_q, &qe);
3262
3263 return (struct bna_mac *)qe;
3264}
3265
3266void
3267bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
3268{
3269 list_add_tail(&mac->qe, &mcam_mod->free_q);
3270}
3271
3272/**
3273 * Note: This should be called in the same locking context as the call to
3274 * bna_rit_mod_seg_get()
3275 */
3276int
3277bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
3278{
3279 int i;
3280
3281 /* Select the pool for seg_size */
3282 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3283 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3284 break;
3285 }
3286
3287 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3288 return 0;
3289
3290 if (list_empty(&rit_mod->rit_seg_pool[i]))
3291 return 0;
3292
3293 return 1;
3294}
3295
3296struct bna_rit_segment *
3297bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
3298{
3299 struct bna_rit_segment *seg;
3300 struct list_head *qe;
3301 int i;
3302
3303 /* Select the pool for seg_size */
3304 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3305 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3306 break;
3307 }
3308
3309 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3310 return NULL;
3311
3312 if (list_empty(&rit_mod->rit_seg_pool[i]))
3313 return NULL;
3314
3315 bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
3316 seg = (struct bna_rit_segment *)qe;
3317 bfa_q_qe_init(&seg->qe);
3318 seg->rit_size = seg_size;
3319
3320 return seg;
3321}
3322
3323void
3324bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
3325 struct bna_rit_segment *seg)
3326{
3327 int i;
3328
3329 /* Select the pool for seg->max_rit_size */
3330 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3331 if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
3332 break;
3333 }
3334
3335 seg->rit_size = 0;
3336 list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);
3337}