Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / 0835ae0f27c0bfde67613d189ef6c537e004a6de / . / arch / sparc64 / kernel / etrap.S
blob: 0d8eba21111b75582ba1f52c946a1121ab7a8774 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
3 *
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8#include <linux/config.h>
9
10#include <asm/asi.h>
11#include <asm/pstate.h>
12#include <asm/ptrace.h>
13#include <asm/page.h>
14#include <asm/spitfire.h>
15#include <asm/head.h>
16#include <asm/processor.h>
17#include <asm/mmu.h>
18
19#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
20#define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
21#define ETRAP_PSTATE2 \
22 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
23
24/*
25 * On entry, %g7 is return address - 0x4.
26 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
27 */
28
29 .text
30 .align 64
31 .globl etrap, etrap_irq, etraptl1
32etrap: rdpr %pil, %g2
33etrap_irq:
34 rdpr %tstate, %g1
35 sllx %g2, 20, %g3
36 andcc %g1, TSTATE_PRIV, %g0
37 or %g1, %g3, %g1
38 bne,pn %xcc, 1f
39 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
40 wrpr %g0, 7, %cleanwin
41
42 sethi %hi(TASK_REGOFF), %g2
43 sethi %hi(TSTATE_PEF), %g3
44 or %g2, %lo(TASK_REGOFF), %g2
45 and %g1, %g3, %g3
46 brnz,pn %g3, 1f
47 add %g6, %g2, %g2
48 wr %g0, 0, %fprs
491: rdpr %tpc, %g3
50
51 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
52 rdpr %tnpc, %g1
53 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
54 rd %y, %g3
55 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
56 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
57 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
58 mov %g6, %l6
59
60 bne,pn %xcc, 3f
61 mov PRIMARY_CONTEXT, %l4
62 rdpr %canrestore, %g3
63 rdpr %wstate, %g2
64 wrpr %g0, 0, %canrestore
65 sll %g2, 3, %g2
66 mov 1, %l5
67 stb %l5, [%l6 + TI_FPDEPTH]
68
69 wrpr %g3, 0, %otherwin
70 wrpr %g2, 0, %wstate
David S. Miller0835ae02005-10-04 15:23:20 -0700[diff] [blame^]71 sethi %hi(sparc64_kern_pri_context), %g2
72 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]73 stxa %g3, [%l4] ASI_DMMU
74 flush %l6
75 wr %g0, ASI_AIUS, %asi
762: wrpr %g0, 0x0, %tl
77 mov %g4, %l4
78 mov %g5, %l5
79
80 mov %g7, %l2
81 wrpr %g0, ETRAP_PSTATE1, %pstate
82 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
83 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
84 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
85 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
86 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
87 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
88
89 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
90 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
91 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
92 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
93 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
94 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
95 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
96
97 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
98 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
99 wrpr %g0, ETRAP_PSTATE2, %pstate
100 mov %l6, %g6
101#ifdef CONFIG_SMP
102 mov TSB_REG, %g3
103 ldxa [%g3] ASI_IMMU, %g5
104#endif
105 jmpl %l2 + 0x4, %g0
106 ldx [%g6 + TI_TASK], %g4
107
1083: ldub [%l6 + TI_FPDEPTH], %l5
109 add %l6, TI_FPSAVED + 1, %l4
110 srl %l5, 1, %l3
111 add %l5, 2, %l5
112 stb %l5, [%l6 + TI_FPDEPTH]
113 ba,pt %xcc, 2b
114 stb %g0, [%l4 + %l3]
115 nop
116
117etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
118 * We place this right after pt_regs on the trap stack.
119 * The layout is:
120 * 0x00 TL1's TSTATE
121 * 0x08 TL1's TPC
122 * 0x10 TL1's TNPC
123 * 0x18 TL1's TT
124 * ...
125 * 0x58 TL4's TT
126 * 0x60 TL
127 */
128 sub %sp, ((4 * 8) * 4) + 8, %g2
129 rdpr %tl, %g1
130
131 wrpr %g0, 1, %tl
132 rdpr %tstate, %g3
133 stx %g3, [%g2 + STACK_BIAS + 0x00]
134 rdpr %tpc, %g3
135 stx %g3, [%g2 + STACK_BIAS + 0x08]
136 rdpr %tnpc, %g3
137 stx %g3, [%g2 + STACK_BIAS + 0x10]
138 rdpr %tt, %g3
139 stx %g3, [%g2 + STACK_BIAS + 0x18]
140
141 wrpr %g0, 2, %tl
142 rdpr %tstate, %g3
143 stx %g3, [%g2 + STACK_BIAS + 0x20]
144 rdpr %tpc, %g3
145 stx %g3, [%g2 + STACK_BIAS + 0x28]
146 rdpr %tnpc, %g3
147 stx %g3, [%g2 + STACK_BIAS + 0x30]
148 rdpr %tt, %g3
149 stx %g3, [%g2 + STACK_BIAS + 0x38]
150
151 wrpr %g0, 3, %tl
152 rdpr %tstate, %g3
153 stx %g3, [%g2 + STACK_BIAS + 0x40]
154 rdpr %tpc, %g3
155 stx %g3, [%g2 + STACK_BIAS + 0x48]
156 rdpr %tnpc, %g3
157 stx %g3, [%g2 + STACK_BIAS + 0x50]
158 rdpr %tt, %g3
159 stx %g3, [%g2 + STACK_BIAS + 0x58]
160
161 wrpr %g0, 4, %tl
162 rdpr %tstate, %g3
163 stx %g3, [%g2 + STACK_BIAS + 0x60]
164 rdpr %tpc, %g3
165 stx %g3, [%g2 + STACK_BIAS + 0x68]
166 rdpr %tnpc, %g3
167 stx %g3, [%g2 + STACK_BIAS + 0x70]
168 rdpr %tt, %g3
169 stx %g3, [%g2 + STACK_BIAS + 0x78]
170
171 wrpr %g1, %tl
172 stx %g1, [%g2 + STACK_BIAS + 0x80]
173
174 rdpr %tstate, %g1
175 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
176 ba,pt %xcc, 1b
177 andcc %g1, TSTATE_PRIV, %g0
178
179 .align 64
180 .globl scetrap
181scetrap: rdpr %pil, %g2
182 rdpr %tstate, %g1
183 sllx %g2, 20, %g3
184 andcc %g1, TSTATE_PRIV, %g0
185 or %g1, %g3, %g1
186 bne,pn %xcc, 1f
187 sub %sp, (STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS), %g2
188 wrpr %g0, 7, %cleanwin
189
190 sllx %g1, 51, %g3
191 sethi %hi(TASK_REGOFF), %g2
192 or %g2, %lo(TASK_REGOFF), %g2
193 brlz,pn %g3, 1f
194 add %g6, %g2, %g2
195 wr %g0, 0, %fprs
1961: rdpr %tpc, %g3
197 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
198
199 rdpr %tnpc, %g1
200 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
201 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
202 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
203 mov %g6, %l6
204 bne,pn %xcc, 2f
205 mov ASI_P, %l7
206 rdpr %canrestore, %g3
207
208 rdpr %wstate, %g2
209 wrpr %g0, 0, %canrestore
210 sll %g2, 3, %g2
211 mov PRIMARY_CONTEXT, %l4
212 wrpr %g3, 0, %otherwin
213 wrpr %g2, 0, %wstate
David S. Miller0835ae02005-10-04 15:23:20 -0700[diff] [blame^]214 sethi %hi(sparc64_kern_pri_context), %g2
215 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]216 stxa %g3, [%l4] ASI_DMMU
217 flush %l6
218
219 mov ASI_AIUS, %l7
2202: mov %g4, %l4
221 mov %g5, %l5
222 add %g7, 0x4, %l2
223 wrpr %g0, ETRAP_PSTATE1, %pstate
224 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
225 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
226 sllx %l7, 24, %l7
227
228 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
229 rdpr %cwp, %l0
230 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
231 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
232 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
233 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
234 or %l7, %l0, %l7
235 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
236
237 or %l7, %l0, %l7
238 wrpr %l2, %tnpc
239 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
240 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
241 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
242 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
243 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
244 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
245
246 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
247 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
248 mov %l6, %g6
249 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
250#ifdef CONFIG_SMP
251 mov TSB_REG, %g3
252 ldxa [%g3] ASI_IMMU, %g5
253#endif
254 ldx [%g6 + TI_TASK], %g4
255 done
256
257#undef TASK_REGOFF
258#undef ETRAP_PSTATE1