blob: 731332288931b37f16f9912424928459aa849db5 [file] [log] [blame]
Kumar Galad0fc2ea2008-07-07 11:28:33 -05001Freescale Synchronous Serial Interface
2
3The SSI is a serial device that communicates with audio codecs. It can
4be programmed in AC97, I2S, left-justified, or right-justified modes.
5
6Required properties:
7- compatible : compatible list, containing "fsl,ssi"
8- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
9- reg : offset and length of the register set for the device
10- interrupts : <a b> where a is the interrupt number and b is a
11 field that represents an encoding of the sense and
12 level information for the interrupt. This should be
13 encoded based on the information in section 2)
14 depending on the type of interrupt controller you
15 have.
16- interrupt-parent : the phandle for the interrupt controller that
17 services interrupts for this device.
18- fsl,mode : the operating mode for the SSI interface
19 "i2s-slave" - I2S mode, SSI is clock slave
20 "i2s-master" - I2S mode, SSI is clock master
21 "lj-slave" - left-justified mode, SSI is clock slave
22 "lj-master" - l.j. mode, SSI is clock master
23 "rj-slave" - right-justified mode, SSI is clock slave
24 "rj-master" - r.j., SSI is clock master
25 "ac97-slave" - AC97 mode, SSI is clock slave
26 "ac97-master" - AC97 mode, SSI is clock master
Timur Tabib56c2762008-10-10 11:52:31 -050027- fsl,playback-dma: phandle to a node for the DMA channel to use for
28 playback of audio. This is typically dictated by SOC
29 design. See the notes below.
30- fsl,capture-dma: phandle to a node for the DMA channel to use for
31 capture (recording) of audio. This is typically dictated
32 by SOC design. See the notes below.
Timur Tabi0bcd7832009-03-04 14:55:30 -060033- fsl,fifo-depth: the number of elements in the transmit and receive FIFOs.
34 This number is the maximum allowed value for SFCSR[TFWM0].
Kumar Galad0fc2ea2008-07-07 11:28:33 -050035
36Optional properties:
37- codec-handle : phandle to a 'codec' node that defines an audio
38 codec connected to this SSI. This node is typically
39 a child of an I2C or other control node.
40
41Child 'codec' node required properties:
42- compatible : compatible list, contains the name of the codec
43
44Child 'codec' node optional properties:
45- clock-frequency : The frequency of the input clock, which typically
46 comes from an on-board dedicated oscillator.
Timur Tabic2fe5942008-08-06 11:48:25 -050047
48Notes on fsl,playback-dma and fsl,capture-dma:
49
50On SOCs that have an SSI, specific DMA channels are hard-wired for playback
51and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
52playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
53playback and DMA channel 3 for capture. The developer can choose which
54DMA controller to use, but the channels themselves are hard-wired. The
55purpose of these two properties is to represent this hardware design.
Timur Tabib56c2762008-10-10 11:52:31 -050056
57The device tree nodes for the DMA channels that are referenced by
58"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
59"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
60"fsl,mpc8610-dma-channel") can remain. If these nodes are left as
61"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
62drivers (fsldma) will attempt to use them, and it will conflict with the
63sound drivers.