blob: 2cdf01dc9fb7bd45668e559cf60c9a5922044fbc [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
18#include <linux/gpio.h>
19#include <asm/clkdev.h>
20#include <linux/msm_kgsl.h>
21#include <linux/android_pmem.h>
22#include <mach/irqs-8960.h>
Mayank Rana9f51f582011-08-04 18:35:59 +053023#include <mach/dma.h>
24#include <linux/dma-mapping.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070025#include <mach/board.h>
26#include <mach/msm_iomap.h>
27#include <mach/msm_hsusb.h>
28#include <mach/msm_sps.h>
29#include <mach/rpm.h>
30#include <mach/msm_bus_board.h>
31#include <mach/msm_memtypes.h>
Bhalchandra Gajare0e795c42011-08-15 18:10:30 -070032#include <sound/msm-dai-q6.h>
33#include <sound/apr_audio.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070034#include "clock.h"
35#include "devices.h"
36#include "devices-msm8x60.h"
37#include "footswitch.h"
38
39#ifdef CONFIG_MSM_MPM
40#include "mpm.h"
41#endif
42#ifdef CONFIG_MSM_DSPS
43#include <mach/msm_dsps.h>
44#endif
45
46
47/* Address of GSBI blocks */
48#define MSM_GSBI1_PHYS 0x16000000
49#define MSM_GSBI2_PHYS 0x16100000
50#define MSM_GSBI3_PHYS 0x16200000
51#define MSM_GSBI4_PHYS 0x16300000
52#define MSM_GSBI5_PHYS 0x16400000
53#define MSM_GSBI6_PHYS 0x16500000
54#define MSM_GSBI7_PHYS 0x16600000
55#define MSM_GSBI8_PHYS 0x1A000000
56#define MSM_GSBI9_PHYS 0x1A100000
57#define MSM_GSBI10_PHYS 0x1A200000
58#define MSM_GSBI11_PHYS 0x12440000
59#define MSM_GSBI12_PHYS 0x12480000
60
61#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000)
62#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000)
Mayank Rana9f51f582011-08-04 18:35:59 +053063#define MSM_UART6DM_PHYS (MSM_GSBI6_PHYS + 0x40000)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070064
65/* GSBI QUP devices */
66#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000)
67#define MSM_GSBI2_QUP_PHYS (MSM_GSBI2_PHYS + 0x80000)
68#define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000)
69#define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000)
70#define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000)
71#define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000)
72#define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000)
73#define MSM_GSBI8_QUP_PHYS (MSM_GSBI8_PHYS + 0x80000)
74#define MSM_GSBI9_QUP_PHYS (MSM_GSBI9_PHYS + 0x80000)
75#define MSM_GSBI10_QUP_PHYS (MSM_GSBI10_PHYS + 0x80000)
76#define MSM_GSBI11_QUP_PHYS (MSM_GSBI11_PHYS + 0x20000)
77#define MSM_GSBI12_QUP_PHYS (MSM_GSBI12_PHYS + 0x20000)
78#define MSM_QUP_SIZE SZ_4K
79
80#define MSM_PMIC1_SSBI_CMD_PHYS 0x00500000
81#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
82#define MSM_PMIC_SSBI_SIZE SZ_4K
83
84static struct resource resources_otg[] = {
85 {
86 .start = MSM8960_HSUSB_PHYS,
87 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE,
88 .flags = IORESOURCE_MEM,
89 },
90 {
91 .start = USB1_HS_IRQ,
92 .end = USB1_HS_IRQ,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -070097struct platform_device msm8960_device_otg = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070098 .name = "msm_otg",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(resources_otg),
101 .resource = resources_otg,
102 .dev = {
103 .coherent_dma_mask = 0xffffffff,
104 },
105};
106
107static struct resource resources_hsusb[] = {
108 {
109 .start = MSM8960_HSUSB_PHYS,
110 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE,
111 .flags = IORESOURCE_MEM,
112 },
113 {
114 .start = USB1_HS_IRQ,
115 .end = USB1_HS_IRQ,
116 .flags = IORESOURCE_IRQ,
117 },
118};
119
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -0700120struct platform_device msm8960_device_gadget_peripheral = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700121 .name = "msm_hsusb",
122 .id = -1,
123 .num_resources = ARRAY_SIZE(resources_hsusb),
124 .resource = resources_hsusb,
125 .dev = {
126 .coherent_dma_mask = 0xffffffff,
127 },
128};
129
130static struct resource resources_hsusb_host[] = {
131 {
132 .start = MSM8960_HSUSB_PHYS,
133 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE - 1,
134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .start = USB1_HS_IRQ,
138 .end = USB1_HS_IRQ,
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143static u64 dma_mask = 0xffffffffULL;
144struct platform_device msm_device_hsusb_host = {
145 .name = "msm_hsusb_host",
146 .id = -1,
147 .num_resources = ARRAY_SIZE(resources_hsusb_host),
148 .resource = resources_hsusb_host,
149 .dev = {
150 .dma_mask = &dma_mask,
151 .coherent_dma_mask = 0xffffffff,
152 },
153};
154
155static struct resource resources_uart_gsbi2[] = {
156 {
157 .start = MSM8960_GSBI2_UARTDM_IRQ,
158 .end = MSM8960_GSBI2_UARTDM_IRQ,
159 .flags = IORESOURCE_IRQ,
160 },
161 {
162 .start = MSM_UART2DM_PHYS,
163 .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
164 .name = "uartdm_resource",
165 .flags = IORESOURCE_MEM,
166 },
167 {
168 .start = MSM_GSBI2_PHYS,
169 .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
170 .name = "gsbi_resource",
171 .flags = IORESOURCE_MEM,
172 },
173};
174
175struct platform_device msm8960_device_uart_gsbi2 = {
176 .name = "msm_serial_hsl",
177 .id = 0,
178 .num_resources = ARRAY_SIZE(resources_uart_gsbi2),
179 .resource = resources_uart_gsbi2,
180};
Mayank Rana9f51f582011-08-04 18:35:59 +0530181/* GSBI 6 used into UARTDM Mode */
182static struct resource msm_uart_dm6_resources[] = {
183 {
184 .start = MSM_UART6DM_PHYS,
185 .end = MSM_UART6DM_PHYS + PAGE_SIZE - 1,
186 .name = "uartdm_resource",
187 .flags = IORESOURCE_MEM,
188 },
189 {
190 .start = GSBI6_UARTDM_IRQ,
191 .end = GSBI6_UARTDM_IRQ,
192 .flags = IORESOURCE_IRQ,
193 },
194 {
195 .start = MSM_GSBI6_PHYS,
196 .end = MSM_GSBI6_PHYS + 4 - 1,
197 .name = "gsbi_resource",
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .start = DMOV_HSUART_GSBI6_TX_CHAN,
202 .end = DMOV_HSUART_GSBI6_RX_CHAN,
203 .name = "uartdm_channels",
204 .flags = IORESOURCE_DMA,
205 },
206 {
207 .start = DMOV_HSUART_GSBI6_TX_CRCI,
208 .end = DMOV_HSUART_GSBI6_RX_CRCI,
209 .name = "uartdm_crci",
210 .flags = IORESOURCE_DMA,
211 },
212};
213static u64 msm_uart_dm6_dma_mask = DMA_BIT_MASK(32);
214struct platform_device msm_device_uart_dm6 = {
215 .name = "msm_serial_hs",
216 .id = 0,
217 .num_resources = ARRAY_SIZE(msm_uart_dm6_resources),
218 .resource = msm_uart_dm6_resources,
219 .dev = {
220 .dma_mask = &msm_uart_dm6_dma_mask,
221 .coherent_dma_mask = DMA_BIT_MASK(32),
222 },
223};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700224
225static struct resource resources_uart_gsbi5[] = {
226 {
227 .start = GSBI5_UARTDM_IRQ,
228 .end = GSBI5_UARTDM_IRQ,
229 .flags = IORESOURCE_IRQ,
230 },
231 {
232 .start = MSM_UART5DM_PHYS,
233 .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
234 .name = "uartdm_resource",
235 .flags = IORESOURCE_MEM,
236 },
237 {
238 .start = MSM_GSBI5_PHYS,
239 .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
240 .name = "gsbi_resource",
241 .flags = IORESOURCE_MEM,
242 },
243};
244
245struct platform_device msm8960_device_uart_gsbi5 = {
246 .name = "msm_serial_hsl",
247 .id = 0,
248 .num_resources = ARRAY_SIZE(resources_uart_gsbi5),
249 .resource = resources_uart_gsbi5,
250};
251/* MSM Video core device */
252#ifdef CONFIG_MSM_BUS_SCALING
253static struct msm_bus_vectors vidc_init_vectors[] = {
254 {
255 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
256 .dst = MSM_BUS_SLAVE_EBI_CH0,
257 .ab = 0,
258 .ib = 0,
259 },
260 {
261 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
262 .dst = MSM_BUS_SLAVE_EBI_CH0,
263 .ab = 0,
264 .ib = 0,
265 },
266 {
267 .src = MSM_BUS_MASTER_AMPSS_M0,
268 .dst = MSM_BUS_SLAVE_EBI_CH0,
269 .ab = 0,
270 .ib = 0,
271 },
272 {
273 .src = MSM_BUS_MASTER_AMPSS_M0,
274 .dst = MSM_BUS_SLAVE_EBI_CH0,
275 .ab = 0,
276 .ib = 0,
277 },
278};
279static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
280 {
281 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
282 .dst = MSM_BUS_SLAVE_EBI_CH0,
283 .ab = 54525952,
284 .ib = 436207616,
285 },
286 {
287 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
288 .dst = MSM_BUS_SLAVE_EBI_CH0,
289 .ab = 72351744,
290 .ib = 289406976,
291 },
292 {
293 .src = MSM_BUS_MASTER_AMPSS_M0,
294 .dst = MSM_BUS_SLAVE_EBI_CH0,
295 .ab = 500000,
296 .ib = 1000000,
297 },
298 {
299 .src = MSM_BUS_MASTER_AMPSS_M0,
300 .dst = MSM_BUS_SLAVE_EBI_CH0,
301 .ab = 500000,
302 .ib = 1000000,
303 },
304};
305static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
306 {
307 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
308 .dst = MSM_BUS_SLAVE_EBI_CH0,
309 .ab = 40894464,
310 .ib = 327155712,
311 },
312 {
313 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
314 .dst = MSM_BUS_SLAVE_EBI_CH0,
315 .ab = 48234496,
316 .ib = 192937984,
317 },
318 {
319 .src = MSM_BUS_MASTER_AMPSS_M0,
320 .dst = MSM_BUS_SLAVE_EBI_CH0,
321 .ab = 500000,
322 .ib = 2000000,
323 },
324 {
325 .src = MSM_BUS_MASTER_AMPSS_M0,
326 .dst = MSM_BUS_SLAVE_EBI_CH0,
327 .ab = 500000,
328 .ib = 2000000,
329 },
330};
331static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
332 {
333 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
334 .dst = MSM_BUS_SLAVE_EBI_CH0,
335 .ab = 163577856,
336 .ib = 1308622848,
337 },
338 {
339 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
340 .dst = MSM_BUS_SLAVE_EBI_CH0,
341 .ab = 219152384,
342 .ib = 876609536,
343 },
344 {
345 .src = MSM_BUS_MASTER_AMPSS_M0,
346 .dst = MSM_BUS_SLAVE_EBI_CH0,
347 .ab = 1750000,
348 .ib = 3500000,
349 },
350 {
351 .src = MSM_BUS_MASTER_AMPSS_M0,
352 .dst = MSM_BUS_SLAVE_EBI_CH0,
353 .ab = 1750000,
354 .ib = 3500000,
355 },
356};
357static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
358 {
359 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
360 .dst = MSM_BUS_SLAVE_EBI_CH0,
361 .ab = 121634816,
362 .ib = 973078528,
363 },
364 {
365 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
366 .dst = MSM_BUS_SLAVE_EBI_CH0,
367 .ab = 155189248,
368 .ib = 620756992,
369 },
370 {
371 .src = MSM_BUS_MASTER_AMPSS_M0,
372 .dst = MSM_BUS_SLAVE_EBI_CH0,
373 .ab = 1750000,
374 .ib = 7000000,
375 },
376 {
377 .src = MSM_BUS_MASTER_AMPSS_M0,
378 .dst = MSM_BUS_SLAVE_EBI_CH0,
379 .ab = 1750000,
380 .ib = 7000000,
381 },
382};
383static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
384 {
385 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
386 .dst = MSM_BUS_SLAVE_EBI_CH0,
387 .ab = 372244480,
388 .ib = 1861222400,
389 },
390 {
391 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
392 .dst = MSM_BUS_SLAVE_EBI_CH0,
393 .ab = 501219328,
394 .ib = 2004877312,
395 },
396 {
397 .src = MSM_BUS_MASTER_AMPSS_M0,
398 .dst = MSM_BUS_SLAVE_EBI_CH0,
399 .ab = 2500000,
400 .ib = 5000000,
401 },
402 {
403 .src = MSM_BUS_MASTER_AMPSS_M0,
404 .dst = MSM_BUS_SLAVE_EBI_CH0,
405 .ab = 2500000,
406 .ib = 5000000,
407 },
408};
409static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
410 {
411 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
412 .dst = MSM_BUS_SLAVE_EBI_CH0,
413 .ab = 222298112,
414 .ib = 1778384896,
415 },
416 {
417 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
418 .dst = MSM_BUS_SLAVE_EBI_CH0,
419 .ab = 330301440,
420 .ib = 1321205760,
421 },
422 {
423 .src = MSM_BUS_MASTER_AMPSS_M0,
424 .dst = MSM_BUS_SLAVE_EBI_CH0,
425 .ab = 2500000,
426 .ib = 700000000,
427 },
428 {
429 .src = MSM_BUS_MASTER_AMPSS_M0,
430 .dst = MSM_BUS_SLAVE_EBI_CH0,
431 .ab = 2500000,
432 .ib = 10000000,
433 },
434};
435
436static struct msm_bus_paths vidc_bus_client_config[] = {
437 {
438 ARRAY_SIZE(vidc_init_vectors),
439 vidc_init_vectors,
440 },
441 {
442 ARRAY_SIZE(vidc_venc_vga_vectors),
443 vidc_venc_vga_vectors,
444 },
445 {
446 ARRAY_SIZE(vidc_vdec_vga_vectors),
447 vidc_vdec_vga_vectors,
448 },
449 {
450 ARRAY_SIZE(vidc_venc_720p_vectors),
451 vidc_venc_720p_vectors,
452 },
453 {
454 ARRAY_SIZE(vidc_vdec_720p_vectors),
455 vidc_vdec_720p_vectors,
456 },
457 {
458 ARRAY_SIZE(vidc_venc_1080p_vectors),
459 vidc_venc_1080p_vectors,
460 },
461 {
462 ARRAY_SIZE(vidc_vdec_1080p_vectors),
463 vidc_vdec_1080p_vectors,
464 },
465};
466
467static struct msm_bus_scale_pdata vidc_bus_client_data = {
468 vidc_bus_client_config,
469 ARRAY_SIZE(vidc_bus_client_config),
470 .name = "vidc",
471};
472#endif
473
Mona Hossain9c430e32011-07-27 11:04:47 -0700474#ifdef CONFIG_HW_RANDOM_MSM
475/* PRNG device */
476#define MSM_PRNG_PHYS 0x1A500000
477static struct resource rng_resources = {
478 .flags = IORESOURCE_MEM,
479 .start = MSM_PRNG_PHYS,
480 .end = MSM_PRNG_PHYS + SZ_512 - 1,
481};
482
483struct platform_device msm_device_rng = {
484 .name = "msm_rng",
485 .id = 0,
486 .num_resources = 1,
487 .resource = &rng_resources,
488};
489#endif
490
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700491#define MSM_VIDC_BASE_PHYS 0x04400000
492#define MSM_VIDC_BASE_SIZE 0x00100000
493
494static struct resource msm_device_vidc_resources[] = {
495 {
496 .start = MSM_VIDC_BASE_PHYS,
497 .end = MSM_VIDC_BASE_PHYS + MSM_VIDC_BASE_SIZE - 1,
498 .flags = IORESOURCE_MEM,
499 },
500 {
501 .start = VCODEC_IRQ,
502 .end = VCODEC_IRQ,
503 .flags = IORESOURCE_IRQ,
504 },
505};
506
507struct msm_vidc_platform_data vidc_platform_data = {
508#ifdef CONFIG_MSM_BUS_SCALING
509 .vidc_bus_client_pdata = &vidc_bus_client_data,
510#endif
511 .memtype = MEMTYPE_EBI1
512};
513
514struct platform_device msm_device_vidc = {
515 .name = "msm_vidc",
516 .id = 0,
517 .num_resources = ARRAY_SIZE(msm_device_vidc_resources),
518 .resource = msm_device_vidc_resources,
519 .dev = {
520 .platform_data = &vidc_platform_data,
521 },
522};
523
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700524#define MSM_SDC1_BASE 0x12400000
525#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
526#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
527#define MSM_SDC2_BASE 0x12140000
528#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
529#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
530#define MSM_SDC2_BASE 0x12140000
531#define MSM_SDC3_BASE 0x12180000
532#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
533#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
534#define MSM_SDC4_BASE 0x121C0000
535#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
536#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
537#define MSM_SDC5_BASE 0x12200000
538#define MSM_SDC5_DML_BASE (MSM_SDC5_BASE + 0x800)
539#define MSM_SDC5_BAM_BASE (MSM_SDC5_BASE + 0x2000)
540
541static struct resource resources_sdc1[] = {
542 {
543 .name = "core_mem",
544 .flags = IORESOURCE_MEM,
545 .start = MSM_SDC1_BASE,
546 .end = MSM_SDC1_DML_BASE - 1,
547 },
548 {
549 .name = "core_irq",
550 .flags = IORESOURCE_IRQ,
551 .start = SDC1_IRQ_0,
552 .end = SDC1_IRQ_0
553 },
554#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
555 {
556 .name = "sdcc_dml_addr",
557 .start = MSM_SDC1_DML_BASE,
558 .end = MSM_SDC1_BAM_BASE - 1,
559 .flags = IORESOURCE_MEM,
560 },
561 {
562 .name = "sdcc_bam_addr",
563 .start = MSM_SDC1_BAM_BASE,
564 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
565 .flags = IORESOURCE_MEM,
566 },
567 {
568 .name = "sdcc_bam_irq",
569 .start = SDC1_BAM_IRQ,
570 .end = SDC1_BAM_IRQ,
571 .flags = IORESOURCE_IRQ,
572 },
573#endif
574};
575
576static struct resource resources_sdc2[] = {
577 {
578 .name = "core_mem",
579 .flags = IORESOURCE_MEM,
580 .start = MSM_SDC2_BASE,
581 .end = MSM_SDC2_DML_BASE - 1,
582 },
583 {
584 .name = "core_irq",
585 .flags = IORESOURCE_IRQ,
586 .start = SDC2_IRQ_0,
587 .end = SDC2_IRQ_0
588 },
589#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
590 {
591 .name = "sdcc_dml_addr",
592 .start = MSM_SDC2_DML_BASE,
593 .end = MSM_SDC2_BAM_BASE - 1,
594 .flags = IORESOURCE_MEM,
595 },
596 {
597 .name = "sdcc_bam_addr",
598 .start = MSM_SDC2_BAM_BASE,
599 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
600 .flags = IORESOURCE_MEM,
601 },
602 {
603 .name = "sdcc_bam_irq",
604 .start = SDC2_BAM_IRQ,
605 .end = SDC2_BAM_IRQ,
606 .flags = IORESOURCE_IRQ,
607 },
608#endif
609};
610
611static struct resource resources_sdc3[] = {
612 {
613 .name = "core_mem",
614 .flags = IORESOURCE_MEM,
615 .start = MSM_SDC3_BASE,
616 .end = MSM_SDC3_DML_BASE - 1,
617 },
618 {
619 .name = "core_irq",
620 .flags = IORESOURCE_IRQ,
621 .start = SDC3_IRQ_0,
622 .end = SDC3_IRQ_0
623 },
624#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
625 {
626 .name = "sdcc_dml_addr",
627 .start = MSM_SDC3_DML_BASE,
628 .end = MSM_SDC3_BAM_BASE - 1,
629 .flags = IORESOURCE_MEM,
630 },
631 {
632 .name = "sdcc_bam_addr",
633 .start = MSM_SDC3_BAM_BASE,
634 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
635 .flags = IORESOURCE_MEM,
636 },
637 {
638 .name = "sdcc_bam_irq",
639 .start = SDC3_BAM_IRQ,
640 .end = SDC3_BAM_IRQ,
641 .flags = IORESOURCE_IRQ,
642 },
643#endif
644};
645
646static struct resource resources_sdc4[] = {
647 {
648 .name = "core_mem",
649 .flags = IORESOURCE_MEM,
650 .start = MSM_SDC4_BASE,
651 .end = MSM_SDC4_DML_BASE - 1,
652 },
653 {
654 .name = "core_irq",
655 .flags = IORESOURCE_IRQ,
656 .start = SDC4_IRQ_0,
657 .end = SDC4_IRQ_0
658 },
659#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
660 {
661 .name = "sdcc_dml_addr",
662 .start = MSM_SDC4_DML_BASE,
663 .end = MSM_SDC4_BAM_BASE - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 {
667 .name = "sdcc_bam_addr",
668 .start = MSM_SDC4_BAM_BASE,
669 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
670 .flags = IORESOURCE_MEM,
671 },
672 {
673 .name = "sdcc_bam_irq",
674 .start = SDC4_BAM_IRQ,
675 .end = SDC4_BAM_IRQ,
676 .flags = IORESOURCE_IRQ,
677 },
678#endif
679};
680
681static struct resource resources_sdc5[] = {
682 {
683 .name = "core_mem",
684 .flags = IORESOURCE_MEM,
685 .start = MSM_SDC5_BASE,
686 .end = MSM_SDC5_DML_BASE - 1,
687 },
688 {
689 .name = "core_irq",
690 .flags = IORESOURCE_IRQ,
691 .start = SDC5_IRQ_0,
692 .end = SDC5_IRQ_0
693 },
694#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
695 {
696 .name = "sdcc_dml_addr",
697 .start = MSM_SDC5_DML_BASE,
698 .end = MSM_SDC5_BAM_BASE - 1,
699 .flags = IORESOURCE_MEM,
700 },
701 {
702 .name = "sdcc_bam_addr",
703 .start = MSM_SDC5_BAM_BASE,
704 .end = MSM_SDC5_BAM_BASE + (2 * SZ_4K) - 1,
705 .flags = IORESOURCE_MEM,
706 },
707 {
708 .name = "sdcc_bam_irq",
709 .start = SDC5_BAM_IRQ,
710 .end = SDC5_BAM_IRQ,
711 .flags = IORESOURCE_IRQ,
712 },
713#endif
714};
715
716struct platform_device msm_device_sdc1 = {
717 .name = "msm_sdcc",
718 .id = 1,
719 .num_resources = ARRAY_SIZE(resources_sdc1),
720 .resource = resources_sdc1,
721 .dev = {
722 .coherent_dma_mask = 0xffffffff,
723 },
724};
725
726struct platform_device msm_device_sdc2 = {
727 .name = "msm_sdcc",
728 .id = 2,
729 .num_resources = ARRAY_SIZE(resources_sdc2),
730 .resource = resources_sdc2,
731 .dev = {
732 .coherent_dma_mask = 0xffffffff,
733 },
734};
735
736struct platform_device msm_device_sdc3 = {
737 .name = "msm_sdcc",
738 .id = 3,
739 .num_resources = ARRAY_SIZE(resources_sdc3),
740 .resource = resources_sdc3,
741 .dev = {
742 .coherent_dma_mask = 0xffffffff,
743 },
744};
745
746struct platform_device msm_device_sdc4 = {
747 .name = "msm_sdcc",
748 .id = 4,
749 .num_resources = ARRAY_SIZE(resources_sdc4),
750 .resource = resources_sdc4,
751 .dev = {
752 .coherent_dma_mask = 0xffffffff,
753 },
754};
755
756struct platform_device msm_device_sdc5 = {
757 .name = "msm_sdcc",
758 .id = 5,
759 .num_resources = ARRAY_SIZE(resources_sdc5),
760 .resource = resources_sdc5,
761 .dev = {
762 .coherent_dma_mask = 0xffffffff,
763 },
764};
765
766struct platform_device msm_device_smd = {
767 .name = "msm_smd",
768 .id = -1,
769};
770
771struct platform_device msm_device_bam_dmux = {
772 .name = "BAM_RMNT",
773 .id = -1,
774};
775
Stepan Moskovchenkodf13d342011-08-03 19:01:25 -0700776static struct resource msm_dmov_resource[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700777 {
778 .start = ADM_0_SCSS_1_IRQ,
779 .end = (resource_size_t)MSM_DMOV_BASE,
780 .flags = IORESOURCE_IRQ,
781 },
782};
783
Stepan Moskovchenkodf13d342011-08-03 19:01:25 -0700784struct platform_device msm8960_device_dmov = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700785 .name = "msm_dmov",
786 .id = -1,
787 .resource = msm_dmov_resource,
788 .num_resources = ARRAY_SIZE(msm_dmov_resource),
789};
790
791static struct platform_device *msm_sdcc_devices[] __initdata = {
792 &msm_device_sdc1,
793 &msm_device_sdc2,
794 &msm_device_sdc3,
795 &msm_device_sdc4,
796 &msm_device_sdc5,
797};
798
799int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
800{
801 struct platform_device *pdev;
802
803 if (controller < 1 || controller > 5)
804 return -EINVAL;
805
806 pdev = msm_sdcc_devices[controller-1];
807 pdev->dev.platform_data = plat;
808 return platform_device_register(pdev);
809}
810
811static struct resource resources_qup_i2c_gsbi4[] = {
812 {
813 .name = "gsbi_qup_i2c_addr",
814 .start = MSM_GSBI4_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600815 .end = MSM_GSBI4_PHYS + 4 - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700816 .flags = IORESOURCE_MEM,
817 },
818 {
819 .name = "qup_phys_addr",
820 .start = MSM_GSBI4_QUP_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600821 .end = MSM_GSBI4_QUP_PHYS + MSM_QUP_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700822 .flags = IORESOURCE_MEM,
823 },
824 {
825 .name = "qup_err_intr",
826 .start = GSBI4_QUP_IRQ,
827 .end = GSBI4_QUP_IRQ,
828 .flags = IORESOURCE_IRQ,
829 },
830};
831
832struct platform_device msm8960_device_qup_i2c_gsbi4 = {
833 .name = "qup_i2c",
834 .id = 4,
835 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi4),
836 .resource = resources_qup_i2c_gsbi4,
837};
838
839static struct resource resources_qup_i2c_gsbi3[] = {
840 {
841 .name = "gsbi_qup_i2c_addr",
842 .start = MSM_GSBI3_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600843 .end = MSM_GSBI3_PHYS + 4 - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700844 .flags = IORESOURCE_MEM,
845 },
846 {
847 .name = "qup_phys_addr",
848 .start = MSM_GSBI3_QUP_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600849 .end = MSM_GSBI3_QUP_PHYS + MSM_QUP_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700850 .flags = IORESOURCE_MEM,
851 },
852 {
853 .name = "qup_err_intr",
854 .start = GSBI3_QUP_IRQ,
855 .end = GSBI3_QUP_IRQ,
856 .flags = IORESOURCE_IRQ,
857 },
858};
859
860struct platform_device msm8960_device_qup_i2c_gsbi3 = {
861 .name = "qup_i2c",
862 .id = 3,
863 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi3),
864 .resource = resources_qup_i2c_gsbi3,
865};
866
867static struct resource resources_qup_i2c_gsbi10[] = {
868 {
869 .name = "gsbi_qup_i2c_addr",
870 .start = MSM_GSBI10_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600871 .end = MSM_GSBI10_PHYS + 4 - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700872 .flags = IORESOURCE_MEM,
873 },
874 {
875 .name = "qup_phys_addr",
876 .start = MSM_GSBI10_QUP_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600877 .end = MSM_GSBI10_QUP_PHYS + MSM_QUP_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700878 .flags = IORESOURCE_MEM,
879 },
880 {
881 .name = "qup_err_intr",
882 .start = GSBI10_QUP_IRQ,
883 .end = GSBI10_QUP_IRQ,
884 .flags = IORESOURCE_IRQ,
885 },
886};
887
888struct platform_device msm8960_device_qup_i2c_gsbi10 = {
889 .name = "qup_i2c",
890 .id = 10,
891 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi10),
892 .resource = resources_qup_i2c_gsbi10,
893};
894
895static struct resource resources_qup_i2c_gsbi12[] = {
896 {
897 .name = "gsbi_qup_i2c_addr",
898 .start = MSM_GSBI12_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600899 .end = MSM_GSBI12_PHYS + 4 - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700900 .flags = IORESOURCE_MEM,
901 },
902 {
903 .name = "qup_phys_addr",
904 .start = MSM_GSBI12_QUP_PHYS,
Harini Jayaramand7614a72011-09-15 14:16:02 -0600905 .end = MSM_GSBI12_QUP_PHYS + MSM_QUP_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700906 .flags = IORESOURCE_MEM,
907 },
908 {
909 .name = "qup_err_intr",
910 .start = GSBI12_QUP_IRQ,
911 .end = GSBI12_QUP_IRQ,
912 .flags = IORESOURCE_IRQ,
913 },
914};
915
916struct platform_device msm8960_device_qup_i2c_gsbi12 = {
917 .name = "qup_i2c",
918 .id = 12,
919 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi12),
920 .resource = resources_qup_i2c_gsbi12,
921};
922
923#ifdef CONFIG_MSM_CAMERA
924struct resource msm_camera_resources[] = {
925 {
926 .name = "vfe",
927 .start = 0x04500000,
928 .end = 0x04500000 + SZ_1M - 1,
929 .flags = IORESOURCE_MEM,
930 },
931 {
932 .name = "vfe",
933 .start = VFE_IRQ,
934 .end = VFE_IRQ,
935 .flags = IORESOURCE_IRQ,
936 },
937 {
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700938 .name = "vpe",
939 .start = 0x05300000,
940 .end = 0x05300000 + SZ_1M - 1,
941 .flags = IORESOURCE_MEM,
942 },
943 {
944 .name = "vpe",
945 .start = VPE_IRQ,
946 .end = VPE_IRQ,
947 .flags = IORESOURCE_IRQ,
948 },
949 {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700950 .name = "vid_buf",
951 .flags = IORESOURCE_DMA,
952 },
953 {
954 .name = "ispif",
955 .start = 0x04800800,
956 .end = 0x04800800 + SZ_1K - 1,
957 .flags = IORESOURCE_MEM,
958 },
959 {
960 .name = "ispif",
961 .start = ISPIF_IRQ,
962 .end = ISPIF_IRQ,
963 .flags = IORESOURCE_IRQ,
964 },
965 {
966 .name = "csid0",
967 .start = 0x04800000,
968 .end = 0x04800000 + SZ_1K - 1,
969 .flags = IORESOURCE_MEM,
970 },
971 {
972 .name = "csid0",
973 .start = CSI_0_IRQ,
974 .end = CSI_0_IRQ,
975 .flags = IORESOURCE_IRQ,
976 },
977 {
978 .name = "csiphy0",
979 .start = 0x04800C00,
980 .end = 0x04800C00 + SZ_1K - 1,
981 .flags = IORESOURCE_MEM,
982 },
983 {
984 .name = "csiphy0",
985 .start = CSIPHY_4LN_IRQ,
986 .end = CSIPHY_4LN_IRQ,
987 .flags = IORESOURCE_IRQ,
988 },
989 {
990 .name = "csid1",
991 .start = 0x04800400,
992 .end = 0x04800400 + SZ_1K - 1,
993 .flags = IORESOURCE_MEM,
994 },
995 {
996 .name = "csid1",
997 .start = CSI_1_IRQ,
998 .end = CSI_1_IRQ,
999 .flags = IORESOURCE_IRQ,
1000 },
1001 {
1002 .name = "csiphy1",
1003 .start = 0x04801000,
1004 .end = 0x04801000 + SZ_1K - 1,
1005 .flags = IORESOURCE_MEM,
1006 },
1007 {
1008 .name = "csiphy1",
1009 .start = MSM8960_CSIPHY_2LN_IRQ,
1010 .end = MSM8960_CSIPHY_2LN_IRQ,
1011 .flags = IORESOURCE_IRQ,
1012 },
Nishant Pandit24153d82011-08-27 16:05:13 +05301013 {
1014 .name = "s3d_rw",
1015 .start = 0x008003E0,
1016 .end = 0x008003E0 + SZ_16 - 1,
1017 .flags = IORESOURCE_MEM,
1018 },
1019 {
1020 .name = "s3d_ctl",
1021 .start = 0x008020B8,
1022 .end = 0x008020B8 + SZ_16 - 1,
1023 .flags = IORESOURCE_MEM,
1024 },
1025
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001026};
1027
1028int __init msm_get_cam_resources(struct msm_camera_sensor_info *s_info)
1029{
1030 s_info->resource = msm_camera_resources;
1031 s_info->num_resources = ARRAY_SIZE(msm_camera_resources);
1032 return 0;
1033}
1034#endif
1035
1036static struct resource resources_ssbi_pm8921[] = {
1037 {
1038 .start = MSM_PMIC1_SSBI_CMD_PHYS,
1039 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
1040 .flags = IORESOURCE_MEM,
1041 },
1042};
1043
1044struct platform_device msm8960_device_ssbi_pm8921 = {
1045 .name = "msm_ssbi",
1046 .id = 0,
1047 .resource = resources_ssbi_pm8921,
1048 .num_resources = ARRAY_SIZE(resources_ssbi_pm8921),
1049};
1050
1051static struct resource resources_qup_spi_gsbi1[] = {
1052 {
1053 .name = "spi_base",
1054 .start = MSM_GSBI1_QUP_PHYS,
1055 .end = MSM_GSBI1_QUP_PHYS + SZ_4K - 1,
1056 .flags = IORESOURCE_MEM,
1057 },
1058 {
1059 .name = "gsbi_base",
1060 .start = MSM_GSBI1_PHYS,
1061 .end = MSM_GSBI1_PHYS + 4 - 1,
1062 .flags = IORESOURCE_MEM,
1063 },
1064 {
1065 .name = "spi_irq_in",
1066 .start = MSM8960_GSBI1_QUP_IRQ,
1067 .end = MSM8960_GSBI1_QUP_IRQ,
1068 .flags = IORESOURCE_IRQ,
1069 },
Harini Jayaramanaac8e342011-08-09 19:25:23 -06001070 {
1071 .name = "spi_clk",
1072 .start = 9,
1073 .end = 9,
1074 .flags = IORESOURCE_IO,
1075 },
1076 {
1077 .name = "spi_cs",
1078 .start = 8,
1079 .end = 8,
1080 .flags = IORESOURCE_IO,
1081 },
1082 {
1083 .name = "spi_miso",
1084 .start = 7,
1085 .end = 7,
1086 .flags = IORESOURCE_IO,
1087 },
1088 {
1089 .name = "spi_mosi",
1090 .start = 6,
1091 .end = 6,
1092 .flags = IORESOURCE_IO,
1093 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001094};
1095
1096struct platform_device msm8960_device_qup_spi_gsbi1 = {
1097 .name = "spi_qsd",
1098 .id = 0,
1099 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi1),
1100 .resource = resources_qup_spi_gsbi1,
1101};
1102
1103struct platform_device msm_pcm = {
1104 .name = "msm-pcm-dsp",
1105 .id = -1,
1106};
1107
1108struct platform_device msm_pcm_routing = {
1109 .name = "msm-pcm-routing",
1110 .id = -1,
1111};
1112
1113struct platform_device msm_cpudai0 = {
1114 .name = "msm-dai-q6",
1115 .id = 0x4000,
1116};
1117
1118struct platform_device msm_cpudai1 = {
1119 .name = "msm-dai-q6",
1120 .id = 0x4001,
1121};
1122
1123struct platform_device msm_cpudai_hdmi_rx = {
1124 .name = "msm-dai-q6",
1125 .id = 8,
1126};
1127
1128struct platform_device msm_cpudai_bt_rx = {
1129 .name = "msm-dai-q6",
1130 .id = 0x3000,
1131};
1132
1133struct platform_device msm_cpudai_bt_tx = {
1134 .name = "msm-dai-q6",
1135 .id = 0x3001,
1136};
1137
1138struct platform_device msm_cpudai_fm_rx = {
1139 .name = "msm-dai-q6",
1140 .id = 0x3004,
1141};
1142
1143struct platform_device msm_cpudai_fm_tx = {
1144 .name = "msm-dai-q6",
1145 .id = 0x3005,
1146};
1147
Bhalchandra Gajare0e795c42011-08-15 18:10:30 -07001148/*
1149 * Machine specific data for AUX PCM Interface
1150 * which the driver will be unware of.
1151 */
1152struct msm_dai_auxpcm_pdata auxpcm_rx_pdata = {
1153 .clk = "pcm_clk",
1154 .mode = AFE_PCM_CFG_MODE_PCM,
1155 .sync = AFE_PCM_CFG_SYNC_INT,
1156 .frame = AFE_PCM_CFG_FRM_256BPF,
1157 .quant = AFE_PCM_CFG_QUANT_LINEAR_NOPAD,
1158 .slot = 0,
1159 .data = AFE_PCM_CFG_CDATAOE_MASTER,
1160 .pcm_clk_rate = 2048000,
1161};
1162
1163struct platform_device msm_cpudai_auxpcm_rx = {
1164 .name = "msm-dai-q6",
1165 .id = 2,
1166 .dev = {
1167 .platform_data = &auxpcm_rx_pdata,
1168 },
1169};
1170
1171struct platform_device msm_cpudai_auxpcm_tx = {
1172 .name = "msm-dai-q6",
1173 .id = 3,
1174};
1175
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001176struct platform_device msm_cpu_fe = {
1177 .name = "msm-dai-fe",
1178 .id = -1,
1179};
1180
1181struct platform_device msm_stub_codec = {
1182 .name = "msm-stub-codec",
1183 .id = 1,
1184};
1185
1186struct platform_device msm_voice = {
1187 .name = "msm-pcm-voice",
1188 .id = -1,
1189};
1190
1191struct platform_device msm_voip = {
1192 .name = "msm-voip-dsp",
1193 .id = -1,
1194};
1195
1196struct platform_device msm_lpa_pcm = {
1197 .name = "msm-pcm-lpa",
1198 .id = -1,
1199};
1200
1201struct platform_device msm_pcm_hostless = {
1202 .name = "msm-pcm-hostless",
1203 .id = -1,
1204};
1205
Laxminath Kasamcee1d602011-08-01 19:26:57 +05301206struct platform_device msm_cpudai_afe_01_rx = {
1207 .name = "msm-dai-q6",
1208 .id = 0xE0,
1209};
1210
1211struct platform_device msm_cpudai_afe_01_tx = {
1212 .name = "msm-dai-q6",
1213 .id = 0xF0,
1214};
1215
1216struct platform_device msm_cpudai_afe_02_rx = {
1217 .name = "msm-dai-q6",
1218 .id = 0xF1,
1219};
1220
1221struct platform_device msm_cpudai_afe_02_tx = {
1222 .name = "msm-dai-q6",
1223 .id = 0xE1,
1224};
1225
1226struct platform_device msm_pcm_afe = {
1227 .name = "msm-pcm-afe",
1228 .id = -1,
1229};
1230
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001231struct platform_device *msm_footswitch_devices[] = {
Nagamalleswararao Ganjifd7454a2011-08-09 10:56:40 -07001232 FS_8X60(FS_MDP, "fs_mdp"),
1233 FS_8X60(FS_ROT, "fs_rot"),
Shuzhen Wang4d28c092011-07-14 15:40:33 -07001234 FS_8X60(FS_IJPEG, "fs_ijpeg"),
1235 FS_8X60(FS_VFE, "fs_vfe"),
1236 FS_8X60(FS_VPE, "fs_vpe"),
Lucille Sylvestera610fb12011-07-22 17:22:20 -06001237 FS_8X60(FS_GFX3D, "fs_gfx3d"),
1238 FS_8X60(FS_GFX2D0, "fs_gfx2d0"),
1239 FS_8X60(FS_GFX2D1, "fs_gfx2d1"),
Gopikrishnaiah Anandan031eb942011-07-28 13:24:00 -07001240 FS_8X60(FS_VED, "fs_ved"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001241};
1242unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
1243
1244#ifdef CONFIG_MSM_ROTATOR
1245#define ROTATOR_HW_BASE 0x04E00000
1246static struct resource resources_msm_rotator[] = {
1247 {
1248 .start = ROTATOR_HW_BASE,
1249 .end = ROTATOR_HW_BASE + 0x100000 - 1,
1250 .flags = IORESOURCE_MEM,
1251 },
1252 {
1253 .start = ROT_IRQ,
1254 .end = ROT_IRQ,
1255 .flags = IORESOURCE_IRQ,
1256 },
1257};
1258
1259static struct msm_rot_clocks rotator_clocks[] = {
1260 {
1261 .clk_name = "rot_clk",
1262 .clk_type = ROTATOR_CORE_CLK,
1263 .clk_rate = 160 * 1000 * 1000,
1264 },
1265 {
1266 .clk_name = "rotator_pclk",
1267 .clk_type = ROTATOR_PCLK,
1268 .clk_rate = 0,
1269 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001270};
1271
1272static struct msm_rotator_platform_data rotator_pdata = {
1273 .number_of_clocks = ARRAY_SIZE(rotator_clocks),
1274 .hardware_version_number = 0x01020309,
1275 .rotator_clks = rotator_clocks,
1276 .regulator_name = "fs_rot",
1277};
1278
1279struct platform_device msm_rotator_device = {
1280 .name = "msm_rotator",
1281 .id = 0,
1282 .num_resources = ARRAY_SIZE(resources_msm_rotator),
1283 .resource = resources_msm_rotator,
1284 .dev = {
1285 .platform_data = &rotator_pdata,
1286 },
1287};
1288#endif
1289
1290#define MIPI_DSI_HW_BASE 0x04700000
1291#define MDP_HW_BASE 0x05100000
1292
1293static struct resource msm_mipi_dsi1_resources[] = {
1294 {
1295 .name = "mipi_dsi",
1296 .start = MIPI_DSI_HW_BASE,
kuogee hsiehf12acf52011-09-06 10:49:43 -07001297 .end = MIPI_DSI_HW_BASE + 0x000F0000 - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001298 .flags = IORESOURCE_MEM,
1299 },
1300 {
1301 .start = DSI1_IRQ,
1302 .end = DSI1_IRQ,
1303 .flags = IORESOURCE_IRQ,
1304 },
1305};
1306
1307struct platform_device msm_mipi_dsi1_device = {
1308 .name = "mipi_dsi",
1309 .id = 1,
1310 .num_resources = ARRAY_SIZE(msm_mipi_dsi1_resources),
1311 .resource = msm_mipi_dsi1_resources,
1312};
1313
1314static struct resource msm_mdp_resources[] = {
1315 {
1316 .name = "mdp",
1317 .start = MDP_HW_BASE,
kuogee hsiehf12acf52011-09-06 10:49:43 -07001318 .end = MDP_HW_BASE + 0x000F0000 - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001319 .flags = IORESOURCE_MEM,
1320 },
1321 {
1322 .start = MDP_IRQ,
1323 .end = MDP_IRQ,
1324 .flags = IORESOURCE_IRQ,
1325 },
1326};
1327
1328static struct platform_device msm_mdp_device = {
1329 .name = "mdp",
1330 .id = 0,
1331 .num_resources = ARRAY_SIZE(msm_mdp_resources),
1332 .resource = msm_mdp_resources,
1333};
1334
1335static void __init msm_register_device(struct platform_device *pdev, void *data)
1336{
1337 int ret;
1338
1339 pdev->dev.platform_data = data;
1340 ret = platform_device_register(pdev);
1341 if (ret)
1342 dev_err(&pdev->dev,
1343 "%s: platform_device_register() failed = %d\n",
1344 __func__, ret);
1345}
1346
Ravishangar Kalyanam882930f2011-07-08 17:51:52 -07001347#ifdef CONFIG_MSM_BUS_SCALING
1348static struct platform_device msm_dtv_device = {
1349 .name = "dtv",
1350 .id = 0,
1351};
1352#endif
1353
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001354void __init msm_fb_register_device(char *name, void *data)
1355{
1356 if (!strncmp(name, "mdp", 3))
1357 msm_register_device(&msm_mdp_device, data);
1358 else if (!strncmp(name, "mipi_dsi", 8))
1359 msm_register_device(&msm_mipi_dsi1_device, data);
Ravishangar Kalyanam882930f2011-07-08 17:51:52 -07001360#ifdef CONFIG_MSM_BUS_SCALING
1361 else if (!strncmp(name, "dtv", 3))
1362 msm_register_device(&msm_dtv_device, data);
1363#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001364 else
1365 printk(KERN_ERR "%s: unknown device! %s\n", __func__, name);
1366}
1367
1368static struct resource resources_sps[] = {
1369 {
1370 .name = "pipe_mem",
1371 .start = 0x12800000,
1372 .end = 0x12800000 + 0x4000 - 1,
1373 .flags = IORESOURCE_MEM,
1374 },
1375 {
1376 .name = "bamdma_dma",
1377 .start = 0x12240000,
1378 .end = 0x12240000 + 0x1000 - 1,
1379 .flags = IORESOURCE_MEM,
1380 },
1381 {
1382 .name = "bamdma_bam",
1383 .start = 0x12244000,
1384 .end = 0x12244000 + 0x4000 - 1,
1385 .flags = IORESOURCE_MEM,
1386 },
1387 {
1388 .name = "bamdma_irq",
1389 .start = SPS_BAM_DMA_IRQ,
1390 .end = SPS_BAM_DMA_IRQ,
1391 .flags = IORESOURCE_IRQ,
1392 },
1393};
1394
1395struct msm_sps_platform_data msm_sps_pdata = {
1396 .bamdma_restricted_pipes = 0x06,
1397};
1398
1399struct platform_device msm_device_sps = {
1400 .name = "msm_sps",
1401 .id = -1,
1402 .num_resources = ARRAY_SIZE(resources_sps),
1403 .resource = resources_sps,
1404 .dev.platform_data = &msm_sps_pdata,
1405};
1406
1407#ifdef CONFIG_MSM_MPM
1408static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
Praveen Chidambaramb3d857c2011-05-31 16:28:07 -06001409 [1] = MSM_GPIO_TO_INT(46),
1410 [2] = MSM_GPIO_TO_INT(150),
1411 [4] = MSM_GPIO_TO_INT(103),
1412 [5] = MSM_GPIO_TO_INT(104),
1413 [6] = MSM_GPIO_TO_INT(105),
1414 [7] = MSM_GPIO_TO_INT(106),
1415 [8] = MSM_GPIO_TO_INT(107),
1416 [9] = MSM_GPIO_TO_INT(7),
1417 [10] = MSM_GPIO_TO_INT(11),
1418 [11] = MSM_GPIO_TO_INT(15),
1419 [12] = MSM_GPIO_TO_INT(19),
1420 [13] = MSM_GPIO_TO_INT(23),
1421 [14] = MSM_GPIO_TO_INT(27),
1422 [15] = MSM_GPIO_TO_INT(31),
1423 [16] = MSM_GPIO_TO_INT(35),
1424 [19] = MSM_GPIO_TO_INT(90),
1425 [20] = MSM_GPIO_TO_INT(92),
1426 [23] = MSM_GPIO_TO_INT(85),
1427 [24] = MSM_GPIO_TO_INT(83),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001428 [25] = USB1_HS_IRQ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001429 [27] = HDMI_IRQ,
Praveen Chidambaramb3d857c2011-05-31 16:28:07 -06001430 [29] = MSM_GPIO_TO_INT(10),
1431 [30] = MSM_GPIO_TO_INT(102),
1432 [31] = MSM_GPIO_TO_INT(81),
1433 [32] = MSM_GPIO_TO_INT(78),
1434 [33] = MSM_GPIO_TO_INT(94),
1435 [34] = MSM_GPIO_TO_INT(72),
1436 [35] = MSM_GPIO_TO_INT(39),
1437 [36] = MSM_GPIO_TO_INT(43),
1438 [37] = MSM_GPIO_TO_INT(61),
1439 [38] = MSM_GPIO_TO_INT(50),
1440 [39] = MSM_GPIO_TO_INT(42),
1441 [41] = MSM_GPIO_TO_INT(62),
1442 [42] = MSM_GPIO_TO_INT(76),
1443 [43] = MSM_GPIO_TO_INT(75),
1444 [44] = MSM_GPIO_TO_INT(70),
1445 [45] = MSM_GPIO_TO_INT(69),
1446 [46] = MSM_GPIO_TO_INT(67),
1447 [47] = MSM_GPIO_TO_INT(65),
1448 [48] = MSM_GPIO_TO_INT(58),
1449 [49] = MSM_GPIO_TO_INT(54),
1450 [50] = MSM_GPIO_TO_INT(52),
1451 [51] = MSM_GPIO_TO_INT(49),
1452 [52] = MSM_GPIO_TO_INT(40),
1453 [53] = MSM_GPIO_TO_INT(37),
1454 [54] = MSM_GPIO_TO_INT(24),
1455 [55] = MSM_GPIO_TO_INT(14),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001456};
1457
1458static uint16_t msm_mpm_bypassed_apps_irqs[] = {
1459 TLMM_MSM_SUMMARY_IRQ,
1460 RPM_APCC_CPU0_GP_HIGH_IRQ,
1461 RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1462 RPM_APCC_CPU0_GP_LOW_IRQ,
1463 RPM_APCC_CPU0_WAKE_UP_IRQ,
1464 RPM_APCC_CPU1_GP_HIGH_IRQ,
1465 RPM_APCC_CPU1_GP_MEDIUM_IRQ,
1466 RPM_APCC_CPU1_GP_LOW_IRQ,
1467 RPM_APCC_CPU1_WAKE_UP_IRQ,
1468 MSS_TO_APPS_IRQ_0,
1469 MSS_TO_APPS_IRQ_1,
1470 MSS_TO_APPS_IRQ_2,
1471 MSS_TO_APPS_IRQ_3,
1472 MSS_TO_APPS_IRQ_4,
1473 MSS_TO_APPS_IRQ_5,
1474 MSS_TO_APPS_IRQ_6,
1475 MSS_TO_APPS_IRQ_7,
1476 MSS_TO_APPS_IRQ_8,
1477 MSS_TO_APPS_IRQ_9,
1478 LPASS_SCSS_GP_LOW_IRQ,
1479 LPASS_SCSS_GP_MEDIUM_IRQ,
1480 LPASS_SCSS_GP_HIGH_IRQ,
David Collins5e2b2fd2011-09-08 15:23:30 -07001481 SPS_MTI_30,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001482 SPS_MTI_31,
David Collins5e2b2fd2011-09-08 15:23:30 -07001483 RIVA_APSS_SPARE_IRQ,
1484 RIVA_APPS_WLAN_SMSM_IRQ
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001485};
1486
1487struct msm_mpm_device_data msm_mpm_dev_data = {
1488 .irqs_m2a = msm_mpm_irqs_m2a,
1489 .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
1490 .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
1491 .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
1492 .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
1493 .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
1494 .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
1495 .mpm_apps_ipc_val = BIT(1),
1496 .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1497
1498};
1499#endif
1500
Stephen Boydbb600ae2011-08-02 20:11:40 -07001501static struct clk_lookup msm_clocks_8960_dummy[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001502 CLK_DUMMY("pll2", PLL2, NULL, 0),
1503 CLK_DUMMY("pll8", PLL8, NULL, 0),
1504 CLK_DUMMY("pll4", PLL4, NULL, 0),
1505
1506 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
1507 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
1508 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
1509 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
1510 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
1511 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
1512 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
1513 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
1514 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
1515 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
1516 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
1517 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
1518 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
1519 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
1520 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
1521 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
1522
Matt Wagantalle2522372011-08-17 14:52:21 -07001523 CLK_DUMMY("core_clk", GSBI1_UART_CLK, NULL, OFF),
1524 CLK_DUMMY("core_clk", GSBI2_UART_CLK, "msm_serial_hsl.0", OFF),
1525 CLK_DUMMY("core_clk", GSBI3_UART_CLK, NULL, OFF),
1526 CLK_DUMMY("core_clk", GSBI4_UART_CLK, NULL, OFF),
1527 CLK_DUMMY("core_clk", GSBI5_UART_CLK, NULL, OFF),
1528 CLK_DUMMY("core_clk", GSBI6_UART_CLK, NULL, OFF),
1529 CLK_DUMMY("core_clk", GSBI7_UART_CLK, NULL, OFF),
1530 CLK_DUMMY("core_clk", GSBI8_UART_CLK, NULL, OFF),
1531 CLK_DUMMY("core_clk", GSBI9_UART_CLK, NULL, OFF),
1532 CLK_DUMMY("core_clk", GSBI10_UART_CLK, NULL, OFF),
1533 CLK_DUMMY("core_clk", GSBI11_UART_CLK, NULL, OFF),
1534 CLK_DUMMY("core_clk", GSBI12_UART_CLK, NULL, OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07001535 CLK_DUMMY("core_clk", GSBI1_QUP_CLK, "spi_qsd.0", OFF),
1536 CLK_DUMMY("core_clk", GSBI2_QUP_CLK, NULL, OFF),
1537 CLK_DUMMY("core_clk", GSBI3_QUP_CLK, NULL, OFF),
1538 CLK_DUMMY("core_clk", GSBI4_QUP_CLK, "qup_i2c.4", OFF),
1539 CLK_DUMMY("core_clk", GSBI5_QUP_CLK, NULL, OFF),
1540 CLK_DUMMY("core_clk", GSBI6_QUP_CLK, NULL, OFF),
1541 CLK_DUMMY("core_clk", GSBI7_QUP_CLK, NULL, OFF),
1542 CLK_DUMMY("core_clk", GSBI8_QUP_CLK, NULL, OFF),
1543 CLK_DUMMY("core_clk", GSBI9_QUP_CLK, NULL, OFF),
1544 CLK_DUMMY("core_clk", GSBI10_QUP_CLK, NULL, OFF),
1545 CLK_DUMMY("core_clk", GSBI11_QUP_CLK, NULL, OFF),
1546 CLK_DUMMY("core_clk", GSBI12_QUP_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001547 CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
Matt Wagantalld86d6832011-08-17 14:06:55 -07001548 CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF),
Matt Wagantallc1205292011-08-11 17:19:31 -07001549 CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
Matt Wagantall37ce3842011-08-17 16:00:36 -07001550 CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF),
1551 CLK_DUMMY("core_clk", SDC2_CLK, NULL, OFF),
1552 CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF),
1553 CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF),
1554 CLK_DUMMY("core_clk", SDC5_CLK, NULL, OFF),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07001555 CLK_DUMMY("core_clk", TSIF_REF_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001556 CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
1557 CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
1558 CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL, OFF),
1559 CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
1560 CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
1561 CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
1562 CLK_DUMMY("usb_fs_src_clk", USB_FS2_SRC_CLK, NULL, OFF),
1563 CLK_DUMMY("usb_fs_clk", USB_FS2_XCVR_CLK, NULL, OFF),
1564 CLK_DUMMY("usb_fs_sys_clk", USB_FS2_SYS_CLK, NULL, OFF),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07001565 CLK_DUMMY("iface_clk", CE2_CLK, "qce.0", OFF),
1566 CLK_DUMMY("core_clk", CE1_CORE_CLK, "qce.0", OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07001567 CLK_DUMMY("iface_clk", GSBI1_P_CLK, "spi_qsd.0", OFF),
1568 CLK_DUMMY("iface_clk", GSBI2_P_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001569 "msm_serial_hsl.0", OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07001570 CLK_DUMMY("iface_clk", GSBI3_P_CLK, NULL, OFF),
Matt Wagantallac294852011-08-17 15:44:58 -07001571 CLK_DUMMY("iface_clk", GSBI4_P_CLK, "qup_i2c.4", OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07001572 CLK_DUMMY("iface_clk", GSBI5_P_CLK, NULL, OFF),
Matt Wagantalle2522372011-08-17 14:52:21 -07001573 CLK_DUMMY("iface_clk", GSBI6_P_CLK, NULL, OFF),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07001574 CLK_DUMMY("iface_clk", GSBI7_P_CLK, NULL, OFF),
1575 CLK_DUMMY("iface_clk", GSBI8_P_CLK, NULL, OFF),
1576 CLK_DUMMY("iface_clk", GSBI9_P_CLK, NULL, OFF),
1577 CLK_DUMMY("iface_clk", GSBI10_P_CLK, NULL, OFF),
1578 CLK_DUMMY("iface_clk", GSBI11_P_CLK, NULL, OFF),
1579 CLK_DUMMY("iface_clk", GSBI12_P_CLK, NULL, OFF),
1580 CLK_DUMMY("iface_clk", GSBI12_P_CLK, NULL, OFF),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07001581 CLK_DUMMY("iface_clk", TSIF_P_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001582 CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
1583 CLK_DUMMY("usb_fs_pclk", USB_FS2_P_CLK, NULL, OFF),
1584 CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
Matt Wagantall37ce3842011-08-17 16:00:36 -07001585 CLK_DUMMY("iface_clk", SDC1_P_CLK, NULL, OFF),
1586 CLK_DUMMY("iface_clk", SDC2_P_CLK, NULL, OFF),
1587 CLK_DUMMY("iface_clk", SDC3_P_CLK, NULL, OFF),
1588 CLK_DUMMY("iface_clk", SDC4_P_CLK, NULL, OFF),
1589 CLK_DUMMY("iface_clk", SDC5_P_CLK, NULL, OFF),
Matt Wagantalle1a86062011-08-18 17:46:10 -07001590 CLK_DUMMY("core_clk", ADM0_CLK, NULL, OFF),
1591 CLK_DUMMY("iface_clk", ADM0_P_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001592 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
1593 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
1594 CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
1595 CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
1596 CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
1597 CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
1598 CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
1599 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
1600 CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
1601 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
1602 CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
1603 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
1604 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
1605 CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
1606 CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
1607 CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
1608 CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, "mipi_dsi.1", OFF),
1609 CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, "mipi_dsi.2", OFF),
1610 CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, "mipi_dsi.1", OFF),
1611 CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, "mipi_dsi.2", OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -07001612 CLK_DUMMY("core_clk", GFX2D0_CLK, NULL, OFF),
1613 CLK_DUMMY("core_clk", GFX2D1_CLK, NULL, OFF),
1614 CLK_DUMMY("core_clk", GFX3D_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001615 CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -07001616 CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001617 CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
1618 CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
1619 CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
1620 CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
1621 CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
1622 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
1623 CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
1624 CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
1625 CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
1626 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
1627 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
1628 CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
1629 CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
1630 CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
1631 CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
1632 CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
1633 CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
1634 CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
1635 CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL, OFF),
1636 CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
1637 CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
1638 CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
1639 CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
1640 CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
1641 CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
1642 CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, "mipi_dsi.1", OFF),
1643 CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, "mipi_dsi.1", OFF),
1644 CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, "mipi_dsi.2", OFF),
1645 CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, "mipi_dsi.2", OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -07001646 CLK_DUMMY("iface_clk", GFX2D0_P_CLK, NULL, OFF),
1647 CLK_DUMMY("iface_clk", GFX2D1_P_CLK, NULL, OFF),
1648 CLK_DUMMY("iface_clk", GFX3D_P_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001649 CLK_DUMMY("hdmi_m_pclk", HDMI_M_P_CLK, NULL, OFF),
1650 CLK_DUMMY("hdmi_s_pclk", HDMI_S_P_CLK, NULL, OFF),
1651 CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
1652 CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
Matt Wagantall9dc01632011-08-17 18:55:04 -07001653 CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001654 CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
1655 CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL, OFF),
1656 CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
1657 CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
1658 CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
1659 CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
1660 CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
1661 CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
1662 CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
1663 CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
1664 CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
1665 CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
1666 CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
1667 CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
1668 CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
1669 CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
1670 CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
1671 CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
1672 CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL, 0),
1673 CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL, 0),
1674 CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL, 0),
1675 CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL, 0),
1676 CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL, 0),
1677 CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL, 0),
1678
1679 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
1680 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
Matt Wagantall37ce3842011-08-17 16:00:36 -07001681 CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, "msm_sdcc.1", 0),
1682 CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, "msm_sdcc.2", 0),
1683 CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, "msm_sdcc.3", 0),
1684 CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, "msm_sdcc.4", 0),
1685 CLK_DUMMY("bus_clk", DFAB_SDC5_CLK, "msm_sdcc.5", 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001686 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
1687 CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
1688};
1689
Stephen Boydbb600ae2011-08-02 20:11:40 -07001690struct clock_init_data msm8960_dummy_clock_init_data __initdata = {
1691 .table = msm_clocks_8960_dummy,
1692 .size = ARRAY_SIZE(msm_clocks_8960_dummy),
1693};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001694
1695#define LPASS_SLIMBUS_PHYS 0x28080000
1696#define LPASS_SLIMBUS_BAM_PHYS 0x28084000
1697/* Board info for the slimbus slave device */
1698static struct resource slimbus_res[] = {
1699 {
1700 .start = LPASS_SLIMBUS_PHYS,
1701 .end = LPASS_SLIMBUS_PHYS + 8191,
1702 .flags = IORESOURCE_MEM,
1703 .name = "slimbus_physical",
1704 },
1705 {
1706 .start = LPASS_SLIMBUS_BAM_PHYS,
1707 .end = LPASS_SLIMBUS_BAM_PHYS + 8191,
1708 .flags = IORESOURCE_MEM,
1709 .name = "slimbus_bam_physical",
1710 },
1711 {
1712 .start = SLIMBUS0_CORE_EE1_IRQ,
1713 .end = SLIMBUS0_CORE_EE1_IRQ,
1714 .flags = IORESOURCE_IRQ,
1715 .name = "slimbus_irq",
1716 },
1717 {
1718 .start = SLIMBUS0_BAM_EE1_IRQ,
1719 .end = SLIMBUS0_BAM_EE1_IRQ,
1720 .flags = IORESOURCE_IRQ,
1721 .name = "slimbus_bam_irq",
1722 },
1723};
1724
1725struct platform_device msm_slim_ctrl = {
1726 .name = "msm_slim_ctrl",
1727 .id = 1,
1728 .num_resources = ARRAY_SIZE(slimbus_res),
1729 .resource = slimbus_res,
1730 .dev = {
1731 .coherent_dma_mask = 0xffffffffULL,
1732 },
1733};
1734
1735#ifdef CONFIG_MSM_BUS_SCALING
1736static struct msm_bus_vectors grp3d_init_vectors[] = {
1737 {
1738 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1739 .dst = MSM_BUS_SLAVE_EBI_CH0,
1740 .ab = 0,
1741 .ib = 0,
1742 },
1743};
1744
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001745static struct msm_bus_vectors grp3d_low_vectors[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001746 {
1747 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1748 .dst = MSM_BUS_SLAVE_EBI_CH0,
1749 .ab = 0,
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001750 .ib = 1200000000U,
1751 },
1752};
1753
1754static struct msm_bus_vectors grp3d_nominal_low_vectors[] = {
1755 {
1756 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1757 .dst = MSM_BUS_SLAVE_EBI_CH0,
1758 .ab = 0,
1759 .ib = 2048000000U,
1760 },
1761};
1762
1763static struct msm_bus_vectors grp3d_nominal_high_vectors[] = {
1764 {
1765 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1766 .dst = MSM_BUS_SLAVE_EBI_CH0,
1767 .ab = 0,
1768 .ib = 2656000000U,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001769 },
1770};
1771
1772static struct msm_bus_vectors grp3d_max_vectors[] = {
1773 {
1774 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1775 .dst = MSM_BUS_SLAVE_EBI_CH0,
1776 .ab = 0,
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001777 .ib = 3968000000U,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001778 },
1779};
1780
1781static struct msm_bus_paths grp3d_bus_scale_usecases[] = {
1782 {
1783 ARRAY_SIZE(grp3d_init_vectors),
1784 grp3d_init_vectors,
1785 },
1786 {
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001787 ARRAY_SIZE(grp3d_low_vectors),
1788 grp3d_low_vectors,
1789 },
1790 {
1791 ARRAY_SIZE(grp3d_nominal_low_vectors),
1792 grp3d_nominal_low_vectors,
1793 },
1794 {
1795 ARRAY_SIZE(grp3d_nominal_high_vectors),
1796 grp3d_nominal_high_vectors,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001797 },
1798 {
1799 ARRAY_SIZE(grp3d_max_vectors),
1800 grp3d_max_vectors,
1801 },
1802};
1803
1804static struct msm_bus_scale_pdata grp3d_bus_scale_pdata = {
1805 grp3d_bus_scale_usecases,
1806 ARRAY_SIZE(grp3d_bus_scale_usecases),
1807 .name = "grp3d",
1808};
1809
1810static struct msm_bus_vectors grp2d0_init_vectors[] = {
1811 {
1812 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
1813 .dst = MSM_BUS_SLAVE_EBI_CH0,
1814 .ab = 0,
1815 .ib = 0,
1816 },
1817};
1818
1819static struct msm_bus_vectors grp2d0_max_vectors[] = {
1820 {
1821 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
1822 .dst = MSM_BUS_SLAVE_EBI_CH0,
1823 .ab = 0,
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001824 .ib = 204800000U,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001825 },
1826};
1827
1828static struct msm_bus_paths grp2d0_bus_scale_usecases[] = {
1829 {
1830 ARRAY_SIZE(grp2d0_init_vectors),
1831 grp2d0_init_vectors,
1832 },
1833 {
1834 ARRAY_SIZE(grp2d0_max_vectors),
1835 grp2d0_max_vectors,
1836 },
1837};
1838
1839struct msm_bus_scale_pdata grp2d0_bus_scale_pdata = {
1840 grp2d0_bus_scale_usecases,
1841 ARRAY_SIZE(grp2d0_bus_scale_usecases),
1842 .name = "grp2d0",
1843};
1844
1845static struct msm_bus_vectors grp2d1_init_vectors[] = {
1846 {
1847 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
1848 .dst = MSM_BUS_SLAVE_EBI_CH0,
1849 .ab = 0,
1850 .ib = 0,
1851 },
1852};
1853
1854static struct msm_bus_vectors grp2d1_max_vectors[] = {
1855 {
1856 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
1857 .dst = MSM_BUS_SLAVE_EBI_CH0,
1858 .ab = 0,
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001859 .ib = 204800000U,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001860 },
1861};
1862
1863static struct msm_bus_paths grp2d1_bus_scale_usecases[] = {
1864 {
1865 ARRAY_SIZE(grp2d1_init_vectors),
1866 grp2d1_init_vectors,
1867 },
1868 {
1869 ARRAY_SIZE(grp2d1_max_vectors),
1870 grp2d1_max_vectors,
1871 },
1872};
1873
1874struct msm_bus_scale_pdata grp2d1_bus_scale_pdata = {
1875 grp2d1_bus_scale_usecases,
1876 ARRAY_SIZE(grp2d1_bus_scale_usecases),
1877 .name = "grp2d1",
1878};
1879#endif
1880
1881static struct resource kgsl_3d0_resources[] = {
1882 {
1883 .name = KGSL_3D0_REG_MEMORY,
1884 .start = 0x04300000, /* GFX3D address */
1885 .end = 0x0431ffff,
1886 .flags = IORESOURCE_MEM,
1887 },
1888 {
1889 .name = KGSL_3D0_IRQ,
1890 .start = GFX3D_IRQ,
1891 .end = GFX3D_IRQ,
1892 .flags = IORESOURCE_IRQ,
1893 },
1894};
1895
1896static struct kgsl_device_platform_data kgsl_3d0_pdata = {
1897 .pwr_data = {
1898 .pwrlevel = {
1899 {
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001900 .gpu_freq = 400000000,
1901 .bus_freq = 4,
1902 },
1903 {
1904 .gpu_freq = 300000000,
1905 .bus_freq = 3,
1906 },
1907 {
1908 .gpu_freq = 200000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001909 .bus_freq = 2,
1910 },
1911 {
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001912 .gpu_freq = 128000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001913 .bus_freq = 1,
1914 },
1915 {
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001916 .gpu_freq = 27000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001917 .bus_freq = 0,
1918 },
1919 },
Lucille Sylvester5d0ac132011-09-21 10:15:01 -06001920 .init_level = 0,
Lucille Sylvester34ec3692011-08-16 16:28:04 -06001921 .num_levels = 5,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001922 .set_grp_async = NULL,
1923 .idle_timeout = HZ/5,
Lucille Sylvester0a98de92011-09-13 17:20:55 -06001924 .nap_allowed = false,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001925 },
1926 .clk = {
1927 .name = {
Matt Wagantall9dc01632011-08-17 18:55:04 -07001928 .clk = "core_clk",
1929 .pclk = "iface_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001930 },
1931#ifdef CONFIG_MSM_BUS_SCALING
1932 .bus_scale_table = &grp3d_bus_scale_pdata,
1933#endif
1934 },
1935 .imem_clk_name = {
1936 .clk = NULL,
Matt Wagantall9dc01632011-08-17 18:55:04 -07001937 .pclk = "mem_iface_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001938 },
1939};
1940
1941struct platform_device msm_kgsl_3d0 = {
1942 .name = "kgsl-3d0",
1943 .id = 0,
1944 .num_resources = ARRAY_SIZE(kgsl_3d0_resources),
1945 .resource = kgsl_3d0_resources,
1946 .dev = {
1947 .platform_data = &kgsl_3d0_pdata,
1948 },
1949};
1950
1951static struct resource kgsl_2d0_resources[] = {
1952 {
1953 .name = KGSL_2D0_REG_MEMORY,
1954 .start = 0x04100000, /* Z180 base address */
1955 .end = 0x04100FFF,
1956 .flags = IORESOURCE_MEM,
1957 },
1958 {
1959 .name = KGSL_2D0_IRQ,
1960 .start = GFX2D0_IRQ,
1961 .end = GFX2D0_IRQ,
1962 .flags = IORESOURCE_IRQ,
1963 },
1964};
1965
1966static struct kgsl_device_platform_data kgsl_2d0_pdata = {
1967 .pwr_data = {
1968 .pwrlevel = {
1969 {
1970 .gpu_freq = 200000000,
1971 .bus_freq = 1,
1972 },
1973 {
1974 .gpu_freq = 200000000,
1975 .bus_freq = 0,
1976 },
1977 },
1978 .init_level = 0,
1979 .num_levels = 2,
1980 .set_grp_async = NULL,
1981 .idle_timeout = HZ/10,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001982 .nap_allowed = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001983 },
1984 .clk = {
1985 .name = {
1986 /* note: 2d clocks disabled on v1 */
Matt Wagantall9dc01632011-08-17 18:55:04 -07001987 .clk = "core_clk",
1988 .pclk = "iface_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001989 },
1990#ifdef CONFIG_MSM_BUS_SCALING
1991 .bus_scale_table = &grp2d0_bus_scale_pdata,
1992#endif
1993 },
1994};
1995
1996struct platform_device msm_kgsl_2d0 = {
1997 .name = "kgsl-2d0",
1998 .id = 0,
1999 .num_resources = ARRAY_SIZE(kgsl_2d0_resources),
2000 .resource = kgsl_2d0_resources,
2001 .dev = {
2002 .platform_data = &kgsl_2d0_pdata,
2003 },
2004};
2005
2006static struct resource kgsl_2d1_resources[] = {
2007 {
2008 .name = KGSL_2D1_REG_MEMORY,
2009 .start = 0x04200000, /* Z180 device 1 base address */
2010 .end = 0x04200FFF,
2011 .flags = IORESOURCE_MEM,
2012 },
2013 {
2014 .name = KGSL_2D1_IRQ,
2015 .start = GFX2D1_IRQ,
2016 .end = GFX2D1_IRQ,
2017 .flags = IORESOURCE_IRQ,
2018 },
2019};
2020
2021static struct kgsl_device_platform_data kgsl_2d1_pdata = {
2022 .pwr_data = {
2023 .pwrlevel = {
2024 {
2025 .gpu_freq = 200000000,
2026 .bus_freq = 1,
2027 },
2028 {
2029 .gpu_freq = 200000000,
2030 .bus_freq = 0,
2031 },
2032 },
2033 .init_level = 0,
2034 .num_levels = 2,
2035 .set_grp_async = NULL,
2036 .idle_timeout = HZ/10,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002037 .nap_allowed = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002038 },
2039 .clk = {
2040 .name = {
Matt Wagantall9dc01632011-08-17 18:55:04 -07002041 .clk = "core_clk",
2042 .pclk = "iface_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002043 },
2044#ifdef CONFIG_MSM_BUS_SCALING
2045 .bus_scale_table = &grp2d1_bus_scale_pdata,
2046#endif
2047 },
2048};
2049
2050struct platform_device msm_kgsl_2d1 = {
2051 .name = "kgsl-2d1",
2052 .id = 1,
2053 .num_resources = ARRAY_SIZE(kgsl_2d1_resources),
2054 .resource = kgsl_2d1_resources,
2055 .dev = {
2056 .platform_data = &kgsl_2d1_pdata,
2057 },
2058};
2059
2060#ifdef CONFIG_MSM_GEMINI
2061static struct resource msm_gemini_resources[] = {
2062 {
2063 .start = 0x04600000,
2064 .end = 0x04600000 + SZ_1M - 1,
2065 .flags = IORESOURCE_MEM,
2066 },
2067 {
2068 .start = JPEG_IRQ,
2069 .end = JPEG_IRQ,
2070 .flags = IORESOURCE_IRQ,
2071 },
2072};
2073
2074struct platform_device msm8960_gemini_device = {
2075 .name = "msm_gemini",
2076 .resource = msm_gemini_resources,
2077 .num_resources = ARRAY_SIZE(msm_gemini_resources),
2078};
2079#endif
2080
2081struct msm_rpm_map_data rpm_map_data[] __initdata = {
2082 MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
2083 MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
2084
2085 MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
2086
2087 MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
2088 MSM_RPM_MAP(PXO_CLK, PXO_CLK, 1),
2089 MSM_RPM_MAP(APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
2090 MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
2091 MSM_RPM_MAP(MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
2092 MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
2093 MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
2094 MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
2095 MSM_RPM_MAP(MMFPB_CLK, MMFPB_CLK, 1),
2096 MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
2097
2098 MSM_RPM_MAP(APPS_FABRIC_CFG_HALT_0, APPS_FABRIC_CFG_HALT, 2),
2099 MSM_RPM_MAP(APPS_FABRIC_CFG_CLKMOD_0, APPS_FABRIC_CFG_CLKMOD, 3),
2100 MSM_RPM_MAP(APPS_FABRIC_CFG_IOCTL, APPS_FABRIC_CFG_IOCTL, 1),
2101 MSM_RPM_MAP(APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
2102
2103 MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
2104 MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
2105 MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
Eugene Seahd9040ad2011-07-11 13:20:54 -06002106 MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002107
2108 MSM_RPM_MAP(MMSS_FABRIC_CFG_HALT_0, MMSS_FABRIC_CFG_HALT, 2),
2109 MSM_RPM_MAP(MMSS_FABRIC_CFG_CLKMOD_0, MMSS_FABRIC_CFG_CLKMOD, 3),
2110 MSM_RPM_MAP(MMSS_FABRIC_CFG_IOCTL, MMSS_FABRIC_CFG_IOCTL, 1),
2111 MSM_RPM_MAP(MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
2112
2113 MSM_RPM_MAP(PM8921_S1_0, PM8921_S1, 2),
2114 MSM_RPM_MAP(PM8921_S2_0, PM8921_S2, 2),
2115 MSM_RPM_MAP(PM8921_S3_0, PM8921_S3, 2),
2116 MSM_RPM_MAP(PM8921_S4_0, PM8921_S4, 2),
2117 MSM_RPM_MAP(PM8921_S5_0, PM8921_S5, 2),
2118 MSM_RPM_MAP(PM8921_S6_0, PM8921_S6, 2),
2119 MSM_RPM_MAP(PM8921_S7_0, PM8921_S7, 2),
2120 MSM_RPM_MAP(PM8921_S8_0, PM8921_S8, 2),
2121 MSM_RPM_MAP(PM8921_L1_0, PM8921_L1, 2),
2122 MSM_RPM_MAP(PM8921_L2_0, PM8921_L2, 2),
2123 MSM_RPM_MAP(PM8921_L3_0, PM8921_L3, 2),
2124 MSM_RPM_MAP(PM8921_L4_0, PM8921_L4, 2),
2125 MSM_RPM_MAP(PM8921_L5_0, PM8921_L5, 2),
2126 MSM_RPM_MAP(PM8921_L6_0, PM8921_L6, 2),
2127 MSM_RPM_MAP(PM8921_L7_0, PM8921_L7, 2),
2128 MSM_RPM_MAP(PM8921_L8_0, PM8921_L8, 2),
2129 MSM_RPM_MAP(PM8921_L9_0, PM8921_L9, 2),
2130 MSM_RPM_MAP(PM8921_L10_0, PM8921_L10, 2),
2131 MSM_RPM_MAP(PM8921_L11_0, PM8921_L11, 2),
2132 MSM_RPM_MAP(PM8921_L12_0, PM8921_L12, 2),
2133 MSM_RPM_MAP(PM8921_L13_0, PM8921_L13, 2),
2134 MSM_RPM_MAP(PM8921_L14_0, PM8921_L14, 2),
2135 MSM_RPM_MAP(PM8921_L15_0, PM8921_L15, 2),
2136 MSM_RPM_MAP(PM8921_L16_0, PM8921_L16, 2),
2137 MSM_RPM_MAP(PM8921_L17_0, PM8921_L17, 2),
2138 MSM_RPM_MAP(PM8921_L18_0, PM8921_L18, 2),
2139 MSM_RPM_MAP(PM8921_L19_0, PM8921_L19, 2),
2140 MSM_RPM_MAP(PM8921_L20_0, PM8921_L20, 2),
2141 MSM_RPM_MAP(PM8921_L21_0, PM8921_L21, 2),
2142 MSM_RPM_MAP(PM8921_L22_0, PM8921_L22, 2),
2143 MSM_RPM_MAP(PM8921_L23_0, PM8921_L23, 2),
2144 MSM_RPM_MAP(PM8921_L24_0, PM8921_L24, 2),
2145 MSM_RPM_MAP(PM8921_L25_0, PM8921_L25, 2),
2146 MSM_RPM_MAP(PM8921_L26_0, PM8921_L26, 2),
2147 MSM_RPM_MAP(PM8921_L27_0, PM8921_L27, 2),
2148 MSM_RPM_MAP(PM8921_L28_0, PM8921_L28, 2),
2149 MSM_RPM_MAP(PM8921_L29_0, PM8921_L29, 2),
2150 MSM_RPM_MAP(PM8921_CLK1_0, PM8921_CLK1, 2),
2151 MSM_RPM_MAP(PM8921_CLK2_0, PM8921_CLK2, 2),
2152 MSM_RPM_MAP(PM8921_LVS1, PM8921_LVS1, 1),
2153 MSM_RPM_MAP(PM8921_LVS2, PM8921_LVS2, 1),
2154 MSM_RPM_MAP(PM8921_LVS3, PM8921_LVS3, 1),
2155 MSM_RPM_MAP(PM8921_LVS4, PM8921_LVS4, 1),
2156 MSM_RPM_MAP(PM8921_LVS5, PM8921_LVS5, 1),
2157 MSM_RPM_MAP(PM8921_LVS6, PM8921_LVS6, 1),
2158 MSM_RPM_MAP(PM8921_LVS7, PM8921_LVS7, 1),
2159 MSM_RPM_MAP(NCP_0, NCP, 2),
2160 MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
2161 MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
2162 MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
Praveen Chidambaram27658c22011-07-07 11:00:49 -06002163 MSM_RPM_MAP(DDR_DMM_0, DDR_DMM, 2),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002164
2165};
2166unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
2167
2168struct platform_device msm_bus_sys_fabric = {
2169 .name = "msm_bus_fabric",
2170 .id = MSM_BUS_FAB_SYSTEM,
2171};
2172struct platform_device msm_bus_apps_fabric = {
2173 .name = "msm_bus_fabric",
2174 .id = MSM_BUS_FAB_APPSS,
2175};
2176struct platform_device msm_bus_mm_fabric = {
2177 .name = "msm_bus_fabric",
2178 .id = MSM_BUS_FAB_MMSS,
2179};
2180struct platform_device msm_bus_sys_fpb = {
2181 .name = "msm_bus_fabric",
2182 .id = MSM_BUS_FAB_SYSTEM_FPB,
2183};
2184struct platform_device msm_bus_cpss_fpb = {
2185 .name = "msm_bus_fabric",
2186 .id = MSM_BUS_FAB_CPSS_FPB,
2187};
2188
2189/* Sensors DSPS platform data */
2190#ifdef CONFIG_MSM_DSPS
2191
2192#define PPSS_REG_PHYS_BASE 0x12080000
2193
2194static struct dsps_clk_info dsps_clks[] = {};
2195static struct dsps_regulator_info dsps_regs[] = {};
2196
2197/*
2198 * Note: GPIOs field is intialized in run-time at the function
2199 * msm8960_init_dsps().
2200 */
2201
2202struct msm_dsps_platform_data msm_dsps_pdata = {
2203 .clks = dsps_clks,
2204 .clks_num = ARRAY_SIZE(dsps_clks),
2205 .gpios = NULL,
2206 .gpios_num = 0,
2207 .regs = dsps_regs,
2208 .regs_num = ARRAY_SIZE(dsps_regs),
2209 .dsps_pwr_ctl_en = 1,
2210 .signature = DSPS_SIGNATURE,
2211};
2212
2213static struct resource msm_dsps_resources[] = {
2214 {
2215 .start = PPSS_REG_PHYS_BASE,
2216 .end = PPSS_REG_PHYS_BASE + SZ_8K - 1,
2217 .name = "ppss_reg",
2218 .flags = IORESOURCE_MEM,
2219 },
Wentao Xua55500b2011-08-16 18:15:04 -04002220
2221 {
2222 .start = PPSS_WDOG_TIMER_IRQ,
2223 .end = PPSS_WDOG_TIMER_IRQ,
2224 .name = "ppss_wdog",
2225 .flags = IORESOURCE_IRQ,
2226 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002227};
2228
2229struct platform_device msm_dsps_device = {
2230 .name = "msm_dsps",
2231 .id = 0,
2232 .num_resources = ARRAY_SIZE(msm_dsps_resources),
2233 .resource = msm_dsps_resources,
2234 .dev.platform_data = &msm_dsps_pdata,
2235};
2236
2237#endif /* CONFIG_MSM_DSPS */
Pratik Patel7831c082011-06-08 21:44:37 -07002238
2239#ifdef CONFIG_MSM_QDSS
2240
2241#define MSM_QDSS_PHYS_BASE 0x01A00000
2242#define MSM_ETB_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x1000)
2243#define MSM_TPIU_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x3000)
2244#define MSM_FUNNEL_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x4000)
2245#define MSM_PTM_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x1C000)
2246
2247static struct resource msm_etb_resources[] = {
2248 {
2249 .start = MSM_ETB_PHYS_BASE,
2250 .end = MSM_ETB_PHYS_BASE + SZ_4K - 1,
2251 .flags = IORESOURCE_MEM,
2252 },
2253};
2254
2255struct platform_device msm_etb_device = {
2256 .name = "msm_etb",
2257 .id = 0,
2258 .num_resources = ARRAY_SIZE(msm_etb_resources),
2259 .resource = msm_etb_resources,
2260};
2261
2262static struct resource msm_tpiu_resources[] = {
2263 {
2264 .start = MSM_TPIU_PHYS_BASE,
2265 .end = MSM_TPIU_PHYS_BASE + SZ_4K - 1,
2266 .flags = IORESOURCE_MEM,
2267 },
2268};
2269
2270struct platform_device msm_tpiu_device = {
2271 .name = "msm_tpiu",
2272 .id = 0,
2273 .num_resources = ARRAY_SIZE(msm_tpiu_resources),
2274 .resource = msm_tpiu_resources,
2275};
2276
2277static struct resource msm_funnel_resources[] = {
2278 {
2279 .start = MSM_FUNNEL_PHYS_BASE,
2280 .end = MSM_FUNNEL_PHYS_BASE + SZ_4K - 1,
2281 .flags = IORESOURCE_MEM,
2282 },
2283};
2284
2285struct platform_device msm_funnel_device = {
2286 .name = "msm_funnel",
2287 .id = 0,
2288 .num_resources = ARRAY_SIZE(msm_funnel_resources),
2289 .resource = msm_funnel_resources,
2290};
2291
2292static struct resource msm_ptm_resources[] = {
2293 {
2294 .start = MSM_PTM_PHYS_BASE,
2295 .end = MSM_PTM_PHYS_BASE + (SZ_4K * 2) - 1,
2296 .flags = IORESOURCE_MEM,
2297 },
2298};
2299
2300struct platform_device msm_ptm_device = {
2301 .name = "msm_ptm",
2302 .id = 0,
2303 .num_resources = ARRAY_SIZE(msm_ptm_resources),
2304 .resource = msm_ptm_resources,
2305};
2306
2307#endif