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review.evervolv.com / android_kernel_htc_msm8960 / 0fd0c21be71293d8a54d9075b18b5a25a1868057 / . / arch / arm / mach-omap2 / cm2xxx_3xxx.c
blob: 6b0c7c85ef530269d50e9f4578ca7cbf3b0ea2de [file] [log] [blame]
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]1/*
2 * OMAP2/3 CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]13#include <linux/types.h>
14#include <linux/delay.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
Paul Walmsley6f8b7ff2009-12-08 16:33:16 -0700[diff] [blame]21#include <plat/common.h>
22
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]23#include "cm.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]24#include "cm2xxx_3xxx.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]25#include "cm-regbits-24xx.h"
26#include "cm-regbits-34xx.h"
27
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700[diff] [blame^]28/* CM_AUTOIDLE_PLL.AUTO_* bit values */
29#define DPLL_AUTOIDLE_DISABLE 0x0
30#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
31
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]32static const u8 cm_idlest_offs[] = {
33 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
34};
35
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]36u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]37{
38 return __raw_readl(cm_base + module + idx);
39}
40
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]41void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]42{
43 __raw_writel(val, cm_base + module + idx);
44}
45
46/* Read-modify-write a register in a CM module. Caller must lock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]47u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]48{
49 u32 v;
50
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]51 v = omap2_cm_read_mod_reg(module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]52 v &= ~mask;
53 v |= bits;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]54 omap2_cm_write_mod_reg(v, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]55
56 return v;
57}
58
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]59u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]60{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]61 return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]62}
63
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]64u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]65{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]66 return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]67}
68
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]69/*
70 *
71 */
72
73static void _write_clktrctrl(u8 c, s16 module, u32 mask)
74{
75 u32 v;
76
77 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
78 v &= ~mask;
79 v |= c << __ffs(mask);
80 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
81}
82
83bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
84{
85 u32 v;
86 bool ret = 0;
87
88 BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
89
90 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
91 v &= mask;
92 v >>= __ffs(mask);
93
94 if (cpu_is_omap24xx())
95 ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
96 else
97 ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
98
99 return ret;
100}
101
102void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
103{
104 _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
105}
106
107void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
108{
109 _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
110}
111
112void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
113{
114 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
115}
116
117void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
118{
119 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
120}
121
122void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
123{
124 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
125}
126
127void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
128{
129 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
130}
131
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700[diff] [blame^]132/*
133 * DPLL autoidle control
134 */
135
136static void _omap2xxx_set_dpll_autoidle(u8 m)
137{
138 u32 v;
139
140 v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
141 v &= ~OMAP24XX_AUTO_DPLL_MASK;
142 v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
143 omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
144}
145
146void omap2xxx_cm_set_dpll_disable_autoidle(void)
147{
148 _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
149}
150
151void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
152{
153 _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
154}
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]155
156/*
157 *
158 */
159
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]160/**
161 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
162 * @prcm_mod: PRCM module offset
163 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
164 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
165 *
166 * XXX document
167 */
168int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
169{
170 int ena = 0, i = 0;
171 u8 cm_idlest_reg;
172 u32 mask;
173
174 if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
175 return -EINVAL;
176
177 cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
178
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]179 mask = 1 << idlest_shift;
180
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]181 if (cpu_is_omap24xx())
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]182 ena = mask;
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]183 else if (cpu_is_omap34xx())
184 ena = 0;
185 else
186 BUG();
187
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]188 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
Paul Walmsley6f8b7ff2009-12-08 16:33:16 -0700[diff] [blame]189 MAX_MODULE_READY_TIME, i);
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]190
191 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
192}
193
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]194/*
195 * Context save/restore code - OMAP3 only
196 */
197#ifdef CONFIG_ARCH_OMAP3
198struct omap3_cm_regs {
199 u32 iva2_cm_clksel1;
200 u32 iva2_cm_clksel2;
201 u32 cm_sysconfig;
202 u32 sgx_cm_clksel;
203 u32 dss_cm_clksel;
204 u32 cam_cm_clksel;
205 u32 per_cm_clksel;
206 u32 emu_cm_clksel;
207 u32 emu_cm_clkstctrl;
208 u32 pll_cm_autoidle2;
209 u32 pll_cm_clksel4;
210 u32 pll_cm_clksel5;
211 u32 pll_cm_clken2;
212 u32 cm_polctrl;
213 u32 iva2_cm_fclken;
214 u32 iva2_cm_clken_pll;
215 u32 core_cm_fclken1;
216 u32 core_cm_fclken3;
217 u32 sgx_cm_fclken;
218 u32 wkup_cm_fclken;
219 u32 dss_cm_fclken;
220 u32 cam_cm_fclken;
221 u32 per_cm_fclken;
222 u32 usbhost_cm_fclken;
223 u32 core_cm_iclken1;
224 u32 core_cm_iclken2;
225 u32 core_cm_iclken3;
226 u32 sgx_cm_iclken;
227 u32 wkup_cm_iclken;
228 u32 dss_cm_iclken;
229 u32 cam_cm_iclken;
230 u32 per_cm_iclken;
231 u32 usbhost_cm_iclken;
232 u32 iva2_cm_autoidle2;
233 u32 mpu_cm_autoidle2;
234 u32 iva2_cm_clkstctrl;
235 u32 mpu_cm_clkstctrl;
236 u32 core_cm_clkstctrl;
237 u32 sgx_cm_clkstctrl;
238 u32 dss_cm_clkstctrl;
239 u32 cam_cm_clkstctrl;
240 u32 per_cm_clkstctrl;
241 u32 neon_cm_clkstctrl;
242 u32 usbhost_cm_clkstctrl;
243 u32 core_cm_autoidle1;
244 u32 core_cm_autoidle2;
245 u32 core_cm_autoidle3;
246 u32 wkup_cm_autoidle;
247 u32 dss_cm_autoidle;
248 u32 cam_cm_autoidle;
249 u32 per_cm_autoidle;
250 u32 usbhost_cm_autoidle;
251 u32 sgx_cm_sleepdep;
252 u32 dss_cm_sleepdep;
253 u32 cam_cm_sleepdep;
254 u32 per_cm_sleepdep;
255 u32 usbhost_cm_sleepdep;
256 u32 cm_clkout_ctrl;
257};
258
259static struct omap3_cm_regs cm_context;
260
261void omap3_cm_save_context(void)
262{
263 cm_context.iva2_cm_clksel1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]264 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]265 cm_context.iva2_cm_clksel2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]266 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]267 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
268 cm_context.sgx_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]269 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]270 cm_context.dss_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]271 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]272 cm_context.cam_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]273 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]274 cm_context.per_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]275 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]276 cm_context.emu_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]277 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]278 cm_context.emu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]279 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]280 cm_context.pll_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]281 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]282 cm_context.pll_cm_clksel4 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]283 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]284 cm_context.pll_cm_clksel5 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]285 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]286 cm_context.pll_cm_clken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]287 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]288 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
289 cm_context.iva2_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]290 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
291 cm_context.iva2_cm_clken_pll =
292 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]293 cm_context.core_cm_fclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]294 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]295 cm_context.core_cm_fclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]296 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]297 cm_context.sgx_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]298 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]299 cm_context.wkup_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]300 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]301 cm_context.dss_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]302 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]303 cm_context.cam_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]304 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]305 cm_context.per_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]306 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]307 cm_context.usbhost_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]308 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]309 cm_context.core_cm_iclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]310 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]311 cm_context.core_cm_iclken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]312 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]313 cm_context.core_cm_iclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]314 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]315 cm_context.sgx_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]316 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]317 cm_context.wkup_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]318 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]319 cm_context.dss_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]320 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]321 cm_context.cam_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]322 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]323 cm_context.per_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]324 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]325 cm_context.usbhost_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]326 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]327 cm_context.iva2_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]328 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]329 cm_context.mpu_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]330 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]331 cm_context.iva2_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]332 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]333 cm_context.mpu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]334 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]335 cm_context.core_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]336 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]337 cm_context.sgx_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]338 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]339 cm_context.dss_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]340 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]341 cm_context.cam_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]342 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]343 cm_context.per_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]344 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]345 cm_context.neon_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]346 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]347 cm_context.usbhost_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]348 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
349 OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]350 cm_context.core_cm_autoidle1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]351 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]352 cm_context.core_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]353 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]354 cm_context.core_cm_autoidle3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]355 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]356 cm_context.wkup_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]357 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]358 cm_context.dss_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]359 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]360 cm_context.cam_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]361 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]362 cm_context.per_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]363 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]364 cm_context.usbhost_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]365 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]366 cm_context.sgx_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]367 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
368 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]369 cm_context.dss_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]370 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]371 cm_context.cam_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]372 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]373 cm_context.per_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]374 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]375 cm_context.usbhost_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]376 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
377 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]378 cm_context.cm_clkout_ctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]379 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
380 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]381}
382
383void omap3_cm_restore_context(void)
384{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]385 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
386 CM_CLKSEL1);
387 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
388 CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]389 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]390 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
391 CM_CLKSEL);
392 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
393 CM_CLKSEL);
394 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
395 CM_CLKSEL);
396 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
397 CM_CLKSEL);
398 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
399 CM_CLKSEL1);
400 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
401 OMAP2_CM_CLKSTCTRL);
402 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
403 CM_AUTOIDLE2);
404 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
405 OMAP3430ES2_CM_CLKSEL4);
406 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
407 OMAP3430ES2_CM_CLKSEL5);
408 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
409 OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]410 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]411 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
412 CM_FCLKEN);
413 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
414 OMAP3430_CM_CLKEN_PLL);
415 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
416 CM_FCLKEN1);
417 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
418 OMAP3430ES2_CM_FCLKEN3);
419 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
420 CM_FCLKEN);
421 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
422 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
423 CM_FCLKEN);
424 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
425 CM_FCLKEN);
426 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
427 CM_FCLKEN);
428 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
429 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
430 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
431 CM_ICLKEN1);
432 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
433 CM_ICLKEN2);
434 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
435 CM_ICLKEN3);
436 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
437 CM_ICLKEN);
438 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
439 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
440 CM_ICLKEN);
441 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
442 CM_ICLKEN);
443 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
444 CM_ICLKEN);
445 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
446 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
447 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
448 CM_AUTOIDLE2);
449 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
450 CM_AUTOIDLE2);
451 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
452 OMAP2_CM_CLKSTCTRL);
453 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
454 OMAP2_CM_CLKSTCTRL);
455 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
456 OMAP2_CM_CLKSTCTRL);
457 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
458 OMAP2_CM_CLKSTCTRL);
459 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
460 OMAP2_CM_CLKSTCTRL);
461 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
462 OMAP2_CM_CLKSTCTRL);
463 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
464 OMAP2_CM_CLKSTCTRL);
465 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
466 OMAP2_CM_CLKSTCTRL);
467 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
468 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
469 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
470 CM_AUTOIDLE1);
471 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
472 CM_AUTOIDLE2);
473 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
474 CM_AUTOIDLE3);
475 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
476 CM_AUTOIDLE);
477 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
478 CM_AUTOIDLE);
479 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
480 CM_AUTOIDLE);
481 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
482 CM_AUTOIDLE);
483 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
484 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
485 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
486 OMAP3430_CM_SLEEPDEP);
487 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
488 OMAP3430_CM_SLEEPDEP);
489 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
490 OMAP3430_CM_SLEEPDEP);
491 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
492 OMAP3430_CM_SLEEPDEP);
493 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
494 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
495 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
496 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]497}
498#endif