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Christian Lamparter32ddf072008-08-08 21:17:37 +02001#ifndef P54COMMON_H
2#define P54COMMON_H
Michael Wueff1a592007-09-25 18:11:01 -07003
4/*
5 * Common code specific definitions for mac80211 Prism54 drivers
6 *
7 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
8 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
9 *
Christian Lamparter0fdd7c52008-10-15 03:55:37 +020010 * Based on:
11 * - the islsm (softmac prism54) driver, which is:
12 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
13 *
14 * - LMAC API interface header file for STLC4560 (lmac_longbow.h)
15 * Copyright (C) 2007 Conexant Systems, Inc.
Michael Wueff1a592007-09-25 18:11:01 -070016 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22struct bootrec {
23 __le32 code;
24 __le32 len;
Larry Finger1f1c0e32008-09-25 14:54:28 -050025 u32 data[10];
Michael Wueff1a592007-09-25 18:11:01 -070026} __attribute__((packed));
27
28struct bootrec_exp_if {
29 __le16 role;
30 __le16 if_id;
31 __le16 variant;
32 __le16 btm_compat;
33 __le16 top_compat;
34} __attribute__((packed));
35
Christian Lamparter4e416a62008-09-01 22:48:41 +020036struct bootrec_desc {
37 __le16 modes;
38 __le16 flags;
39 __le32 rx_start;
40 __le32 rx_end;
41 u8 headroom;
42 u8 tailroom;
43 u8 unimportant[6];
44 u8 rates[16];
Larry Finger2e20cc32008-10-09 17:38:52 -070045 u8 padding2[4];
46 __le16 rx_mtu;
Christian Lamparter4e416a62008-09-01 22:48:41 +020047} __attribute__((packed));
48
Michael Wueff1a592007-09-25 18:11:01 -070049#define BR_CODE_MIN 0x80000000
50#define BR_CODE_COMPONENT_ID 0x80000001
51#define BR_CODE_COMPONENT_VERSION 0x80000002
52#define BR_CODE_DEPENDENT_IF 0x80000003
53#define BR_CODE_EXPOSED_IF 0x80000004
54#define BR_CODE_DESCR 0x80000101
55#define BR_CODE_MAX 0x8FFFFFFF
56#define BR_CODE_END_OF_BRA 0xFF0000FF
57#define LEGACY_BR_CODE_END_OF_BRA 0xFFFFFFFF
58
Michael Wueff1a592007-09-25 18:11:01 -070059/* PDA defines are Copyright (C) 2005 Nokia Corporation (taken from islsm_pda.h) */
60
61struct pda_entry {
62 __le16 len; /* includes both code and data */
63 __le16 code;
64 u8 data[0];
65} __attribute__ ((packed));
66
67struct eeprom_pda_wrap {
Johannes Berg8c282932008-02-29 13:56:33 +010068 __le32 magic;
69 __le16 pad;
70 __le16 len;
71 __le32 arm_opcode;
Michael Wueff1a592007-09-25 18:11:01 -070072 u8 data[0];
73} __attribute__ ((packed));
74
75struct pda_iq_autocal_entry {
76 __le16 freq;
77 __le16 iq_param[4];
78} __attribute__ ((packed));
79
80struct pda_channel_output_limit {
81 __le16 freq;
82 u8 val_bpsk;
83 u8 val_qpsk;
84 u8 val_16qam;
85 u8 val_64qam;
86 u8 rate_set_mask;
87 u8 rate_set_size;
88} __attribute__ ((packed));
89
90struct pda_pa_curve_data_sample_rev0 {
91 u8 rf_power;
92 u8 pa_detector;
93 u8 pcv;
94} __attribute__ ((packed));
95
96struct pda_pa_curve_data_sample_rev1 {
97 u8 rf_power;
98 u8 pa_detector;
99 u8 data_barker;
100 u8 data_bpsk;
101 u8 data_qpsk;
102 u8 data_16qam;
103 u8 data_64qam;
Christian Lamparter154e3af2008-08-23 22:15:25 +0200104} __attribute__ ((packed));
105
106struct p54_pa_curve_data_sample {
107 u8 rf_power;
108 u8 pa_detector;
109 u8 data_barker;
110 u8 data_bpsk;
111 u8 data_qpsk;
112 u8 data_16qam;
113 u8 data_64qam;
Michael Wueff1a592007-09-25 18:11:01 -0700114 u8 padding;
115} __attribute__ ((packed));
116
117struct pda_pa_curve_data {
118 u8 cal_method_rev;
119 u8 channels;
120 u8 points_per_channel;
121 u8 padding;
122 u8 data[0];
123} __attribute__ ((packed));
124
125/*
126 * this defines the PDR codes used to build PDAs as defined in document
127 * number 553155. The current implementation mirrors version 1.1 of the
128 * document and lists only PDRs supported by the ARM platform.
129 */
130
131/* common and choice range (0x0000 - 0x0fff) */
132#define PDR_END 0x0000
133#define PDR_MANUFACTURING_PART_NUMBER 0x0001
134#define PDR_PDA_VERSION 0x0002
135#define PDR_NIC_SERIAL_NUMBER 0x0003
136
137#define PDR_MAC_ADDRESS 0x0101
138#define PDR_REGULATORY_DOMAIN_LIST 0x0103
139#define PDR_TEMPERATURE_TYPE 0x0107
140
141#define PDR_PRISM_PCI_IDENTIFIER 0x0402
142
143/* ARM range (0x1000 - 0x1fff) */
144#define PDR_COUNTRY_INFORMATION 0x1000
145#define PDR_INTERFACE_LIST 0x1001
146#define PDR_HARDWARE_PLATFORM_COMPONENT_ID 0x1002
147#define PDR_OEM_NAME 0x1003
148#define PDR_PRODUCT_NAME 0x1004
149#define PDR_UTF8_OEM_NAME 0x1005
150#define PDR_UTF8_PRODUCT_NAME 0x1006
151#define PDR_COUNTRY_LIST 0x1007
152#define PDR_DEFAULT_COUNTRY 0x1008
153
154#define PDR_ANTENNA_GAIN 0x1100
155
156#define PDR_PRISM_INDIGO_PA_CALIBRATION_DATA 0x1901
157#define PDR_RSSI_LINEAR_APPROXIMATION 0x1902
158#define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS 0x1903
159#define PDR_PRISM_PA_CAL_CURVE_DATA 0x1904
160#define PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND 0x1905
161#define PDR_PRISM_ZIF_TX_IQ_CALIBRATION 0x1906
162#define PDR_REGULATORY_POWER_LIMITS 0x1907
163#define PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED 0x1908
164#define PDR_RADIATED_TRANSMISSION_CORRECTION 0x1909
165#define PDR_PRISM_TX_IQ_CALIBRATION 0x190a
166
167/* reserved range (0x2000 - 0x7fff) */
168
169/* customer range (0x8000 - 0xffff) */
170#define PDR_BASEBAND_REGISTERS 0x8000
171#define PDR_PER_CHANNEL_BASEBAND_REGISTERS 0x8001
172
173/* stored in skb->cb */
174struct memrecord {
175 u32 start_addr;
176 u32 end_addr;
Michael Wueff1a592007-09-25 18:11:01 -0700177};
178
179struct p54_eeprom_lm86 {
180 __le16 offset;
181 __le16 len;
182 u8 data[0];
183} __attribute__ ((packed));
184
185struct p54_rx_hdr {
186 __le16 magic;
187 __le16 len;
188 __le16 freq;
189 u8 antenna;
190 u8 rate;
191 u8 rssi;
192 u8 quality;
193 u16 unknown2;
Christian Lampartera0db6632008-09-06 02:56:04 +0200194 __le32 tsf32;
195 __le32 unalloc0;
Christian Lamparter19c19d52008-09-03 22:25:25 +0200196 u8 align[0];
Michael Wueff1a592007-09-25 18:11:01 -0700197} __attribute__ ((packed));
198
199struct p54_frame_sent_hdr {
200 u8 status;
201 u8 retries;
202 __le16 ack_rssi;
203 __le16 seq;
204 u16 rate;
205} __attribute__ ((packed));
206
207struct p54_tx_control_allocdata {
208 u8 rateset[8];
Christian Lamparteraaa15532008-08-09 19:20:47 -0500209 u8 unalloc0[2];
210 u8 key_type;
211 u8 key_len;
212 u8 key[16];
213 u8 hw_queue;
214 u8 unalloc1[9];
215 u8 tx_antenna;
Michael Wueff1a592007-09-25 18:11:01 -0700216 u8 output_power;
Christian Lamparteraaa15532008-08-09 19:20:47 -0500217 u8 cts_rate;
218 u8 unalloc2[3];
Michael Wueff1a592007-09-25 18:11:01 -0700219 u8 align[0];
220} __attribute__ ((packed));
221
222struct p54_tx_control_filter {
223 __le16 filter_type;
Christian Lampartere0a58ea2008-09-03 22:25:20 +0200224 u8 mac_addr[ETH_ALEN];
225 u8 bssid[ETH_ALEN];
226 u8 rx_antenna;
227 u8 rx_align;
Christian Lamparter19c19d52008-09-03 22:25:25 +0200228 union {
229 struct {
230 __le32 basic_rate_mask;
231 u8 rts_rates[8];
232 __le32 rx_addr;
233 __le16 max_rx;
234 __le16 rxhw;
235 __le16 wakeup_timer;
236 __le16 unalloc0;
237 } v1 __attribute__ ((packed));
238 struct {
239 __le32 rx_addr;
240 __le16 max_rx;
241 __le16 rxhw;
242 __le16 timer;
243 __le16 unalloc0;
244 __le32 unalloc1;
245 } v2 __attribute__ ((packed));
246 } __attribute__ ((packed));
Michael Wueff1a592007-09-25 18:11:01 -0700247} __attribute__ ((packed));
248
Christian Lamparter19c19d52008-09-03 22:25:25 +0200249#define P54_TX_CONTROL_FILTER_V1_LEN (sizeof(struct p54_tx_control_filter))
250#define P54_TX_CONTROL_FILTER_V2_LEN (sizeof(struct p54_tx_control_filter)-8)
251
Michael Wueff1a592007-09-25 18:11:01 -0700252struct p54_tx_control_channel {
Christian Lamparter154e3af2008-08-23 22:15:25 +0200253 __le16 flags;
254 __le16 dwell;
Michael Wueff1a592007-09-25 18:11:01 -0700255 u8 padding1[20];
256 struct pda_iq_autocal_entry iq_autocal;
257 u8 pa_points_per_curve;
258 u8 val_barker;
259 u8 val_bpsk;
260 u8 val_qpsk;
261 u8 val_16qam;
262 u8 val_64qam;
Christian Lamparter19c19d52008-09-03 22:25:25 +0200263 struct p54_pa_curve_data_sample curve_data[8];
Christian Lamparter154e3af2008-08-23 22:15:25 +0200264 u8 dup_bpsk;
265 u8 dup_qpsk;
266 u8 dup_16qam;
267 u8 dup_64qam;
Christian Lamparter19c19d52008-09-03 22:25:25 +0200268 union {
269 struct {
270 __le16 rssical_mul;
271 __le16 rssical_add;
272 } v1 __attribute__ ((packed));
273
274 struct {
275 __le32 basic_rate_mask;
276 u8 rts_rates[8];
277 __le16 rssical_mul;
278 __le16 rssical_add;
279 } v2 __attribute__ ((packed));
280 } __attribute__ ((packed));
Michael Wueff1a592007-09-25 18:11:01 -0700281} __attribute__ ((packed));
282
Christian Lamparter19c19d52008-09-03 22:25:25 +0200283#define P54_TX_CONTROL_CHANNEL_V1_LEN (sizeof(struct p54_tx_control_channel)-12)
284#define P54_TX_CONTROL_CHANNEL_V2_LEN (sizeof(struct p54_tx_control_channel))
285
Michael Wueff1a592007-09-25 18:11:01 -0700286struct p54_tx_control_led {
287 __le16 mode;
288 __le16 led_temporary;
289 __le16 led_permanent;
290 __le16 duration;
291} __attribute__ ((packed));
292
Christian Lamparter0fdd7c52008-10-15 03:55:37 +0200293struct p54_edcf {
294 u8 flags;
Michael Wueff1a592007-09-25 18:11:01 -0700295 u8 slottime;
Christian Lamparter0fdd7c52008-10-15 03:55:37 +0200296 u8 sifs;
297 u8 eofpad;
298 struct p54_edcf_queue_param queue[8];
299 u8 mapping[4];
Michael Wueff1a592007-09-25 18:11:01 -0700300 __le16 frameburst;
Christian Lamparter0fdd7c52008-10-15 03:55:37 +0200301 __le16 round_trip_delay;
Michael Wueff1a592007-09-25 18:11:01 -0700302} __attribute__ ((packed));
303
Christian Lampartercc6de662008-09-06 02:56:23 +0200304struct p54_statistics {
305 __le32 rx_success;
306 __le32 rx_bad_fcs;
307 __le32 rx_abort;
308 __le32 rx_abort_phy;
309 __le32 rts_success;
310 __le32 rts_fail;
311 __le32 tsf32;
312 __le32 airtime;
313 __le32 noise;
314 __le32 unkn[10]; /* CCE / CCA / RADAR */
315} __attribute__ ((packed));
316
Christian Lamparter1b997532008-09-06 14:25:58 +0200317struct p54_tx_control_xbow_synth {
318 __le16 magic1;
319 __le16 magic2;
320 __le16 freq;
321 u32 padding[5];
322} __attribute__ ((packed));
323
Christian Lamparter32ddf072008-08-08 21:17:37 +0200324#endif /* P54COMMON_H */