| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * Definitions for Motorola SPS Sandpoint Test Platform |
| 3 | * |
| 4 | * Author: Mark A. Greer |
| 5 | * mgreer@mvista.com |
| 6 | * |
| 7 | * 2000-2003 (c) MontaVista, Software, Inc. This file is licensed under |
| 8 | * the terms of the GNU General Public License version 2. This program |
| 9 | * is licensed "as is" without any warranty of any kind, whether express |
| 10 | * or implied. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Sandpoint uses the CHRP map (Map B). |
| 15 | */ |
| 16 | |
| 17 | #ifndef __PPC_PLATFORMS_SANDPOINT_H |
| 18 | #define __PPC_PLATFORMS_SANDPOINT_H |
| 19 | |
| 20 | #include <asm/ppcboot.h> |
| 21 | |
| 22 | #if 0 |
| 23 | /* The Sandpoint X3 allows the IDE interrupt to be directly connected |
| 24 | * from the Windbond (PCI INTC or INTD) to the serial EPIC. Someday |
| 25 | * we should try this, but it was easier to use the existing 83c553 |
| 26 | * initialization than change it to route the different interrupts :-). |
| 27 | * -- Dan |
| 28 | */ |
| 29 | #define SANDPOINT_IDE_INT0 23 /* EPIC 7 */ |
| 30 | #define SANDPOINT_IDE_INT1 24 /* EPIC 8 */ |
| 31 | #else |
| 32 | #define SANDPOINT_IDE_INT0 14 /* 8259 Test */ |
| 33 | #define SANDPOINT_IDE_INT1 15 /* 8259 Test */ |
| 34 | #endif |
| 35 | |
| 36 | /* |
| 37 | * The sandpoint boards have processor modules that either have an 8240 or |
| 38 | * an MPC107 host bridge on them. These bridges have an IDSEL line that allows |
| 39 | * them to respond to PCI transactions as if they were a normal PCI devices. |
| 40 | * However, the processor on the processor side of the bridge can not reach |
| 41 | * out onto the PCI bus and then select the bridge or bad things will happen |
| 42 | * (documented in the 8240 and 107 manuals). |
| 43 | * Because of this, we always skip the bridge PCI device when accessing the |
| 44 | * PCI bus. The PCI slot that the bridge occupies is defined by the macro |
| 45 | * below. |
| 46 | */ |
| 47 | #define SANDPOINT_HOST_BRIDGE_IDSEL 12 |
| 48 | |
| 49 | /* |
| 50 | * Serial defines. |
| 51 | */ |
| 52 | #define SANDPOINT_SERIAL_0 0xfe0003f8 |
| 53 | #define SANDPOINT_SERIAL_1 0xfe0002f8 |
| 54 | |
| 55 | #define RS_TABLE_SIZE 2 |
| 56 | |
| 57 | /* Rate for the 1.8432 Mhz clock for the onboard serial chip */ |
| 58 | #define BASE_BAUD ( 1843200 / 16 ) |
| 59 | #define UART_CLK 1843200 |
| 60 | |
| 61 | #ifdef CONFIG_SERIAL_DETECT_IRQ |
| 62 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ) |
| 63 | #else |
| 64 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF) |
| 65 | #endif |
| 66 | |
| 67 | #define STD_SERIAL_PORT_DFNS \ |
| 68 | { 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \ |
| 69 | iomem_base: (u8 *)SANDPOINT_SERIAL_0, \ |
| 70 | io_type: SERIAL_IO_MEM }, \ |
| 71 | { 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \ |
| 72 | iomem_base: (u8 *)SANDPOINT_SERIAL_1, \ |
| 73 | io_type: SERIAL_IO_MEM }, |
| 74 | |
| 75 | #define SERIAL_PORT_DFNS \ |
| 76 | STD_SERIAL_PORT_DFNS |
| 77 | |
| 78 | #endif /* __PPC_PLATFORMS_SANDPOINT_H */ |