Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / 1335e873690d168a071fbd32324e23072ba617ca / . / arch / arm / boot / dts / msm8974.dtsi
blob: 12f46a33ad7637a30b45efc694d3ed8ce81d85bc [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]16/include/ "msm-gdsc.dtsi"
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame^]17/include/ "msm8974-gpu.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]18
19/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]20 model = "Qualcomm MSM 8974";
21 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]22 interrupt-parent = <&intc>;
23
24 intc: interrupt-controller@F9000000 {
25 compatible = "qcom,msm-qgic2";
26 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]27 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]28 reg = <0xF9000000 0x1000>,
29 <0xF9002000 0x1000>;
30 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]31
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]32 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]33 compatible = "qcom,msm-gpio";
34 interrupt-controller;
35 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]36 reg = <0xfd510000 0x4000>;
37 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]38 };
39
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]40 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]41 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]42 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]43 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]44 };
45
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]46 qcom,vidc@fdc00000 {
47 compatible = "qcom,msm-vidc";
48 reg = <0xfdc00000 0xff000>;
49 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -0700[diff] [blame]50 vidc-cp-map = <0x1000000 0x40000000>;
51 vidc-ns-map = <0x40000000 0x40000000>;
Vinay Kalia40680aa2012-07-23 12:45:39 -0700[diff] [blame]52 load-freq-tbl = <979200 410000000>,
53 <560145 266670000>,
54 <421161 200000000>,
55 <243000 133330000>,
56 <108000 100000000>,
57 <36000 50000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]58 };
59
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]60 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]61 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]62 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]63 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]64 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]65
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]66 serial@f995e000 {
67 compatible = "qcom,msm-lsuart-v14";
68 reg = <0xf995e000 0x1000>;
69 interrupts = <0 114 0>;
70 };
71
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]72 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]73 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]74 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]75 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]76 HSUSB_VDDCX-supply = <&pm8841_s2>;
77 HSUSB_1p8-supply = <&pm8941_l6>;
78 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]79
80 qcom,hsusb-otg-phy-type = <2>;
81 qcom,hsusb-otg-mode = <1>;
82 qcom,hsusb-otg-otg-control = <1>;
83 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]84
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]85 qcom,sdcc@f9824000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]86 cell-index = <1>; /* SDC1 eMMC slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]87 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]88 reg = <0xf9824000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]89 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]90 interrupts = <0 123 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]91 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]92 vdd-supply = <&pm8941_l20>;
93 vdd-io-supply = <&pm8941_s3>;
94
95 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
96 qcom,sdcc-vdd-current_level = <800 500000>;
97
98 qcom,sdcc-vdd-io-always_on;
99 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
100 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]101
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]102 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
103 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
104 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
105 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
106
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]107 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
108 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]109 qcom,sdcc-bus-width = <8>;
110 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]111 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]112 };
113
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]114 qcom,sdcc@f98a4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]115 cell-index = <2>; /* SDC2 SD card slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]116 compatible = "qcom,msm-sdcc";
117 reg = <0xf98a4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]118 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]119 interrupts = <0 125 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]120 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]121 vdd-supply = <&pm8941_l21>;
122 vdd-io-supply = <&pm8941_l13>;
123
124 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
125 qcom,sdcc-vdd-current_level = <9000 800000>;
126
127 qcom,sdcc-vdd-io-always_on;
128 qcom,sdcc-vdd-io-lpm_sup;
129 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
130 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]131
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]132 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
133 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
134 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
135 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
136
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]137 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
138 qcom,sdcc-sup-voltages = <2950 2950>;
139 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]140 qcom,sdcc-xpc;
141 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
142 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]143 };
144
145 qcom,sdcc@f9864000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]146 cell-index = <3>; /* SDC3 SDIO slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]147 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]148 reg = <0xf9864000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]149 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]150 interrupts = <0 127 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]151 interrupt-names = "core_irq";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]152
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]153 gpios = <&msmgpio 40 0>, /* CLK */
154 <&msmgpio 39 0>, /* CMD */
155 <&msmgpio 38 0>, /* DATA0 */
156 <&msmgpio 37 0>, /* DATA1 */
157 <&msmgpio 36 0>, /* DATA2 */
158 <&msmgpio 35 0>; /* DATA3 */
159 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
160
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]161 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
162 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]163 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]164 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]165 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]166 };
167
168 qcom,sdcc@f98e4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]169 cell-index = <4>; /* SDC4 SDIO slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]170 compatible = "qcom,msm-sdcc";
171 reg = <0xf98e4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]172 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]173 interrupts = <0 129 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]174 interrupt-names = "core_irq";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]175
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]176 gpios = <&msmgpio 93 0>, /* CLK */
177 <&msmgpio 91 0>, /* CMD */
178 <&msmgpio 96 0>, /* DATA0 */
179 <&msmgpio 95 0>, /* DATA1 */
180 <&msmgpio 94 0>, /* DATA2 */
181 <&msmgpio 92 0>; /* DATA3 */
182 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
183
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]184 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
185 qcom,sdcc-sup-voltages = <1800 1800>;
186 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]187 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]188 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]189 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]190
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]191 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]192 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]193 reg = <0xf9984000 0x15000>,
194 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]195 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]196
197 qcom,bam-dma-res-pipes = <6>;
198 };
199
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]200
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]201 spi@f9924000 {
202 compatible = "qcom,spi-qup-v2";
203 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]204 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]205 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]206 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]207
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]208 slim@fe12f000 {
209 cell-index = <1>;
210 compatible = "qcom,slim-msm";
211 reg = <0xfe12f000 0x35000>,
212 <0xfe104000 0x20000>;
213 reg-names = "slimbus_physical", "slimbus_bam_physical";
214 interrupts = <0 163 0 0 164 0>;
215 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
216 qcom,min-clk-gear = <10>;
217 };
218
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]219 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]220 cell-index = <0>;
221 compatible = "qcom,spmi-pmic-arb";
222 reg = <0xfc4cf000 0x1000>,
223 <0Xfc4cb000 0x1000>;
224 /* 190,ee0_krait_hlos_spmi_periph_irq */
225 /* 187,channel_0_krait_hlos_trans_done_irq */
226 interrupts = <0 190 0 0 187 0>;
227 qcom,pmic-arb-ee = <0>;
228 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]229 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
230 <0x13100001>, /* PM8941_LDO2 */
231 <0x13200002>, /* PM8941_LDO3 */
232 <0x13300003>, /* PM8941_LDO4 */
233 <0x13400004>, /* PM8941_LDO5 */
234 <0x13500005>, /* PM8941_LDO6 */
235 <0x13600006>, /* PM8941_LDO7 */
236 <0x13700007>, /* PM8941_LDO8 */
237 <0x13800008>, /* PM8941_LDO9 */
238 <0x13900009>, /* PM8941_LDO10 */
239 <0x13a0000a>, /* PM8941_LDO11 */
240 <0x13b0000b>, /* PM8941_LDO12 */
241 <0x13c0000c>, /* PM8941_LDO13 */
242 <0x13d0000d>, /* PM8941_LDO14 */
243 <0x13e0000e>, /* PM8941_LDO15 */
244 <0x13f0000f>, /* PM8941_LDO16 */
245 <0x14000010>, /* PM8941_LDO17 */
246 <0x14100011>, /* PM8941_LDO18 */
247 <0x14200012>, /* PM8941_LDO19 */
248 <0x14300013>, /* PM8941_LDO20 */
249 <0x14400014>, /* PM8941_LDO21 */
250 <0x14500015>, /* PM8941_LDO22 */
251 <0x14600016>, /* PM8941_LDO23 */
252 <0x14700017>, /* PM8941_LDO24 */
253 <0x14800018>, /* PM8941_LDO25 */
254 <0x14900019>, /* PM8941_LDO26 */
255 <0x0c00001a>, /* PM8941_GPIO1 */
256 <0x0c10001b>, /* PM8941_GPIO2 */
257 <0x0c20001c>, /* PM8941_GPIO3 */
258 <0x0c30001d>, /* PM8941_GPIO4 */
259 <0x0c40001e>, /* PM8941_GPIO5 */
260 <0x0c50001f>, /* PM8941_GPIO6 */
261 <0x0c600020>, /* PM8941_GPIO7 */
262 <0x0c700021>, /* PM8941_GPIO8 */
263 <0x0c800022>, /* PM8941_GPIO9 */
264 <0x0c900023>, /* PM8941_GPIO10 */
265 <0x0ca00024>, /* PM8941_GPIO11 */
266 <0x0cb00025>, /* PM8941_GPIO12 */
267 <0x0cc00026>, /* PM8941_GPIO13 */
268 <0x0cd00027>, /* PM8941_GPIO14 */
269 <0x0ce00028>, /* PM8941_GPIO15 */
270 <0x0cf00029>, /* PM8941_GPIO16 */
271 <0x0d00002a>, /* PM8941_GPIO17 */
272 <0x0d10002b>, /* PM8941_GPIO18 */
273 <0x0d20002c>, /* PM8941_GPIO19 */
274 <0x0d30002d>, /* PM8941_GPIO20 */
275 <0x0d40002e>, /* PM8941_GPIO21 */
276 <0x0d50002f>, /* PM8941_GPIO22 */
277 <0x0d600030>, /* PM8941_GPIO23 */
278 <0x0d700031>, /* PM8941_GPIO24 */
279 <0x0d800032>, /* PM8941_GPIO25 */
280 <0x0d900033>, /* PM8941_GPIO26 */
281 <0x0da00034>, /* PM8941_GPIO27 */
282 <0x0db00035>, /* PM8941_GPIO28 */
283 <0x0dc00036>, /* PM8941_GPIO29 */
284 <0x0dd00037>, /* PM8941_GPIO30 */
285 <0x0de00038>, /* PM8941_GPIO31 */
286 <0x0df00039>, /* PM8941_GPIO32 */
287 <0x0e00003a>, /* PM8941_GPIO33 */
288 <0x0e10003b>, /* PM8941_GPIO34 */
289 <0x0e20003c>, /* PM8941_GPIO35 */
290 <0x0e30003d>, /* PM8941_GPIO36 */
291 <0x0280003e>, /* COINCELL */
292 <0x0100003f>, /* SMBC_OVP */
293 <0x01100040>, /* SMBC_CHG */
294 <0x01200041>, /* SMBC_BIF */
295 <0x00500042>, /* INTERRUPT */
296 <0x00100043>, /* PM8941_0 */
297 <0x20100044>, /* PM8841_0 */
298 <0x10100045>, /* PM8941_1 */
299 <0x30100046>, /* PM8841_1 */
300 <0x00800047>, /* PON0 */
301 <0x20800048>, /* PON1 */
302 <0x11000049>, /* PM8941_SMPS1 */
303 <0x1110004a>, /* PM8941_SMPS2 */
304 <0x1120004b>, /* PM8941_SMPS3 */
305 <0x3100004c>, /* PM8841_SMPS1 */
306 <0x3110004d>, /* PM8841_SMPS2 */
307 <0x3120004e>, /* PM8841_SMPS3 */
308 <0x3130004f>, /* PM8841_SMPS4 */
309 <0x31400050>, /* PM8841_SMPS5 */
310 <0x31500051>, /* PM8841_SMPS6 */
311 <0x31600052>, /* PM8841_SMPS7 */
312 <0x31700053>, /* PM8841_SMPS8 */
313 <0x05000054>, /* SHARED_XO */
314 <0x05100055>, /* BB_CLK1 */
315 <0x05200056>, /* BB_CLK2 */
316 <0x05900057>, /* SLEEP_CLK */
317 <0x07000058>, /* PBS_CORE */
318 <0x07100059>, /* PBS_CLIENT1 */
319 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]320 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]321
322 i2c@f9966000 {
323 cell-index = <0>;
324 compatible = "qcom,i2c-qup";
325 reg = <0Xf9966000 0x1000>;
326 reg-names = "qup_phys_addr";
327 interrupts = <0 104 0>;
328 interrupt-names = "qup_err_intr";
329 qcom,i2c-bus-freq = <100000>;
330 qcom,i2c-src-freq = <24000000>;
331 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]332
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]333 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]334 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]335 krait0-supply = <&krait0_vreg>;
336 krait1-supply = <&krait1_vreg>;
337 krait2-supply = <&krait2_vreg>;
338 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]339 krait0_mem-supply = <&pm8841_s1_ao>;
340 krait1_mem-supply = <&pm8841_s1_ao>;
341 krait2_mem-supply = <&pm8841_s1_ao>;
342 krait3_mem-supply = <&pm8841_s1_ao>;
343 krait0_dig-supply = <&pm8841_s2_corner_ao>;
344 krait1_dig-supply = <&pm8841_s2_corner_ao>;
345 krait2_dig-supply = <&pm8841_s2_corner_ao>;
346 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]347 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
348 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
349 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
350 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
351 l2_hfpll_a-supply = <&pm8941_s2_ao>;
352 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
353 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
354 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
355 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
356 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]357 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]358
359 qcom,ssusb@F9200000 {
360 compatible = "qcom,dwc-usb3-msm";
Manu Gautam8c642812012-06-07 10:35:10 +0530[diff] [blame]361 reg = <0xF9200000 0xFA000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]362 interrupts = <0 131 0 0 179 0>;
363 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]364 SSUSB_VDDCX-supply = <&pm8841_s2>;
365 SSUSB_1p8-supply = <&pm8941_l6>;
366 HSUSB_VDDCX-supply = <&pm8841_s2>;
367 HSUSB_1p8-supply = <&pm8941_l6>;
368 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]369 qcom,dwc-usb3-msm-dbm-eps = <4>;
370 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]371
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]372 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
373 parent-supply = <&pm8841_s4>;
374 };
375
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]376 qcom,lpass@fe200000 {
377 compatible = "qcom,pil-q6v5-lpass";
378 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]379 <0xfd485100 0x00010>;
380
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]381 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]382 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]383
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]384 qcom,msm-pcm {
385 compatible = "qcom,msm-pcm-dsp";
386 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]387
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]388 qcom,msm-pcm-routing {
389 compatible = "qcom,msm-pcm-routing";
390 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]391
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]392 qcom,msm-pcm-lpa {
393 compatible = "qcom,msm-pcm-lpa";
394 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]395
Harmandeep Singha3453a72012-07-03 12:31:09 -0700[diff] [blame]396 qcom,msm-compr-dsp {
397 compatible = "qcom,msm-compr-dsp";
398 };
399
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]400 qcom,msm-voip-dsp {
401 compatible = "qcom,msm-voip-dsp";
402 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]403
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]404 qcom,msm-stub-codec {
405 compatible = "qcom,msm-stub-codec";
406 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]407
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]408 qcom,msm-dai-fe {
409 compatible = "qcom,msm-dai-fe";
410 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]411
Joonwoo Park6572ac52012-07-10 17:17:00 -0700[diff] [blame]412 qcom,msm-dai-q6 {
413 compatible = "qcom,msm-dai-q6";
414 qcom,msm-dai-q6-sb-0-rx {
415 compatible = "qcom,msm-dai-q6-dev";
416 qcom,msm-dai-q6-dev-id = <16384>;
417 };
418
419 qcom,msm-dai-q6-sb-0-tx {
420 compatible = "qcom,msm-dai-q6-dev";
421 qcom,msm-dai-q6-dev-id = <16385>;
422 };
423 };
424
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]425 qcom,msm-auxpcm {
426 compatible = "qcom,msm-auxpcm-resource";
427 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
428 qcom,msm-cpudai-auxpcm-mode = <0>;
429 qcom,msm-cpudai-auxpcm-sync = <1>;
430 qcom,msm-cpudai-auxpcm-frame = <5>;
431 qcom,msm-cpudai-auxpcm-quant = <2>;
432 qcom,msm-cpudai-auxpcm-slot = <1>;
433 qcom,msm-cpudai-auxpcm-data = <0>;
434 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]435
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]436 qcom,msm-auxpcm-rx {
437 qcom,msm-auxpcm-dev-id = <4106>;
438 compatible = "qcom,msm-auxpcm-dev";
439 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]440
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]441 qcom,msm-auxpcm-tx {
442 qcom,msm-auxpcm-dev-id = <4107>;
443 compatible = "qcom,msm-auxpcm-dev";
444 };
445 };
446
447 qcom,msm-pcm-hostless {
448 compatible = "qcom,msm-pcm-hostless";
449 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]450
Phani Kumar Uppalapati8b3a1bb2012-06-26 19:56:58 -0700[diff] [blame]451 qcom,msm-ocmem-audio {
452 compatible = "qcom,msm-ocmem-audio";
453 qcom,msm-ocmem-audio-src-id = <11>;
454 qcom,msm-ocmem-audio-dst-id = <604>;
455 qcom,msm-ocmem-audio-ab = <32505856>;
456 qcom,msm-ocmem-audio-ib = <32505856>;
457 };
458
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]459 qcom,mss@fc880000 {
460 compatible = "qcom,pil-q6v5-mss";
461 reg = <0xfc880000 0x100>,
462 <0xfd485000 0x400>,
463 <0xfc820000 0x020>,
464 <0xfc401680 0x004>;
465 vdd_mss-supply = <&pm8841_s3>;
466
467 qcom,firmware-name = "mba";
468 qcom,pil-self-auth = <1>;
469 };
470
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]471 qcom,mba@fc820000 {
472 compatible = "qcom,pil-mba";
473 reg = <0xfc820000 0x0020>,
474 <0x0d1fc000 0x4000>;
475
476 qcom,firmware-name = "modem";
477 qcom,depends-on = "mba";
478 };
479
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]480 qcom,pronto@fb21b000 {
481 compatible = "qcom,pil-pronto";
482 reg = <0xfb21b000 0x3000>,
483 <0xfc401700 0x4>,
484 <0xfd485300 0xc>;
485 vdd_pronto_pll-supply = <&pm8941_l12>;
486
487 qcom,firmware-name = "wcnss";
488 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]489
490 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]491 compatible = "qcom,msm-ocmem";
492 reg = <0xfdd00000 0x2000>,
493 <0xfdd02000 0x2000>,
494 <0xfe039000 0x400>,
495 <0xfec00000 0x180000>;
496 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
497 interrupts = <0 76 0 0 77 0>;
498 interrupt-names = "ocmem_irq", "dm_irq";
499 qcom,ocmem-num-regions = <0x3>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges = <0x0 0xfec00000 0x180000>;
503
504 partition@0 {
505 reg = <0x0 0x100000>;
506 qcom,ocmem-part-name = "graphics";
507 qcom,ocmem-part-min = <0x80000>;
508 };
509
510 partition@80000 {
511 reg = <0x80000 0xA0000>;
512 qcom,ocmem-part-name = "lp_audio";
513 qcom,ocmem-part-min = <0xA0000>;
514 };
515
516 partition@E0000 {
517 reg = <0x120000 0x20000>;
Naveen Ramarajcc4ec152012-05-14 09:55:29 -0700[diff] [blame]518 qcom,ocmem-part-name = "other_os";
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]519 qcom,ocmem-part-min = <0x20000>;
520 };
521
522 partition@100000 {
523 reg = <0x100000 0x80000>;
524 qcom,ocmem-part-name = "video";
525 qcom,ocmem-part-min = <0x55000>;
526 };
527
528 partition@140000 {
529 reg = <0x140000 0x40000>;
530 qcom,ocmem-part-name = "sensors";
531 qcom,ocmem-part-min = <0x40000>;
532 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]533 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]534
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]535 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]536 compatible = "qcom,rpm-smd";
537 rpm-channel-name = "rpm_requests";
538 rpm-channel-type = <15>; /* SMD_APPS_RPM */
539 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]540
541 qcom,msm-rng@f9bff000 {
542 compatible = "qcom,msm-rng";
543 reg = <0xf9bff000 0x200>;
544 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]545
546 qcom,qseecom@fe806000 {
547 compatible = "qcom,qseecom";
548 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]549
550 qcom,mdss_mdp@fd900000 {
551 cell-index = <0>;
552 compatible = "qcom,mdss_mdp";
553 reg = <0xfd900000 0x22100>;
554 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]555 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]556 };
557
558 qcom,mdss_wb_panel {
559 cell-index = <1>;
560 compatible = "qcom,mdss_wb";
561 qcom,mdss_pan_res = <640 480>;
562 qcom,mdss_pan_bpp = <24>;
563 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]564
565 qcom,wdt@f9017000 {
566 compatible = "qcom,msm-watchdog";
567 reg = <0xf9017000 0x1000>;
568 interrupts = <0 3 0 0 4 0>;
569 qcom,bark-time = <11000>;
570 qcom,pet-time = <10000>;
571 qcom,ipi-ping = <1>;
572 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]573
574 qcom,tz-log@fe805720 {
575 compatible = "qcom,tz-log";
576 reg = <0xfe805720 0x1000>;
577 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]578
579 qcom,venus@fdce0000 {
580 compatible = "qcom,pil-venus";
581 reg = <0xfdce0000 0x4000>,
582 <0xfdc80208 0x8>;
583 vdd-supply = <&gdsc_venus>;
584
585 qcom,firmware-name = "venus";
586 qcom,firmware-min-paddr = <0xF500000>;
587 qcom,firmware-max-paddr = <0xFA00000>;
588 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]589
Stepan Moskovchenkoc79a7382012-07-19 17:24:32 -0700[diff] [blame]590 qcom,cache_erp {
591 compatible = "qcom,cache_erp";
592 interrupts = <1 9 0>, <0 2 0>;
593 interrupt-names = "l1_irq", "l2_irq";
594 };
595
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]596 tsens@fc4a8000 {
597 compatible = "qcom,msm-tsens";
598 reg = <0xfc4a8000 0x2000>,
599 <0xfc4b80d0 0x5>;
600 reg-names = "tsens_physical", "tsens_eeprom_physical";
601 interrupts = <0 184 0>;
602 qcom,sensors = <11>;
Siddartha Mohanadoss205bce62012-07-27 17:17:18 -0700[diff] [blame]603 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
604 3200 3200>;
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]605 };
Laura Abbottf7e44042012-06-22 12:50:32 -0700[diff] [blame]606
607 qcom,msm-rtb {
608 compatible = "qcom,msm-rtb";
609 qcom,memory-reservation-type = "EBI1";
610 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
611 };
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]612
613 qcom,qcedev@fd440000 {
614 compatible = "qcom,qcedev";
615 reg = <0xfd440000 0x20000>,
616 <0xfd444000 0x8000>;
617 interrupts = <0 235 0>;
618 qcom,bam-pipes = <0>;
619 };
620
621 qcom,qcrypto@fd444000 {
622 compatible = "qcom,qcrypto";
623 reg = <0xfd440000 0x20000>,
624 <0xfd444000 0x8000>;
625 interrupts = <0 235 0>;
626 qcom,bam-pipes = <1>;
627 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]628};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]629
630/include/ "msm-pm8x41-rpm-regulator.dtsi"
631/include/ "msm-pm8841.dtsi"
632/include/ "msm-pm8941.dtsi"
633/include/ "msm8974-regulator.dtsi"
634/include/ "msm8974-gpio.dtsi"