blob: e1e19598c648cb07cedd22f007e6beee2340d188 [file] [log] [blame]
Marc Dietrich65b935a2011-03-07 21:01:31 +01001/*
2 * arch/arm/mach-tegra/board-paz00.c
3 *
4 * Copyright (C) 2011 Marc Dietrich <marvin24@gmx.de>
5 *
6 * Based on board-harmony.c
7 * Copyright (C) 2010 Google, Inc.
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/serial_8250.h>
24#include <linux/clk.h>
25#include <linux/dma-mapping.h>
26#include <linux/pda_power.h>
27#include <linux/io.h>
Marc Dietrichdda9cd22011-05-19 14:08:26 +020028#include <linux/i2c.h>
29#include <linux/i2c-tegra.h>
Marc Dietrich13db7a72011-05-19 14:08:27 +020030#include <linux/platform_data/tegra_usb.h>
Marc Dietrich65b935a2011-03-07 21:01:31 +010031
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35#include <asm/setup.h>
36
37#include <mach/iomap.h>
38#include <mach/irqs.h>
39#include <mach/sdhci.h>
Marc Dietrich13db7a72011-05-19 14:08:27 +020040#include <mach/usb_phy.h>
41#include <mach/gpio.h>
Marc Dietrich65b935a2011-03-07 21:01:31 +010042
43#include "board.h"
44#include "board-paz00.h"
45#include "clock.h"
46#include "devices.h"
47#include "gpio-names.h"
48
49static struct plat_serial8250_port debug_uart_platform_data[] = {
50 {
51 .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
52 .mapbase = TEGRA_UARTD_BASE,
53 .irq = INT_UARTD,
54 .flags = UPF_BOOT_AUTOCONF,
55 .iotype = UPIO_MEM,
56 .regshift = 2,
57 .uartclk = 216000000,
58 }, {
59 .flags = 0
60 }
61};
62
63static struct platform_device debug_uart = {
64 .name = "serial8250",
65 .id = PLAT8250_DEV_PLATFORM,
66 .dev = {
67 .platform_data = debug_uart_platform_data,
68 },
69};
70
71static struct platform_device *paz00_devices[] __initdata = {
72 &debug_uart,
73 &tegra_sdhci_device1,
74 &tegra_sdhci_device2,
75 &tegra_sdhci_device4,
76};
77
Marc Dietrichdda9cd22011-05-19 14:08:26 +020078static struct tegra_i2c_platform_data paz00_i2c1_platform_data = {
79 .bus_clk_rate = 400000,
80};
81
82static struct tegra_i2c_platform_data paz00_i2c2_platform_data = {
83 .bus_clk_rate = 400000,
84};
85
86static struct tegra_i2c_platform_data paz00_dvc_platform_data = {
87 .bus_clk_rate = 400000,
88};
89
90static void paz00_i2c_init(void)
91{
92 tegra_i2c_device1.dev.platform_data = &paz00_i2c1_platform_data;
93 tegra_i2c_device2.dev.platform_data = &paz00_i2c2_platform_data;
94 tegra_i2c_device4.dev.platform_data = &paz00_dvc_platform_data;
95
96 platform_device_register(&tegra_i2c_device1);
97 platform_device_register(&tegra_i2c_device2);
98 platform_device_register(&tegra_i2c_device4);
99}
100
Marc Dietrich13db7a72011-05-19 14:08:27 +0200101static struct tegra_ulpi_config ulpi_phy_config = {
102 .reset_gpio = TEGRA_ULPI_RST,
103 .clk = "cdev2",
104};
105
106static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
107 [0] = {
108 .operating_mode = TEGRA_USB_OTG,
109 .power_down_on_bus_suspend = 1,
110 },
111 [1] = {
112 .phy_config = &ulpi_phy_config,
113 .operating_mode = TEGRA_USB_HOST,
114 .power_down_on_bus_suspend = 1,
115 },
116 [2] = {
117 .operating_mode = TEGRA_USB_HOST,
118 .power_down_on_bus_suspend = 1,
119 },
120};
121
122static void paz00_usb_init(void)
123{
124 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
125 tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
126
127 platform_device_register(&tegra_ehci2_device);
128 platform_device_register(&tegra_ehci3_device);
129}
130
Marc Dietrich65b935a2011-03-07 21:01:31 +0100131static void __init tegra_paz00_fixup(struct machine_desc *desc,
132 struct tag *tags, char **cmdline, struct meminfo *mi)
133{
134 mi->nr_banks = 1;
135 mi->bank[0].start = PHYS_OFFSET;
136 mi->bank[0].size = 448 * SZ_1M;
137}
138
139static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
140 /* name parent rate enabled */
141 { "uartd", "pll_p", 216000000, true },
142 { NULL, NULL, 0, 0},
143};
144
Marc Dietrich65b935a2011-03-07 21:01:31 +0100145static struct tegra_sdhci_platform_data sdhci_pdata1 = {
146 .cd_gpio = TEGRA_GPIO_SD1_CD,
147 .wp_gpio = TEGRA_GPIO_SD1_WP,
148 .power_gpio = TEGRA_GPIO_SD1_POWER,
149};
150
151static struct tegra_sdhci_platform_data sdhci_pdata2 = {
152 .cd_gpio = -1,
153 .wp_gpio = -1,
154 .power_gpio = -1,
155};
156
157static struct tegra_sdhci_platform_data sdhci_pdata4 = {
158 .cd_gpio = TEGRA_GPIO_SD4_CD,
159 .wp_gpio = TEGRA_GPIO_SD4_WP,
160 .power_gpio = TEGRA_GPIO_SD4_POWER,
161 .is_8bit = 1,
162};
163
164static void __init tegra_paz00_init(void)
165{
166 tegra_clk_init_from_table(paz00_clk_init_table);
167
168 paz00_pinmux_init();
169
170 tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
171 tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
172 tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
173
174 platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
Marc Dietrichdda9cd22011-05-19 14:08:26 +0200175
176 paz00_i2c_init();
Marc Dietrich13db7a72011-05-19 14:08:27 +0200177 paz00_usb_init();
Marc Dietrich65b935a2011-03-07 21:01:31 +0100178}
179
180MACHINE_START(PAZ00, "paz00")
181 .boot_params = 0x00000100,
182 .fixup = tegra_paz00_fixup,
183 .map_io = tegra_map_common_io,
184 .init_early = tegra_init_early,
185 .init_irq = tegra_init_irq,
186 .timer = &tegra_timer,
187 .init_machine = tegra_paz00_init,
188MACHINE_END