Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2002,2007-2011, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __Z80_REG_H |
| 14 | #define __Z80_REG_H |
| 15 | |
| 16 | #define REG_VGC_IRQSTATUS__MH_MASK 0x00000001L |
| 17 | #define REG_VGC_IRQSTATUS__G2D_MASK 0x00000002L |
| 18 | #define REG_VGC_IRQSTATUS__FIFO_MASK 0x00000004L |
| 19 | |
| 20 | #define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 |
| 21 | #define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 |
| 22 | #define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 |
| 23 | #define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 |
| 24 | #define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a |
| 25 | #define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d |
| 26 | #define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e |
| 27 | #define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f |
| 28 | #define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 |
| 29 | #define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 |
| 30 | #define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 |
| 31 | #define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 |
| 32 | #define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 |
| 33 | #define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a |
| 34 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 35 | #define ADDR_VGC_MH_READ_ADDR 0x0510 |
| 36 | #define ADDR_VGC_MH_DATA_ADDR 0x0518 |
| 37 | #define ADDR_VGC_COMMANDSTREAM 0x0000 |
| 38 | #define ADDR_VGC_IRQENABLE 0x0438 |
| 39 | #define ADDR_VGC_IRQSTATUS 0x0418 |
| 40 | #define ADDR_VGC_IRQ_ACTIVE_CNT 0x04E0 |
| 41 | #define ADDR_VGC_MMUCOMMANDSTREAM 0x03FC |
| 42 | #define ADDR_VGV3_CONTROL 0x0070 |
| 43 | #define ADDR_VGV3_LAST 0x007F |
| 44 | #define ADDR_VGV3_MODE 0x0071 |
| 45 | #define ADDR_VGV3_NEXTADDR 0x0075 |
| 46 | #define ADDR_VGV3_NEXTCMD 0x0076 |
| 47 | #define ADDR_VGV3_WRITEADDR 0x0072 |
| 48 | |
| 49 | #endif /* __Z180_REG_H */ |