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review.evervolv.com / android_kernel_htc_msm8960 / 1707d4a47db0b51a89c8c256544e8d1a7bdffef4 / . / drivers / mtd / devices / msm_nand.h
blob: 2729c6bae237f1cb4efd5d47de7ec1fc10367e7d [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/* drivers/mtd/devices/msm_nand.h
2 *
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Copyright (C) 2007 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __DRIVERS_MTD_DEVICES_MSM_NAND_H
18#define __DRIVERS_MTD_DEVICES_MSM_NAND_H
19
20#include <mach/msm_iomap.h>
21
22extern unsigned long msm_nand_phys;
23extern unsigned long msm_nandc01_phys;
24extern unsigned long msm_nandc10_phys;
25extern unsigned long msm_nandc11_phys;
26extern unsigned long ebi2_register_base;
27
28#define NC01(X) ((X) + msm_nandc01_phys - msm_nand_phys)
29#define NC10(X) ((X) + msm_nandc10_phys - msm_nand_phys)
30#define NC11(X) ((X) + msm_nandc11_phys - msm_nand_phys)
31
32#define MSM_NAND_REG(off) (msm_nand_phys + (off))
33
34#define MSM_NAND_FLASH_CMD MSM_NAND_REG(0x0000)
35#define MSM_NAND_ADDR0 MSM_NAND_REG(0x0004)
36#define MSM_NAND_ADDR1 MSM_NAND_REG(0x0008)
37#define MSM_NAND_FLASH_CHIP_SELECT MSM_NAND_REG(0x000C)
38#define MSM_NAND_EXEC_CMD MSM_NAND_REG(0x0010)
39#define MSM_NAND_FLASH_STATUS MSM_NAND_REG(0x0014)
40#define MSM_NAND_BUFFER_STATUS MSM_NAND_REG(0x0018)
41#define MSM_NAND_SFLASHC_STATUS MSM_NAND_REG(0x001C)
42#define MSM_NAND_DEV0_CFG0 MSM_NAND_REG(0x0020)
43#define MSM_NAND_DEV0_CFG1 MSM_NAND_REG(0x0024)
44#define MSM_NAND_DEV0_ECC_CFG MSM_NAND_REG(0x0028)
45#define MSM_NAND_DEV1_ECC_CFG MSM_NAND_REG(0x002C)
46#define MSM_NAND_DEV1_CFG0 MSM_NAND_REG(0x0030)
47#define MSM_NAND_DEV1_CFG1 MSM_NAND_REG(0x0034)
48#define MSM_NAND_SFLASHC_CMD MSM_NAND_REG(0x0038)
49#define MSM_NAND_SFLASHC_EXEC_CMD MSM_NAND_REG(0x003C)
50#define MSM_NAND_READ_ID MSM_NAND_REG(0x0040)
51#define MSM_NAND_READ_STATUS MSM_NAND_REG(0x0044)
52#define MSM_NAND_CONFIG_DATA MSM_NAND_REG(0x0050)
53#define MSM_NAND_CONFIG MSM_NAND_REG(0x0054)
54#define MSM_NAND_CONFIG_MODE MSM_NAND_REG(0x0058)
55#define MSM_NAND_CONFIG_STATUS MSM_NAND_REG(0x0060)
56#define MSM_NAND_MACRO1_REG MSM_NAND_REG(0x0064)
57#define MSM_NAND_XFR_STEP1 MSM_NAND_REG(0x0070)
58#define MSM_NAND_XFR_STEP2 MSM_NAND_REG(0x0074)
59#define MSM_NAND_XFR_STEP3 MSM_NAND_REG(0x0078)
60#define MSM_NAND_XFR_STEP4 MSM_NAND_REG(0x007C)
61#define MSM_NAND_XFR_STEP5 MSM_NAND_REG(0x0080)
62#define MSM_NAND_XFR_STEP6 MSM_NAND_REG(0x0084)
63#define MSM_NAND_XFR_STEP7 MSM_NAND_REG(0x0088)
64#define MSM_NAND_GENP_REG0 MSM_NAND_REG(0x0090)
65#define MSM_NAND_GENP_REG1 MSM_NAND_REG(0x0094)
66#define MSM_NAND_GENP_REG2 MSM_NAND_REG(0x0098)
67#define MSM_NAND_GENP_REG3 MSM_NAND_REG(0x009C)
68#define MSM_NAND_DEV_CMD0 MSM_NAND_REG(0x00A0)
69#define MSM_NAND_DEV_CMD1 MSM_NAND_REG(0x00A4)
70#define MSM_NAND_DEV_CMD2 MSM_NAND_REG(0x00A8)
71#define MSM_NAND_DEV_CMD_VLD MSM_NAND_REG(0x00AC)
72#define MSM_NAND_EBI2_MISR_SIG_REG MSM_NAND_REG(0x00B0)
73#define MSM_NAND_ADDR2 MSM_NAND_REG(0x00C0)
74#define MSM_NAND_ADDR3 MSM_NAND_REG(0x00C4)
75#define MSM_NAND_ADDR4 MSM_NAND_REG(0x00C8)
76#define MSM_NAND_ADDR5 MSM_NAND_REG(0x00CC)
77#define MSM_NAND_DEV_CMD3 MSM_NAND_REG(0x00D0)
78#define MSM_NAND_DEV_CMD4 MSM_NAND_REG(0x00D4)
79#define MSM_NAND_DEV_CMD5 MSM_NAND_REG(0x00D8)
80#define MSM_NAND_DEV_CMD6 MSM_NAND_REG(0x00DC)
81#define MSM_NAND_SFLASHC_BURST_CFG MSM_NAND_REG(0x00E0)
82#define MSM_NAND_ADDR6 MSM_NAND_REG(0x00E4)
83#define MSM_NAND_EBI2_ECC_BUF_CFG MSM_NAND_REG(0x00F0)
84#define MSM_NAND_HW_INFO MSM_NAND_REG(0x00FC)
85#define MSM_NAND_FLASH_BUFFER MSM_NAND_REG(0x0100)
86
87/* device commands */
88
89#define MSM_NAND_CMD_SOFT_RESET 0x01
90#define MSM_NAND_CMD_PAGE_READ 0x32
91#define MSM_NAND_CMD_PAGE_READ_ECC 0x33
92#define MSM_NAND_CMD_PAGE_READ_ALL 0x34
93#define MSM_NAND_CMD_SEQ_PAGE_READ 0x15
94#define MSM_NAND_CMD_PRG_PAGE 0x36
95#define MSM_NAND_CMD_PRG_PAGE_ECC 0x37
96#define MSM_NAND_CMD_PRG_PAGE_ALL 0x39
97#define MSM_NAND_CMD_BLOCK_ERASE 0x3A
98#define MSM_NAND_CMD_FETCH_ID 0x0B
99#define MSM_NAND_CMD_STATUS 0x0C
100#define MSM_NAND_CMD_RESET 0x0D
101
102/* Sflash Commands */
103
104#define MSM_NAND_SFCMD_DATXS 0x0
105#define MSM_NAND_SFCMD_CMDXS 0x1
106#define MSM_NAND_SFCMD_BURST 0x0
107#define MSM_NAND_SFCMD_ASYNC 0x1
108#define MSM_NAND_SFCMD_ABORT 0x1
109#define MSM_NAND_SFCMD_REGRD 0x2
110#define MSM_NAND_SFCMD_REGWR 0x3
111#define MSM_NAND_SFCMD_INTLO 0x4
112#define MSM_NAND_SFCMD_INTHI 0x5
113#define MSM_NAND_SFCMD_DATRD 0x6
114#define MSM_NAND_SFCMD_DATWR 0x7
115
116#define SFLASH_PREPCMD(numxfr, offval, delval, trnstp, mode, opcode) \
117 ((numxfr<<20)|(offval<<12)|(delval<<6)|(trnstp<<5)|(mode<<4)|opcode)
118
119#define SFLASH_BCFG 0x20100327
120
121/* Onenand addresses */
122
123#define ONENAND_MANUFACTURER_ID 0xF000
124#define ONENAND_DEVICE_ID 0xF001
125#define ONENAND_VERSION_ID 0xF002
126#define ONENAND_DATA_BUFFER_SIZE 0xF003
127#define ONENAND_BOOT_BUFFER_SIZE 0xF004
128#define ONENAND_AMOUNT_OF_BUFFERS 0xF005
129#define ONENAND_TECHNOLOGY 0xF006
130#define ONENAND_START_ADDRESS_1 0xF100
131#define ONENAND_START_ADDRESS_2 0xF101
132#define ONENAND_START_ADDRESS_3 0xF102
133#define ONENAND_START_ADDRESS_4 0xF103
134#define ONENAND_START_ADDRESS_5 0xF104
135#define ONENAND_START_ADDRESS_6 0xF105
136#define ONENAND_START_ADDRESS_7 0xF106
137#define ONENAND_START_ADDRESS_8 0xF107
138#define ONENAND_START_BUFFER 0xF200
139#define ONENAND_COMMAND 0xF220
140#define ONENAND_SYSTEM_CONFIG_1 0xF221
141#define ONENAND_SYSTEM_CONFIG_2 0xF222
142#define ONENAND_CONTROLLER_STATUS 0xF240
143#define ONENAND_INTERRUPT_STATUS 0xF241
144#define ONENAND_START_BLOCK_ADDRESS 0xF24C
145#define ONENAND_WRITE_PROT_STATUS 0xF24E
146#define ONENAND_ECC_STATUS 0xFF00
147#define ONENAND_ECC_ERRPOS_MAIN0 0xFF01
148#define ONENAND_ECC_ERRPOS_SPARE0 0xFF02
149#define ONENAND_ECC_ERRPOS_MAIN1 0xFF03
150#define ONENAND_ECC_ERRPOS_SPARE1 0xFF04
151#define ONENAND_ECC_ERRPOS_MAIN2 0xFF05
152#define ONENAND_ECC_ERRPOS_SPARE2 0xFF06
153#define ONENAND_ECC_ERRPOS_MAIN3 0xFF07
154#define ONENAND_ECC_ERRPOS_SPARE3 0xFF08
155
156/* Onenand commands */
157#define ONENAND_WP_US (1 << 2)
158#define ONENAND_WP_LS (1 << 1)
159
160#define ONENAND_CMDLOAD 0x0000
161#define ONENAND_CMDLOADSPARE 0x0013
162#define ONENAND_CMDPROG 0x0080
163#define ONENAND_CMDPROGSPARE 0x001A
164#define ONENAND_CMDERAS 0x0094
165#define ONENAND_CMD_UNLOCK 0x0023
166#define ONENAND_CMD_LOCK 0x002A
167
168#define ONENAND_SYSCFG1_ECCENA(mode) (0x40E0 | (mode ? 0 : 0x8002))
169#define ONENAND_SYSCFG1_ECCDIS(mode) (0x41E0 | (mode ? 0 : 0x8002))
170
171#define ONENAND_CLRINTR 0x0000
172#define ONENAND_STARTADDR1_RES 0x07FF
173#define ONENAND_STARTADDR3_RES 0x07FF
174
175#define DATARAM0_0 0x8
176#define DEVICE_FLASHCORE_0 (0 << 15)
177#define DEVICE_FLASHCORE_1 (1 << 15)
178#define DEVICE_BUFFERRAM_0 (0 << 15)
179#define DEVICE_BUFFERRAM_1 (1 << 15)
180#define ONENAND_DEVICE_IS_DDP (1 << 3)
181
182#define CLEAN_DATA_16 0xFFFF
183#define CLEAN_DATA_32 0xFFFFFFFF
184
185#define EBI2_REG(off) (ebi2_register_base + (off))
186#define EBI2_CHIP_SELECT_CFG0 EBI2_REG(0x0000)
187#define EBI2_CFG_REG EBI2_REG(0x0004)
188#define EBI2_NAND_ADM_MUX EBI2_REG(0x005C)
189
190#define MSM_NAND_BUF_STAT_UNCRCTBL_ERR (1 << 8)
191#define MSM_NAND_BUF_STAT_NUM_ERR_MASK (enable_bch_ecc ? 0x1F : 0x0F)
192
193extern struct flash_platform_data msm_nand_data;
194
195#endif