blob: cb728a0c3167ef014c41ee42d8b08f37a517e7da [file] [log] [blame]
Kiran Kumar H Ndd128472011-12-01 09:35:34 -08001/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
Shuzhen Wangce650862011-08-17 15:27:01 -070013#ifndef __MSM_ISP_H__
14#define __MSM_ISP_H__
15
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080016#define BIT(nr) (1UL << (nr))
17
Shuzhen Wangce650862011-08-17 15:27:01 -070018/* ISP message IDs */
19#define MSG_ID_RESET_ACK 0
20#define MSG_ID_START_ACK 1
21#define MSG_ID_STOP_ACK 2
22#define MSG_ID_UPDATE_ACK 3
23#define MSG_ID_OUTPUT_P 4
24#define MSG_ID_OUTPUT_T 5
25#define MSG_ID_OUTPUT_S 6
26#define MSG_ID_OUTPUT_V 7
27#define MSG_ID_SNAPSHOT_DONE 8
28#define MSG_ID_STATS_AEC 9
29#define MSG_ID_STATS_AF 10
30#define MSG_ID_STATS_AWB 11
31#define MSG_ID_STATS_RS 12
32#define MSG_ID_STATS_CS 13
33#define MSG_ID_STATS_IHIST 14
34#define MSG_ID_STATS_SKIN 15
35#define MSG_ID_EPOCH1 16
36#define MSG_ID_EPOCH2 17
37#define MSG_ID_SYNC_TIMER0_DONE 18
38#define MSG_ID_SYNC_TIMER1_DONE 19
39#define MSG_ID_SYNC_TIMER2_DONE 20
40#define MSG_ID_ASYNC_TIMER0_DONE 21
41#define MSG_ID_ASYNC_TIMER1_DONE 22
42#define MSG_ID_ASYNC_TIMER2_DONE 23
43#define MSG_ID_ASYNC_TIMER3_DONE 24
44#define MSG_ID_AE_OVERFLOW 25
45#define MSG_ID_AF_OVERFLOW 26
46#define MSG_ID_AWB_OVERFLOW 27
47#define MSG_ID_RS_OVERFLOW 28
48#define MSG_ID_CS_OVERFLOW 29
49#define MSG_ID_IHIST_OVERFLOW 30
50#define MSG_ID_SKIN_OVERFLOW 31
51#define MSG_ID_AXI_ERROR 32
52#define MSG_ID_CAMIF_OVERFLOW 33
53#define MSG_ID_VIOLATION 34
54#define MSG_ID_CAMIF_ERROR 35
55#define MSG_ID_BUS_OVERFLOW 36
56#define MSG_ID_SOF_ACK 37
57#define MSG_ID_STOP_REC_ACK 38
Suresh Vankadara055cb8e2012-01-18 00:50:04 +053058#define MSG_ID_STATS_AWB_AEC 39
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080059#define MSG_ID_OUTPUT_PRIMARY 40
60#define MSG_ID_OUTPUT_SECONDARY 41
Shuzhen Wang74768242011-09-02 17:38:01 -070061#define MSG_ID_STATS_COMPOSITE 42
Shuzhen Wangce650862011-08-17 15:27:01 -070062
63/* ISP command IDs */
64#define VFE_CMD_DUMMY_0 0
65#define VFE_CMD_SET_CLK 1
66#define VFE_CMD_RESET 2
67#define VFE_CMD_START 3
68#define VFE_CMD_TEST_GEN_START 4
69#define VFE_CMD_OPERATION_CFG 5
70#define VFE_CMD_AXI_OUT_CFG 6
71#define VFE_CMD_CAMIF_CFG 7
72#define VFE_CMD_AXI_INPUT_CFG 8
73#define VFE_CMD_BLACK_LEVEL_CFG 9
Ujwal Pateledcbdcc2011-08-24 09:14:14 -070074#define VFE_CMD_MESH_ROLL_OFF_CFG 10
Shuzhen Wangce650862011-08-17 15:27:01 -070075#define VFE_CMD_DEMUX_CFG 11
76#define VFE_CMD_FOV_CFG 12
77#define VFE_CMD_MAIN_SCALER_CFG 13
78#define VFE_CMD_WB_CFG 14
79#define VFE_CMD_COLOR_COR_CFG 15
80#define VFE_CMD_RGB_G_CFG 16
81#define VFE_CMD_LA_CFG 17
82#define VFE_CMD_CHROMA_EN_CFG 18
83#define VFE_CMD_CHROMA_SUP_CFG 19
84#define VFE_CMD_MCE_CFG 20
85#define VFE_CMD_SK_ENHAN_CFG 21
86#define VFE_CMD_ASF_CFG 22
87#define VFE_CMD_S2Y_CFG 23
88#define VFE_CMD_S2CbCr_CFG 24
89#define VFE_CMD_CHROMA_SUBS_CFG 25
90#define VFE_CMD_OUT_CLAMP_CFG 26
91#define VFE_CMD_FRAME_SKIP_CFG 27
92#define VFE_CMD_DUMMY_1 28
93#define VFE_CMD_DUMMY_2 29
94#define VFE_CMD_DUMMY_3 30
95#define VFE_CMD_UPDATE 31
96#define VFE_CMD_BL_LVL_UPDATE 32
97#define VFE_CMD_DEMUX_UPDATE 33
98#define VFE_CMD_FOV_UPDATE 34
99#define VFE_CMD_MAIN_SCALER_UPDATE 35
100#define VFE_CMD_WB_UPDATE 36
101#define VFE_CMD_COLOR_COR_UPDATE 37
102#define VFE_CMD_RGB_G_UPDATE 38
103#define VFE_CMD_LA_UPDATE 39
104#define VFE_CMD_CHROMA_EN_UPDATE 40
105#define VFE_CMD_CHROMA_SUP_UPDATE 41
106#define VFE_CMD_MCE_UPDATE 42
107#define VFE_CMD_SK_ENHAN_UPDATE 43
108#define VFE_CMD_S2CbCr_UPDATE 44
109#define VFE_CMD_S2Y_UPDATE 45
110#define VFE_CMD_ASF_UPDATE 46
111#define VFE_CMD_FRAME_SKIP_UPDATE 47
112#define VFE_CMD_CAMIF_FRAME_UPDATE 48
113#define VFE_CMD_STATS_AF_UPDATE 49
114#define VFE_CMD_STATS_AE_UPDATE 50
115#define VFE_CMD_STATS_AWB_UPDATE 51
116#define VFE_CMD_STATS_RS_UPDATE 52
117#define VFE_CMD_STATS_CS_UPDATE 53
118#define VFE_CMD_STATS_SKIN_UPDATE 54
119#define VFE_CMD_STATS_IHIST_UPDATE 55
120#define VFE_CMD_DUMMY_4 56
121#define VFE_CMD_EPOCH1_ACK 57
122#define VFE_CMD_EPOCH2_ACK 58
123#define VFE_CMD_START_RECORDING 59
124#define VFE_CMD_STOP_RECORDING 60
125#define VFE_CMD_DUMMY_5 61
126#define VFE_CMD_DUMMY_6 62
127#define VFE_CMD_CAPTURE 63
128#define VFE_CMD_DUMMY_7 64
129#define VFE_CMD_STOP 65
130#define VFE_CMD_GET_HW_VERSION 66
131#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
132#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
133#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
134#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
135#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
136#define VFE_CMD_RAW_OUT_BUF_ENQ 72
137#define VFE_CMD_RAW_IN_BUF_ENQ 73
138#define VFE_CMD_STATS_AF_ENQ 74
139#define VFE_CMD_STATS_AE_ENQ 75
140#define VFE_CMD_STATS_AWB_ENQ 76
141#define VFE_CMD_STATS_RS_ENQ 77
142#define VFE_CMD_STATS_CS_ENQ 78
143#define VFE_CMD_STATS_SKIN_ENQ 79
144#define VFE_CMD_STATS_IHIST_ENQ 80
145#define VFE_CMD_DUMMY_8 81
146#define VFE_CMD_JPEG_ENC_CFG 82
147#define VFE_CMD_DUMMY_9 83
148#define VFE_CMD_STATS_AF_START 84
149#define VFE_CMD_STATS_AF_STOP 85
150#define VFE_CMD_STATS_AE_START 86
151#define VFE_CMD_STATS_AE_STOP 87
152#define VFE_CMD_STATS_AWB_START 88
153#define VFE_CMD_STATS_AWB_STOP 89
154#define VFE_CMD_STATS_RS_START 90
155#define VFE_CMD_STATS_RS_STOP 91
156#define VFE_CMD_STATS_CS_START 92
157#define VFE_CMD_STATS_CS_STOP 93
158#define VFE_CMD_STATS_SKIN_START 94
159#define VFE_CMD_STATS_SKIN_STOP 95
160#define VFE_CMD_STATS_IHIST_START 96
161#define VFE_CMD_STATS_IHIST_STOP 97
162#define VFE_CMD_DUMMY_10 98
163#define VFE_CMD_SYNC_TIMER_SETTING 99
164#define VFE_CMD_ASYNC_TIMER_SETTING 100
165#define VFE_CMD_LIVESHOT 101
166#define VFE_CMD_LA_SETUP 102
167#define VFE_CMD_LINEARIZATION_CFG 103
168#define VFE_CMD_DEMOSAICV3 104
169#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
170#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
171#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
172#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
173#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
174#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
175#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
176#define VFE_CMD_XBAR_CFG 112
Ujwal Patel1fe4c9c2011-10-07 12:19:52 -0700177#define VFE_CMD_MODULE_CFG 113
Shuzhen Wangce650862011-08-17 15:27:01 -0700178#define VFE_CMD_ZSL 114
179#define VFE_CMD_LINEARIZATION_UPDATE 115
180#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
181#define VFE_CMD_CLF_CFG 117
182#define VFE_CMD_CLF_LUMA_UPDATE 118
183#define VFE_CMD_CLF_CHROMA_UPDATE 119
Ujwal Pateledcbdcc2011-08-24 09:14:14 -0700184#define VFE_CMD_PCA_ROLL_OFF_CFG 120
185#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
Ujwal Patel6e4308d2011-10-25 11:24:52 -0700186#define VFE_CMD_GET_REG_DUMP 122
187#define VFE_CMD_GET_LINEARIZATON_TABLE 123
188#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
189#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
190#define VFE_CMD_GET_RGB_G_TABLE 126
191#define VFE_CMD_GET_LA_TABLE 127
Azam Sadiq Pasha Kapatrala Syed5156dd42011-10-27 19:30:13 -0700192#define VFE_CMD_DEMOSAICV3_UPDATE 128
Suresh Vankadara055cb8e2012-01-18 00:50:04 +0530193#define VFE_CMD_ACTIVE_REGION_CFG 129
194#define VFE_CMD_COLOR_PROCESSING_CONFIG 130
195#define VFE_CMD_STATS_WB_AEC_CONFIG 131
196#define VFE_CMD_STATS_WB_AEC_UPDATE 132
197#define VFE_CMD_Y_GAMMA_CONFIG 133
198#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134
199#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135
Kiran Kumar H Ndd128472011-12-01 09:35:34 -0800200#define VFE_CMD_CAPTURE_RAW 136
201#define VFE_CMD_STOP_LIVESHOT 137
Sandeep Kodimelac6f78672012-03-07 10:44:04 +0530202#define VFE_CMD_RECONFIG_VFE 138
Shuzhen Wangce650862011-08-17 15:27:01 -0700203
Shuzhen Wang6b0f3322011-08-26 12:14:43 -0700204struct msm_isp_cmd {
205 int32_t id;
206 uint16_t length;
207 void *value;
208};
209
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700210#define VPE_CMD_DUMMY_0 0
211#define VPE_CMD_INIT 1
212#define VPE_CMD_DEINIT 2
213#define VPE_CMD_ENABLE 3
214#define VPE_CMD_DISABLE 4
215#define VPE_CMD_RESET 5
216#define VPE_CMD_FLUSH 6
217#define VPE_CMD_OPERATION_MODE_CFG 7
218#define VPE_CMD_INPUT_PLANE_CFG 8
219#define VPE_CMD_OUTPUT_PLANE_CFG 9
220#define VPE_CMD_INPUT_PLANE_UPDATE 10
221#define VPE_CMD_SCALE_CFG_TYPE 11
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700222#define VPE_CMD_ZOOM 13
Kevin Chan318d7cb2011-11-29 14:24:26 -0800223#define VPE_CMD_MAX 14
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700224
225#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */
226#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */
227#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */
228
229#define MCTL_CMD_DUMMY_0 0 /* not used */
230#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */
231#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */
232#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700233
234/* event typese sending to MCTL PP module */
235#define MCTL_PP_EVENT_NOTUSED 0
236#define MCTL_PP_EVENT_CMD_ACK 1
237
Kiran Kumar H N8f68c592012-01-06 15:11:47 -0800238#define VPE_OPERATION_MODE_CFG_LEN 4
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700239#define VPE_INPUT_PLANE_CFG_LEN 24
Kiran Kumar H N8f68c592012-01-06 15:11:47 -0800240#define VPE_OUTPUT_PLANE_CFG_LEN 20
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700241#define VPE_INPUT_PLANE_UPDATE_LEN 12
242#define VPE_SCALER_CONFIG_LEN 260
243#define VPE_DIS_OFFSET_CFG_LEN 12
244
Jignesh Mehtabde84242012-02-16 13:21:22 -0800245
246#define CAPTURE_WIDTH 1280
247#define IMEM_Y_SIZE (CAPTURE_WIDTH*16)
248#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8)
249
250#define IMEM_Y_PING_OFFSET 0x2E000000
251#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE)
252
253#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE)
254#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE)
255
Jignesh Mehta6cf8a742012-02-04 23:40:50 -0800256
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700257struct msm_vpe_op_mode_cfg {
258 uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
259};
260
261struct msm_vpe_input_plane_cfg {
262 uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
263};
264
265struct msm_vpe_output_plane_cfg {
266 uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
267};
268
269struct msm_vpe_input_plane_update_cfg {
270 uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
271};
272
273struct msm_vpe_scaler_cfg {
274 uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
275};
276
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700277struct msm_vpe_flush_frame_buffer {
278 uint32_t src_buf_handle;
279 uint32_t dest_buf_handle;
280 int path;
281};
282
283struct msm_mctl_pp_frame_buffer {
284 uint32_t buf_handle;
285 int path;
286};
287struct msm_mctl_pp_divert_pp {
288 int path;
Mingcheng Zhu8feaa3f2011-11-23 11:33:52 -0800289 int enable;
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700290};
291struct msm_vpe_clock_rate {
292 uint32_t rate;
293};
294struct msm_pp_crop {
295 uint32_t src_x;
296 uint32_t src_y;
297 uint32_t src_w;
298 uint32_t src_h;
299 uint32_t dst_x;
300 uint32_t dst_y;
301 uint32_t dst_w;
302 uint32_t dst_h;
303 uint8_t update_flag;
304};
305#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0)
306#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1)
307
308struct msm_mctl_pp_frame_cmd {
309 uint32_t cookie;
310 uint8_t vpe_output_action;
311 uint32_t src_buf_handle;
312 uint32_t dest_buf_handle;
313 struct msm_pp_crop crop;
314 int path;
315 /* TBD: 3D related */
316};
317
Kiran Kumar H Ndd128472011-12-01 09:35:34 -0800318#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0)
319#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1)
320#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2)
321#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3)
322#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4)
323#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5)
324#define VFE_OUTPUTS_PREVIEW BIT(6)
325#define VFE_OUTPUTS_VIDEO BIT(7)
326#define VFE_OUTPUTS_RAW BIT(8)
Jignesh Mehta6cf8a742012-02-04 23:40:50 -0800327#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
328#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
Kiran Kumar H Ndd128472011-12-01 09:35:34 -0800329
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700330#endif /*__MSM_ISP_H__*/
331