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review.evervolv.com / android_kernel_htc_msm8960 / 1844c9bc0b2fed3023551c1affe033ab38e90b9a / . / arch / s390 / kernel / head64.S
blob: 39580e768658e0b23f76587b6fb59e5c000936f1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
Heiko Carstens0ad775d2005-11-07 00:59:12 -0800[diff] [blame]2 * arch/s390/kernel/head64.S
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3 *
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame^]4 * Copyright (C) IBM Corp. 1999,2010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5 *
Heiko Carstens0ad775d2005-11-07 00:59:12 -0800[diff] [blame]6 * Author(s): Hartmut Penner <hp@de.ibm.com>
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>
8 * Rob van der Heij <rvdhei@iae.nl>
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]11 */
12
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame^]13#include <linux/init.h>
14#include <asm/asm-offsets.h>
15#include <asm/thread_info.h>
16#include <asm/page.h>
Heiko Carstensb1b70302006-06-29 14:58:17 +0200[diff] [blame]17
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame^]18__HEAD
19 .globl startup_continue
Heiko Carstensb1b70302006-06-29 14:58:17 +0200[diff] [blame]20startup_continue:
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame^]21 larl %r1,sched_clock_base_cc
22 mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK
23 larl %r13,.LPG1 # get base
Hendrik Bruecknercf87b742009-12-07 12:44:42 +0100[diff] [blame]24 lmh %r0,%r15,.Lzero64-.LPG1(%r13) # clear high-order half
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]25 lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
26 lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
27 # move IPL device to lowcore
Martin Schwidefskyc742b312008-12-31 15:11:42 +0100[diff] [blame]28 lghi %r0,__LC_PASTE
29 stg %r0,__LC_VDSO_PER_CPU
Heiko Carstense87bfe52006-09-20 15:59:15 +0200[diff] [blame]30#
31# Setup stack
32#
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]33 larl %r15,init_thread_union
Heiko Carstens0c88ee52009-09-11 10:28:58 +0200[diff] [blame]34 stg %r15,__LC_THREAD_INFO # cache thread info in lowcore
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]35 lg %r14,__TI_task(%r15) # cache current in lowcore
36 stg %r14,__LC_CURRENT
37 aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
38 stg %r15,__LC_KERNEL_STACK # set end of kernel stack
39 aghi %r15,-160
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]40#
Hongjie Yangfe355b72007-02-05 21:18:24 +0100[diff] [blame]41# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
42# and create a kernel NSS if the SAVESYS= parm is defined
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]43#
Hongjie Yangfe355b72007-02-05 21:18:24 +0100[diff] [blame]44 brasl %r14,startup_init
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]45 lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
46 # virtual and never return ...
47 .align 16
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame^]48.LPG1:
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]49.Lentry:.quad 0x0000000180000000,_stext
Gerald Schaefer53492b12008-04-30 13:38:46 +0200[diff] [blame]50.Lctl: .quad 0x04350002 # cr0: various things
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]51 .quad 0 # cr1: primary space segment table
52 .quad .Lduct # cr2: dispatchable unit control table
53 .quad 0 # cr3: instruction authorization
54 .quad 0 # cr4: instruction authorization
Gerald Schaefer482b05d2007-03-05 23:35:54 +0100[diff] [blame]55 .quad .Lduct # cr5: primary-aste origin
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]56 .quad 0 # cr6: I/O interrupts
57 .quad 0 # cr7: secondary space segment table
58 .quad 0 # cr8: access registers translation
59 .quad 0 # cr9: tracing off
60 .quad 0 # cr10: tracing off
61 .quad 0 # cr11: tracing off
62 .quad 0 # cr12: tracing off
63 .quad 0 # cr13: home space segment table
64 .quad 0xc0000000 # cr14: machine check handling off
65 .quad 0 # cr15: linkage stack operations
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]66.Lpcmsk:.quad 0x0000000180000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]67.L4malign:.quad 0xffffffffffc00000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]68.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
69.Lnop: .long 0x07000700
Hendrik Bruecknercf87b742009-12-07 12:44:42 +0100[diff] [blame]70.Lzero64:.fill 16,4,0x0
Heiko Carstensb1b70302006-06-29 14:58:17 +0200[diff] [blame]71.Lparmaddr:
72 .quad PARMAREA
Gerald Schaefer482b05d2007-03-05 23:35:54 +0100[diff] [blame]73 .align 64
74.Lduct: .long 0,0,0,0,.Lduald,0,0,0
75 .long 0,0,0,0,0,0,0,0
76 .align 128
77.Lduald:.rept 8
78 .long 0x80000000,0,0,0 # invalid access-list entries
79 .endr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]80
Heiko Carstens615b04b2007-02-21 10:55:37 +0100[diff] [blame]81 .globl _ehead
82_ehead:
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame^]83
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]84#ifdef CONFIG_SHARED_KERNEL
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]85 .org 0x100000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]86#endif
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]87
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]88#
Heiko Carstensb1b70302006-06-29 14:58:17 +0200[diff] [blame]89# startup-code, running in absolute addressing mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]90#
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]91 .globl _stext
92_stext: basr %r13,0 # get base
Heiko Carstens1e8e3382005-10-30 15:00:11 -0800[diff] [blame]93.LPG3:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]94# check control registers
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]95 stctg %c0,%c15,0(%r15)
96 oi 6(%r15),0x40 # enable sigp emergency signal
97 oi 4(%r15),0x10 # switch on low address proctection
98 lctlg %c0,%c15,0(%r15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]99
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]100 lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
101 brasl %r14,start_kernel # go to C code
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]102#
103# We returned from start_kernel ?!? PANIK
104#
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]105 basr %r13,0
106 lpswe .Ldw-.(%r13) # load disabled wait psw
Heiko Carstense87bfe52006-09-20 15:59:15 +0200[diff] [blame]107
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]108 .align 8
109.Ldw: .quad 0x0002000180000000,0x0000000000000000
110.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0