Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / 18a0c23617a2cb1c2e55e650046c2084d823fde0 / . / drivers / atm / idt77252.c
blob: b4a76cade646badde872e6895c07c97339465a22 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*******************************************************************
2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
3 *
4 * $Author: ecd $
5 * $Date: 2001/11/11 08:13:54 $
6 *
7 * Copyright (c) 2000 ATecoM GmbH
8 *
9 * The author may be reached at ecd@atecom.com.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *******************************************************************/
32static char const rcsid[] =
33"$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
34
35
36#include <linux/module.h>
37#include <linux/config.h>
38#include <linux/pci.h>
39#include <linux/skbuff.h>
40#include <linux/kernel.h>
41#include <linux/vmalloc.h>
42#include <linux/netdevice.h>
43#include <linux/atmdev.h>
44#include <linux/atm.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/bitops.h>
48#include <linux/wait.h>
Marcelo Feitoza Parisie1bd2322005-07-19 13:55:14 -0700[diff] [blame]49#include <linux/jiffies.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]50#include <asm/semaphore.h>
51#include <asm/io.h>
52#include <asm/uaccess.h>
53#include <asm/atomic.h>
54#include <asm/byteorder.h>
55
56#ifdef CONFIG_ATM_IDT77252_USE_SUNI
57#include "suni.h"
58#endif /* CONFIG_ATM_IDT77252_USE_SUNI */
59
60
61#include "idt77252.h"
62#include "idt77252_tables.h"
63
64static unsigned int vpibits = 1;
65
66
67#define CONFIG_ATM_IDT77252_SEND_IDLE 1
68
69
70/*
71 * Debug HACKs.
72 */
73#define DEBUG_MODULE 1
74#undef HAVE_EEPROM /* does not work, yet. */
75
76#ifdef CONFIG_ATM_IDT77252_DEBUG
77static unsigned long debug = DBG_GENERAL;
78#endif
79
80
81#define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
82
83
84/*
85 * SCQ Handling.
86 */
87static struct scq_info *alloc_scq(struct idt77252_dev *, int);
88static void free_scq(struct idt77252_dev *, struct scq_info *);
89static int queue_skb(struct idt77252_dev *, struct vc_map *,
90 struct sk_buff *, int oam);
91static void drain_scq(struct idt77252_dev *, struct vc_map *);
92static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
93static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
94
95/*
96 * FBQ Handling.
97 */
98static int push_rx_skb(struct idt77252_dev *,
99 struct sk_buff *, int queue);
100static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
101static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
102static void recycle_rx_pool_skb(struct idt77252_dev *,
103 struct rx_pool *);
104static void add_rx_skb(struct idt77252_dev *, int queue,
105 unsigned int size, unsigned int count);
106
107/*
108 * RSQ Handling.
109 */
110static int init_rsq(struct idt77252_dev *);
111static void deinit_rsq(struct idt77252_dev *);
112static void idt77252_rx(struct idt77252_dev *);
113
114/*
115 * TSQ handling.
116 */
117static int init_tsq(struct idt77252_dev *);
118static void deinit_tsq(struct idt77252_dev *);
119static void idt77252_tx(struct idt77252_dev *);
120
121
122/*
123 * ATM Interface.
124 */
125static void idt77252_dev_close(struct atm_dev *dev);
126static int idt77252_open(struct atm_vcc *vcc);
127static void idt77252_close(struct atm_vcc *vcc);
128static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
129static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
130 int flags);
131static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
132 unsigned long addr);
133static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
134static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
135 int flags);
136static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
137 char *page);
138static void idt77252_softint(void *dev_id);
139
140
141static struct atmdev_ops idt77252_ops =
142{
143 .dev_close = idt77252_dev_close,
144 .open = idt77252_open,
145 .close = idt77252_close,
146 .send = idt77252_send,
147 .send_oam = idt77252_send_oam,
148 .phy_put = idt77252_phy_put,
149 .phy_get = idt77252_phy_get,
150 .change_qos = idt77252_change_qos,
151 .proc_read = idt77252_proc_read,
152 .owner = THIS_MODULE
153};
154
155static struct idt77252_dev *idt77252_chain = NULL;
156static unsigned int idt77252_sram_write_errors = 0;
157
158/*****************************************************************************/
159/* */
160/* I/O and Utility Bus */
161/* */
162/*****************************************************************************/
163
164static void
165waitfor_idle(struct idt77252_dev *card)
166{
167 u32 stat;
168
169 stat = readl(SAR_REG_STAT);
170 while (stat & SAR_STAT_CMDBZ)
171 stat = readl(SAR_REG_STAT);
172}
173
174static u32
175read_sram(struct idt77252_dev *card, unsigned long addr)
176{
177 unsigned long flags;
178 u32 value;
179
180 spin_lock_irqsave(&card->cmd_lock, flags);
181 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
182 waitfor_idle(card);
183 value = readl(SAR_REG_DR0);
184 spin_unlock_irqrestore(&card->cmd_lock, flags);
185 return value;
186}
187
188static void
189write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
190{
191 unsigned long flags;
192
193 if ((idt77252_sram_write_errors == 0) &&
194 (((addr > card->tst[0] + card->tst_size - 2) &&
195 (addr < card->tst[0] + card->tst_size)) ||
196 ((addr > card->tst[1] + card->tst_size - 2) &&
197 (addr < card->tst[1] + card->tst_size)))) {
198 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
199 card->name, addr, value);
200 }
201
202 spin_lock_irqsave(&card->cmd_lock, flags);
203 writel(value, SAR_REG_DR0);
204 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
205 waitfor_idle(card);
206 spin_unlock_irqrestore(&card->cmd_lock, flags);
207}
208
209static u8
210read_utility(void *dev, unsigned long ubus_addr)
211{
212 struct idt77252_dev *card = dev;
213 unsigned long flags;
214 u8 value;
215
216 if (!card) {
217 printk("Error: No such device.\n");
218 return -1;
219 }
220
221 spin_lock_irqsave(&card->cmd_lock, flags);
222 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
223 waitfor_idle(card);
224 value = readl(SAR_REG_DR0);
225 spin_unlock_irqrestore(&card->cmd_lock, flags);
226 return value;
227}
228
229static void
230write_utility(void *dev, unsigned long ubus_addr, u8 value)
231{
232 struct idt77252_dev *card = dev;
233 unsigned long flags;
234
235 if (!card) {
236 printk("Error: No such device.\n");
237 return;
238 }
239
240 spin_lock_irqsave(&card->cmd_lock, flags);
241 writel((u32) value, SAR_REG_DR0);
242 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
243 waitfor_idle(card);
244 spin_unlock_irqrestore(&card->cmd_lock, flags);
245}
246
247#ifdef HAVE_EEPROM
248static u32 rdsrtab[] =
249{
250 SAR_GP_EECS | SAR_GP_EESCLK,
251 0,
252 SAR_GP_EESCLK, /* 0 */
253 0,
254 SAR_GP_EESCLK, /* 0 */
255 0,
256 SAR_GP_EESCLK, /* 0 */
257 0,
258 SAR_GP_EESCLK, /* 0 */
259 0,
260 SAR_GP_EESCLK, /* 0 */
261 SAR_GP_EEDO,
262 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
263 0,
264 SAR_GP_EESCLK, /* 0 */
265 SAR_GP_EEDO,
266 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
267};
268
269static u32 wrentab[] =
270{
271 SAR_GP_EECS | SAR_GP_EESCLK,
272 0,
273 SAR_GP_EESCLK, /* 0 */
274 0,
275 SAR_GP_EESCLK, /* 0 */
276 0,
277 SAR_GP_EESCLK, /* 0 */
278 0,
279 SAR_GP_EESCLK, /* 0 */
280 SAR_GP_EEDO,
281 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
282 SAR_GP_EEDO,
283 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
284 0,
285 SAR_GP_EESCLK, /* 0 */
286 0,
287 SAR_GP_EESCLK /* 0 */
288};
289
290static u32 rdtab[] =
291{
292 SAR_GP_EECS | SAR_GP_EESCLK,
293 0,
294 SAR_GP_EESCLK, /* 0 */
295 0,
296 SAR_GP_EESCLK, /* 0 */
297 0,
298 SAR_GP_EESCLK, /* 0 */
299 0,
300 SAR_GP_EESCLK, /* 0 */
301 0,
302 SAR_GP_EESCLK, /* 0 */
303 0,
304 SAR_GP_EESCLK, /* 0 */
305 SAR_GP_EEDO,
306 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
307 SAR_GP_EEDO,
308 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
309};
310
311static u32 wrtab[] =
312{
313 SAR_GP_EECS | SAR_GP_EESCLK,
314 0,
315 SAR_GP_EESCLK, /* 0 */
316 0,
317 SAR_GP_EESCLK, /* 0 */
318 0,
319 SAR_GP_EESCLK, /* 0 */
320 0,
321 SAR_GP_EESCLK, /* 0 */
322 0,
323 SAR_GP_EESCLK, /* 0 */
324 0,
325 SAR_GP_EESCLK, /* 0 */
326 SAR_GP_EEDO,
327 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
328 0,
329 SAR_GP_EESCLK /* 0 */
330};
331
332static u32 clktab[] =
333{
334 0,
335 SAR_GP_EESCLK,
336 0,
337 SAR_GP_EESCLK,
338 0,
339 SAR_GP_EESCLK,
340 0,
341 SAR_GP_EESCLK,
342 0,
343 SAR_GP_EESCLK,
344 0,
345 SAR_GP_EESCLK,
346 0,
347 SAR_GP_EESCLK,
348 0,
349 SAR_GP_EESCLK,
350 0
351};
352
353static u32
354idt77252_read_gp(struct idt77252_dev *card)
355{
356 u32 gp;
357
358 gp = readl(SAR_REG_GP);
359#if 0
360 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
361#endif
362 return gp;
363}
364
365static void
366idt77252_write_gp(struct idt77252_dev *card, u32 value)
367{
368 unsigned long flags;
369
370#if 0
371 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
372 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
373 value & SAR_GP_EEDO ? "1" : "0");
374#endif
375
376 spin_lock_irqsave(&card->cmd_lock, flags);
377 waitfor_idle(card);
378 writel(value, SAR_REG_GP);
379 spin_unlock_irqrestore(&card->cmd_lock, flags);
380}
381
382static u8
383idt77252_eeprom_read_status(struct idt77252_dev *card)
384{
385 u8 byte;
386 u32 gp;
387 int i, j;
388
389 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
390
391 for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) {
392 idt77252_write_gp(card, gp | rdsrtab[i]);
393 udelay(5);
394 }
395 idt77252_write_gp(card, gp | SAR_GP_EECS);
396 udelay(5);
397
398 byte = 0;
399 for (i = 0, j = 0; i < 8; i++) {
400 byte <<= 1;
401
402 idt77252_write_gp(card, gp | clktab[j++]);
403 udelay(5);
404
405 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
406
407 idt77252_write_gp(card, gp | clktab[j++]);
408 udelay(5);
409 }
410 idt77252_write_gp(card, gp | SAR_GP_EECS);
411 udelay(5);
412
413 return byte;
414}
415
416static u8
417idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
418{
419 u8 byte;
420 u32 gp;
421 int i, j;
422
423 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
424
425 for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) {
426 idt77252_write_gp(card, gp | rdtab[i]);
427 udelay(5);
428 }
429 idt77252_write_gp(card, gp | SAR_GP_EECS);
430 udelay(5);
431
432 for (i = 0, j = 0; i < 8; i++) {
433 idt77252_write_gp(card, gp | clktab[j++] |
434 (offset & 1 ? SAR_GP_EEDO : 0));
435 udelay(5);
436
437 idt77252_write_gp(card, gp | clktab[j++] |
438 (offset & 1 ? SAR_GP_EEDO : 0));
439 udelay(5);
440
441 offset >>= 1;
442 }
443 idt77252_write_gp(card, gp | SAR_GP_EECS);
444 udelay(5);
445
446 byte = 0;
447 for (i = 0, j = 0; i < 8; i++) {
448 byte <<= 1;
449
450 idt77252_write_gp(card, gp | clktab[j++]);
451 udelay(5);
452
453 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
454
455 idt77252_write_gp(card, gp | clktab[j++]);
456 udelay(5);
457 }
458 idt77252_write_gp(card, gp | SAR_GP_EECS);
459 udelay(5);
460
461 return byte;
462}
463
464static void
465idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
466{
467 u32 gp;
468 int i, j;
469
470 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
471
472 for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) {
473 idt77252_write_gp(card, gp | wrentab[i]);
474 udelay(5);
475 }
476 idt77252_write_gp(card, gp | SAR_GP_EECS);
477 udelay(5);
478
479 for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) {
480 idt77252_write_gp(card, gp | wrtab[i]);
481 udelay(5);
482 }
483 idt77252_write_gp(card, gp | SAR_GP_EECS);
484 udelay(5);
485
486 for (i = 0, j = 0; i < 8; i++) {
487 idt77252_write_gp(card, gp | clktab[j++] |
488 (offset & 1 ? SAR_GP_EEDO : 0));
489 udelay(5);
490
491 idt77252_write_gp(card, gp | clktab[j++] |
492 (offset & 1 ? SAR_GP_EEDO : 0));
493 udelay(5);
494
495 offset >>= 1;
496 }
497 idt77252_write_gp(card, gp | SAR_GP_EECS);
498 udelay(5);
499
500 for (i = 0, j = 0; i < 8; i++) {
501 idt77252_write_gp(card, gp | clktab[j++] |
502 (data & 1 ? SAR_GP_EEDO : 0));
503 udelay(5);
504
505 idt77252_write_gp(card, gp | clktab[j++] |
506 (data & 1 ? SAR_GP_EEDO : 0));
507 udelay(5);
508
509 data >>= 1;
510 }
511 idt77252_write_gp(card, gp | SAR_GP_EECS);
512 udelay(5);
513}
514
515static void
516idt77252_eeprom_init(struct idt77252_dev *card)
517{
518 u32 gp;
519
520 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
521
522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523 udelay(5);
524 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 udelay(5);
526 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
527 udelay(5);
528 idt77252_write_gp(card, gp | SAR_GP_EECS);
529 udelay(5);
530}
531#endif /* HAVE_EEPROM */
532
533
534#ifdef CONFIG_ATM_IDT77252_DEBUG
535static void
536dump_tct(struct idt77252_dev *card, int index)
537{
538 unsigned long tct;
539 int i;
540
541 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
542
543 printk("%s: TCT %x:", card->name, index);
544 for (i = 0; i < 8; i++) {
545 printk(" %08x", read_sram(card, tct + i));
546 }
547 printk("\n");
548}
549
550static void
551idt77252_tx_dump(struct idt77252_dev *card)
552{
553 struct atm_vcc *vcc;
554 struct vc_map *vc;
555 int i;
556
557 printk("%s\n", __FUNCTION__);
558 for (i = 0; i < card->tct_size; i++) {
559 vc = card->vcs[i];
560 if (!vc)
561 continue;
562
563 vcc = NULL;
564 if (vc->rx_vcc)
565 vcc = vc->rx_vcc;
566 else if (vc->tx_vcc)
567 vcc = vc->tx_vcc;
568
569 if (!vcc)
570 continue;
571
572 printk("%s: Connection %d:\n", card->name, vc->index);
573 dump_tct(card, vc->index);
574 }
575}
576#endif
577
578
579/*****************************************************************************/
580/* */
581/* SCQ Handling */
582/* */
583/*****************************************************************************/
584
585static int
586sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
587{
588 struct sb_pool *pool = &card->sbpool[queue];
589 int index;
590
591 index = pool->index;
592 while (pool->skb[index]) {
593 index = (index + 1) & FBQ_MASK;
594 if (index == pool->index)
595 return -ENOBUFS;
596 }
597
598 pool->skb[index] = skb;
599 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
600
601 pool->index = (index + 1) & FBQ_MASK;
602 return 0;
603}
604
605static void
606sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
607{
608 unsigned int queue, index;
609 u32 handle;
610
611 handle = IDT77252_PRV_POOL(skb);
612
613 queue = POOL_QUEUE(handle);
614 if (queue > 3)
615 return;
616
617 index = POOL_INDEX(handle);
618 if (index > FBQ_SIZE - 1)
619 return;
620
621 card->sbpool[queue].skb[index] = NULL;
622}
623
624static struct sk_buff *
625sb_pool_skb(struct idt77252_dev *card, u32 handle)
626{
627 unsigned int queue, index;
628
629 queue = POOL_QUEUE(handle);
630 if (queue > 3)
631 return NULL;
632
633 index = POOL_INDEX(handle);
634 if (index > FBQ_SIZE - 1)
635 return NULL;
636
637 return card->sbpool[queue].skb[index];
638}
639
640static struct scq_info *
641alloc_scq(struct idt77252_dev *card, int class)
642{
643 struct scq_info *scq;
644
645 scq = (struct scq_info *) kmalloc(sizeof(struct scq_info), GFP_KERNEL);
646 if (!scq)
647 return NULL;
648 memset(scq, 0, sizeof(struct scq_info));
649
650 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
651 &scq->paddr);
652 if (scq->base == NULL) {
653 kfree(scq);
654 return NULL;
655 }
656 memset(scq->base, 0, SCQ_SIZE);
657
658 scq->next = scq->base;
659 scq->last = scq->base + (SCQ_ENTRIES - 1);
660 atomic_set(&scq->used, 0);
661
662 spin_lock_init(&scq->lock);
663 spin_lock_init(&scq->skblock);
664
665 skb_queue_head_init(&scq->transmit);
666 skb_queue_head_init(&scq->pending);
667
668 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
669 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
670
671 return scq;
672}
673
674static void
675free_scq(struct idt77252_dev *card, struct scq_info *scq)
676{
677 struct sk_buff *skb;
678 struct atm_vcc *vcc;
679
680 pci_free_consistent(card->pcidev, SCQ_SIZE,
681 scq->base, scq->paddr);
682
683 while ((skb = skb_dequeue(&scq->transmit))) {
684 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
685 skb->len, PCI_DMA_TODEVICE);
686
687 vcc = ATM_SKB(skb)->vcc;
688 if (vcc->pop)
689 vcc->pop(vcc, skb);
690 else
691 dev_kfree_skb(skb);
692 }
693
694 while ((skb = skb_dequeue(&scq->pending))) {
695 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
696 skb->len, PCI_DMA_TODEVICE);
697
698 vcc = ATM_SKB(skb)->vcc;
699 if (vcc->pop)
700 vcc->pop(vcc, skb);
701 else
702 dev_kfree_skb(skb);
703 }
704
705 kfree(scq);
706}
707
708
709static int
710push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
711{
712 struct scq_info *scq = vc->scq;
713 unsigned long flags;
714 struct scqe *tbd;
715 int entries;
716
717 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
718
719 atomic_inc(&scq->used);
720 entries = atomic_read(&scq->used);
721 if (entries > (SCQ_ENTRIES - 1)) {
722 atomic_dec(&scq->used);
723 goto out;
724 }
725
726 skb_queue_tail(&scq->transmit, skb);
727
728 spin_lock_irqsave(&vc->lock, flags);
729 if (vc->estimator) {
730 struct atm_vcc *vcc = vc->tx_vcc;
731 struct sock *sk = sk_atm(vcc);
732
733 vc->estimator->cells += (skb->len + 47) / 48;
734 if (atomic_read(&sk->sk_wmem_alloc) >
735 (sk->sk_sndbuf >> 1)) {
736 u32 cps = vc->estimator->maxcps;
737
738 vc->estimator->cps = cps;
739 vc->estimator->avcps = cps << 5;
740 if (vc->lacr < vc->init_er) {
741 vc->lacr = vc->init_er;
742 writel(TCMDQ_LACR | (vc->lacr << 16) |
743 vc->index, SAR_REG_TCMDQ);
744 }
745 }
746 }
747 spin_unlock_irqrestore(&vc->lock, flags);
748
749 tbd = &IDT77252_PRV_TBD(skb);
750
751 spin_lock_irqsave(&scq->lock, flags);
752 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
753 SAR_TBD_TSIF | SAR_TBD_GTSI);
754 scq->next->word_2 = cpu_to_le32(tbd->word_2);
755 scq->next->word_3 = cpu_to_le32(tbd->word_3);
756 scq->next->word_4 = cpu_to_le32(tbd->word_4);
757
758 if (scq->next == scq->last)
759 scq->next = scq->base;
760 else
761 scq->next++;
762
763 write_sram(card, scq->scd,
764 scq->paddr +
765 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
766 spin_unlock_irqrestore(&scq->lock, flags);
767
768 scq->trans_start = jiffies;
769
770 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
771 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
772 SAR_REG_TCMDQ);
773 }
774
775 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
776
777 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
778 card->name, atomic_read(&scq->used),
779 read_sram(card, scq->scd + 1), scq->next);
780
781 return 0;
782
783out:
Marcelo Feitoza Parisie1bd2322005-07-19 13:55:14 -0700[diff] [blame]784 if (time_after(jiffies, scq->trans_start + HZ)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]785 printk("%s: Error pushing TBD for %d.%d\n",
786 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
787#ifdef CONFIG_ATM_IDT77252_DEBUG
788 idt77252_tx_dump(card);
789#endif
790 scq->trans_start = jiffies;
791 }
792
793 return -ENOBUFS;
794}
795
796
797static void
798drain_scq(struct idt77252_dev *card, struct vc_map *vc)
799{
800 struct scq_info *scq = vc->scq;
801 struct sk_buff *skb;
802 struct atm_vcc *vcc;
803
804 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
805 card->name, atomic_read(&scq->used), scq->next);
806
807 skb = skb_dequeue(&scq->transmit);
808 if (skb) {
809 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
810
811 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
812 skb->len, PCI_DMA_TODEVICE);
813
814 vcc = ATM_SKB(skb)->vcc;
815
816 if (vcc->pop)
817 vcc->pop(vcc, skb);
818 else
819 dev_kfree_skb(skb);
820
821 atomic_inc(&vcc->stats->tx);
822 }
823
824 atomic_dec(&scq->used);
825
826 spin_lock(&scq->skblock);
827 while ((skb = skb_dequeue(&scq->pending))) {
828 if (push_on_scq(card, vc, skb)) {
829 skb_queue_head(&vc->scq->pending, skb);
830 break;
831 }
832 }
833 spin_unlock(&scq->skblock);
834}
835
836static int
837queue_skb(struct idt77252_dev *card, struct vc_map *vc,
838 struct sk_buff *skb, int oam)
839{
840 struct atm_vcc *vcc;
841 struct scqe *tbd;
842 unsigned long flags;
843 int error;
844 int aal;
845
846 if (skb->len == 0) {
847 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
848 return -EINVAL;
849 }
850
851 TXPRINTK("%s: Sending %d bytes of data.\n",
852 card->name, skb->len);
853
854 tbd = &IDT77252_PRV_TBD(skb);
855 vcc = ATM_SKB(skb)->vcc;
856
857 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
858 skb->len, PCI_DMA_TODEVICE);
859
860 error = -EINVAL;
861
862 if (oam) {
863 if (skb->len != 52)
864 goto errout;
865
866 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
867 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
868 tbd->word_3 = 0x00000000;
869 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
870 (skb->data[2] << 8) | (skb->data[3] << 0);
871
872 if (test_bit(VCF_RSV, &vc->flags))
873 vc = card->vcs[0];
874
875 goto done;
876 }
877
878 if (test_bit(VCF_RSV, &vc->flags)) {
879 printk("%s: Trying to transmit on reserved VC\n", card->name);
880 goto errout;
881 }
882
883 aal = vcc->qos.aal;
884
885 switch (aal) {
886 case ATM_AAL0:
887 case ATM_AAL34:
888 if (skb->len > 52)
889 goto errout;
890
891 if (aal == ATM_AAL0)
892 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
893 ATM_CELL_PAYLOAD;
894 else
895 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
896 ATM_CELL_PAYLOAD;
897
898 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
899 tbd->word_3 = 0x00000000;
900 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
901 (skb->data[2] << 8) | (skb->data[3] << 0);
902 break;
903
904 case ATM_AAL5:
905 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
906 tbd->word_2 = IDT77252_PRV_PADDR(skb);
907 tbd->word_3 = skb->len;
908 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
909 (vcc->vci << SAR_TBD_VCI_SHIFT);
910 break;
911
912 case ATM_AAL1:
913 case ATM_AAL2:
914 default:
915 printk("%s: Traffic type not supported.\n", card->name);
916 error = -EPROTONOSUPPORT;
917 goto errout;
918 }
919
920done:
921 spin_lock_irqsave(&vc->scq->skblock, flags);
922 skb_queue_tail(&vc->scq->pending, skb);
923
924 while ((skb = skb_dequeue(&vc->scq->pending))) {
925 if (push_on_scq(card, vc, skb)) {
926 skb_queue_head(&vc->scq->pending, skb);
927 break;
928 }
929 }
930 spin_unlock_irqrestore(&vc->scq->skblock, flags);
931
932 return 0;
933
934errout:
935 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
936 skb->len, PCI_DMA_TODEVICE);
937 return error;
938}
939
940static unsigned long
941get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
942{
943 int i;
944
945 for (i = 0; i < card->scd_size; i++) {
946 if (!card->scd2vc[i]) {
947 card->scd2vc[i] = vc;
948 vc->scd_index = i;
949 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
950 }
951 }
952 return 0;
953}
954
955static void
956fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
957{
958 write_sram(card, scq->scd, scq->paddr);
959 write_sram(card, scq->scd + 1, 0x00000000);
960 write_sram(card, scq->scd + 2, 0xffffffff);
961 write_sram(card, scq->scd + 3, 0x00000000);
962}
963
964static void
965clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
966{
967 return;
968}
969
970/*****************************************************************************/
971/* */
972/* RSQ Handling */
973/* */
974/*****************************************************************************/
975
976static int
977init_rsq(struct idt77252_dev *card)
978{
979 struct rsq_entry *rsqe;
980
981 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
982 &card->rsq.paddr);
983 if (card->rsq.base == NULL) {
984 printk("%s: can't allocate RSQ.\n", card->name);
985 return -1;
986 }
987 memset(card->rsq.base, 0, RSQSIZE);
988
989 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
990 card->rsq.next = card->rsq.last;
991 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
992 rsqe->word_4 = 0;
993
994 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
995 SAR_REG_RSQH);
996 writel(card->rsq.paddr, SAR_REG_RSQB);
997
998 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
999 (unsigned long) card->rsq.base,
1000 readl(SAR_REG_RSQB));
1001 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1002 card->name,
1003 readl(SAR_REG_RSQH),
1004 readl(SAR_REG_RSQB),
1005 readl(SAR_REG_RSQT));
1006
1007 return 0;
1008}
1009
1010static void
1011deinit_rsq(struct idt77252_dev *card)
1012{
1013 pci_free_consistent(card->pcidev, RSQSIZE,
1014 card->rsq.base, card->rsq.paddr);
1015}
1016
1017static void
1018dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1019{
1020 struct atm_vcc *vcc;
1021 struct sk_buff *skb;
1022 struct rx_pool *rpp;
1023 struct vc_map *vc;
1024 u32 header, vpi, vci;
1025 u32 stat;
1026 int i;
1027
1028 stat = le32_to_cpu(rsqe->word_4);
1029
1030 if (stat & SAR_RSQE_IDLE) {
1031 RXPRINTK("%s: message about inactive connection.\n",
1032 card->name);
1033 return;
1034 }
1035
1036 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1037 if (skb == NULL) {
1038 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1039 card->name, __FUNCTION__,
1040 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1041 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1042 return;
1043 }
1044
1045 header = le32_to_cpu(rsqe->word_1);
1046 vpi = (header >> 16) & 0x00ff;
1047 vci = (header >> 0) & 0xffff;
1048
1049 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1050 card->name, vpi, vci, skb, skb->data);
1051
1052 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1053 printk("%s: SDU received for out-of-range vc %u.%u\n",
1054 card->name, vpi, vci);
1055 recycle_rx_skb(card, skb);
1056 return;
1057 }
1058
1059 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1060 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1061 printk("%s: SDU received on non RX vc %u.%u\n",
1062 card->name, vpi, vci);
1063 recycle_rx_skb(card, skb);
1064 return;
1065 }
1066
1067 vcc = vc->rx_vcc;
1068
1069 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1070 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1071
1072 if ((vcc->qos.aal == ATM_AAL0) ||
1073 (vcc->qos.aal == ATM_AAL34)) {
1074 struct sk_buff *sb;
1075 unsigned char *cell;
1076 u32 aal0;
1077
1078 cell = skb->data;
1079 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1080 if ((sb = dev_alloc_skb(64)) == NULL) {
1081 printk("%s: Can't allocate buffers for aal0.\n",
1082 card->name);
1083 atomic_add(i, &vcc->stats->rx_drop);
1084 break;
1085 }
1086 if (!atm_charge(vcc, sb->truesize)) {
1087 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1088 card->name);
1089 atomic_add(i - 1, &vcc->stats->rx_drop);
1090 dev_kfree_skb(sb);
1091 break;
1092 }
1093 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1094 (vci << ATM_HDR_VCI_SHIFT);
1095 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1096 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1097
1098 *((u32 *) sb->data) = aal0;
1099 skb_put(sb, sizeof(u32));
1100 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1101 cell, ATM_CELL_PAYLOAD);
1102
1103 ATM_SKB(sb)->vcc = vcc;
Patrick McHardya61bbcf2005-08-14 17:24:31 -0700[diff] [blame]1104 __net_timestamp(sb);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1105 vcc->push(vcc, sb);
1106 atomic_inc(&vcc->stats->rx);
1107
1108 cell += ATM_CELL_PAYLOAD;
1109 }
1110
1111 recycle_rx_skb(card, skb);
1112 return;
1113 }
1114 if (vcc->qos.aal != ATM_AAL5) {
1115 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1116 card->name, vcc->qos.aal);
1117 recycle_rx_skb(card, skb);
1118 return;
1119 }
1120 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1121
1122 rpp = &vc->rcv.rx_pool;
1123
1124 rpp->len += skb->len;
1125 if (!rpp->count++)
1126 rpp->first = skb;
1127 *rpp->last = skb;
1128 rpp->last = &skb->next;
1129
1130 if (stat & SAR_RSQE_EPDU) {
1131 unsigned char *l1l2;
1132 unsigned int len;
1133
1134 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1135
1136 len = (l1l2[0] << 8) | l1l2[1];
1137 len = len ? len : 0x10000;
1138
1139 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1140
1141 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1142 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1143 "(CDC: %08x)\n",
1144 card->name, len, rpp->len, readl(SAR_REG_CDC));
1145 recycle_rx_pool_skb(card, rpp);
1146 atomic_inc(&vcc->stats->rx_err);
1147 return;
1148 }
1149 if (stat & SAR_RSQE_CRC) {
1150 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1151 recycle_rx_pool_skb(card, rpp);
1152 atomic_inc(&vcc->stats->rx_err);
1153 return;
1154 }
1155 if (rpp->count > 1) {
1156 struct sk_buff *sb;
1157
1158 skb = dev_alloc_skb(rpp->len);
1159 if (!skb) {
1160 RXPRINTK("%s: Can't alloc RX skb.\n",
1161 card->name);
1162 recycle_rx_pool_skb(card, rpp);
1163 atomic_inc(&vcc->stats->rx_err);
1164 return;
1165 }
1166 if (!atm_charge(vcc, skb->truesize)) {
1167 recycle_rx_pool_skb(card, rpp);
1168 dev_kfree_skb(skb);
1169 return;
1170 }
1171 sb = rpp->first;
1172 for (i = 0; i < rpp->count; i++) {
1173 memcpy(skb_put(skb, sb->len),
1174 sb->data, sb->len);
1175 sb = sb->next;
1176 }
1177
1178 recycle_rx_pool_skb(card, rpp);
1179
1180 skb_trim(skb, len);
1181 ATM_SKB(skb)->vcc = vcc;
Patrick McHardya61bbcf2005-08-14 17:24:31 -0700[diff] [blame]1182 __net_timestamp(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1183
1184 vcc->push(vcc, skb);
1185 atomic_inc(&vcc->stats->rx);
1186
1187 return;
1188 }
1189
1190 skb->next = NULL;
1191 flush_rx_pool(card, rpp);
1192
1193 if (!atm_charge(vcc, skb->truesize)) {
1194 recycle_rx_skb(card, skb);
1195 return;
1196 }
1197
1198 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1199 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1200 sb_pool_remove(card, skb);
1201
1202 skb_trim(skb, len);
1203 ATM_SKB(skb)->vcc = vcc;
Patrick McHardya61bbcf2005-08-14 17:24:31 -0700[diff] [blame]1204 __net_timestamp(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1205
1206 vcc->push(vcc, skb);
1207 atomic_inc(&vcc->stats->rx);
1208
1209 if (skb->truesize > SAR_FB_SIZE_3)
1210 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1211 else if (skb->truesize > SAR_FB_SIZE_2)
1212 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1213 else if (skb->truesize > SAR_FB_SIZE_1)
1214 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1215 else
1216 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1217 return;
1218 }
1219}
1220
1221static void
1222idt77252_rx(struct idt77252_dev *card)
1223{
1224 struct rsq_entry *rsqe;
1225
1226 if (card->rsq.next == card->rsq.last)
1227 rsqe = card->rsq.base;
1228 else
1229 rsqe = card->rsq.next + 1;
1230
1231 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1232 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1233 return;
1234 }
1235
1236 do {
1237 dequeue_rx(card, rsqe);
1238 rsqe->word_4 = 0;
1239 card->rsq.next = rsqe;
1240 if (card->rsq.next == card->rsq.last)
1241 rsqe = card->rsq.base;
1242 else
1243 rsqe = card->rsq.next + 1;
1244 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1245
1246 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1247 SAR_REG_RSQH);
1248}
1249
1250static void
1251idt77252_rx_raw(struct idt77252_dev *card)
1252{
1253 struct sk_buff *queue;
1254 u32 head, tail;
1255 struct atm_vcc *vcc;
1256 struct vc_map *vc;
1257 struct sk_buff *sb;
1258
1259 if (card->raw_cell_head == NULL) {
1260 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1261 card->raw_cell_head = sb_pool_skb(card, handle);
1262 }
1263
1264 queue = card->raw_cell_head;
1265 if (!queue)
1266 return;
1267
1268 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1269 tail = readl(SAR_REG_RAWCT);
1270
1271 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1272 queue->end - queue->head - 16,
1273 PCI_DMA_FROMDEVICE);
1274
1275 while (head != tail) {
1276 unsigned int vpi, vci, pti;
1277 u32 header;
1278
1279 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1280
1281 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1282 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1283 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1284
1285#ifdef CONFIG_ATM_IDT77252_DEBUG
1286 if (debug & DBG_RAW_CELL) {
1287 int i;
1288
1289 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1290 card->name, (header >> 28) & 0x000f,
1291 (header >> 20) & 0x00ff,
1292 (header >> 4) & 0xffff,
1293 (header >> 1) & 0x0007,
1294 (header >> 0) & 0x0001);
1295 for (i = 16; i < 64; i++)
1296 printk(" %02x", queue->data[i]);
1297 printk("\n");
1298 }
1299#endif
1300
1301 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1302 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1303 card->name, vpi, vci);
1304 goto drop;
1305 }
1306
1307 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1308 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1309 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1310 card->name, vpi, vci);
1311 goto drop;
1312 }
1313
1314 vcc = vc->rx_vcc;
1315
1316 if (vcc->qos.aal != ATM_AAL0) {
1317 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1318 card->name, vpi, vci);
1319 atomic_inc(&vcc->stats->rx_drop);
1320 goto drop;
1321 }
1322
1323 if ((sb = dev_alloc_skb(64)) == NULL) {
1324 printk("%s: Can't allocate buffers for AAL0.\n",
1325 card->name);
1326 atomic_inc(&vcc->stats->rx_err);
1327 goto drop;
1328 }
1329
1330 if (!atm_charge(vcc, sb->truesize)) {
1331 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1332 card->name);
1333 dev_kfree_skb(sb);
1334 goto drop;
1335 }
1336
1337 *((u32 *) sb->data) = header;
1338 skb_put(sb, sizeof(u32));
1339 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1340 ATM_CELL_PAYLOAD);
1341
1342 ATM_SKB(sb)->vcc = vcc;
Patrick McHardya61bbcf2005-08-14 17:24:31 -0700[diff] [blame]1343 __net_timestamp(sb);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1344 vcc->push(vcc, sb);
1345 atomic_inc(&vcc->stats->rx);
1346
1347drop:
1348 skb_pull(queue, 64);
1349
1350 head = IDT77252_PRV_PADDR(queue)
1351 + (queue->data - queue->head - 16);
1352
1353 if (queue->len < 128) {
1354 struct sk_buff *next;
1355 u32 handle;
1356
1357 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1358 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1359
1360 next = sb_pool_skb(card, handle);
1361 recycle_rx_skb(card, queue);
1362
1363 if (next) {
1364 card->raw_cell_head = next;
1365 queue = card->raw_cell_head;
1366 pci_dma_sync_single_for_cpu(card->pcidev,
1367 IDT77252_PRV_PADDR(queue),
1368 queue->end - queue->data,
1369 PCI_DMA_FROMDEVICE);
1370 } else {
1371 card->raw_cell_head = NULL;
1372 printk("%s: raw cell queue overrun\n",
1373 card->name);
1374 break;
1375 }
1376 }
1377 }
1378}
1379
1380
1381/*****************************************************************************/
1382/* */
1383/* TSQ Handling */
1384/* */
1385/*****************************************************************************/
1386
1387static int
1388init_tsq(struct idt77252_dev *card)
1389{
1390 struct tsq_entry *tsqe;
1391
1392 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1393 &card->tsq.paddr);
1394 if (card->tsq.base == NULL) {
1395 printk("%s: can't allocate TSQ.\n", card->name);
1396 return -1;
1397 }
1398 memset(card->tsq.base, 0, TSQSIZE);
1399
1400 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1401 card->tsq.next = card->tsq.last;
1402 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1403 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1404
1405 writel(card->tsq.paddr, SAR_REG_TSQB);
1406 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1407 SAR_REG_TSQH);
1408
1409 return 0;
1410}
1411
1412static void
1413deinit_tsq(struct idt77252_dev *card)
1414{
1415 pci_free_consistent(card->pcidev, TSQSIZE,
1416 card->tsq.base, card->tsq.paddr);
1417}
1418
1419static void
1420idt77252_tx(struct idt77252_dev *card)
1421{
1422 struct tsq_entry *tsqe;
1423 unsigned int vpi, vci;
1424 struct vc_map *vc;
1425 u32 conn, stat;
1426
1427 if (card->tsq.next == card->tsq.last)
1428 tsqe = card->tsq.base;
1429 else
1430 tsqe = card->tsq.next + 1;
1431
1432 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1433 card->tsq.base, card->tsq.next, card->tsq.last);
1434 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1435 readl(SAR_REG_TSQB),
1436 readl(SAR_REG_TSQT),
1437 readl(SAR_REG_TSQH));
1438
1439 stat = le32_to_cpu(tsqe->word_2);
1440
1441 if (stat & SAR_TSQE_INVALID)
1442 return;
1443
1444 do {
1445 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1446 le32_to_cpu(tsqe->word_1),
1447 le32_to_cpu(tsqe->word_2));
1448
1449 switch (stat & SAR_TSQE_TYPE) {
1450 case SAR_TSQE_TYPE_TIMER:
1451 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1452 break;
1453
1454 case SAR_TSQE_TYPE_IDLE:
1455
1456 conn = le32_to_cpu(tsqe->word_1);
1457
1458 if (SAR_TSQE_TAG(stat) == 0x10) {
1459#ifdef NOTDEF
1460 printk("%s: Connection %d halted.\n",
1461 card->name,
1462 le32_to_cpu(tsqe->word_1) & 0x1fff);
1463#endif
1464 break;
1465 }
1466
1467 vc = card->vcs[conn & 0x1fff];
1468 if (!vc) {
1469 printk("%s: could not find VC from conn %d\n",
1470 card->name, conn & 0x1fff);
1471 break;
1472 }
1473
1474 printk("%s: Connection %d IDLE.\n",
1475 card->name, vc->index);
1476
1477 set_bit(VCF_IDLE, &vc->flags);
1478 break;
1479
1480 case SAR_TSQE_TYPE_TSR:
1481
1482 conn = le32_to_cpu(tsqe->word_1);
1483
1484 vc = card->vcs[conn & 0x1fff];
1485 if (!vc) {
1486 printk("%s: no VC at index %d\n",
1487 card->name,
1488 le32_to_cpu(tsqe->word_1) & 0x1fff);
1489 break;
1490 }
1491
1492 drain_scq(card, vc);
1493 break;
1494
1495 case SAR_TSQE_TYPE_TBD_COMP:
1496
1497 conn = le32_to_cpu(tsqe->word_1);
1498
1499 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1500 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1501
1502 if (vpi >= (1 << card->vpibits) ||
1503 vci >= (1 << card->vcibits)) {
1504 printk("%s: TBD complete: "
1505 "out of range VPI.VCI %u.%u\n",
1506 card->name, vpi, vci);
1507 break;
1508 }
1509
1510 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1511 if (!vc) {
1512 printk("%s: TBD complete: "
1513 "no VC at VPI.VCI %u.%u\n",
1514 card->name, vpi, vci);
1515 break;
1516 }
1517
1518 drain_scq(card, vc);
1519 break;
1520 }
1521
1522 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1523
1524 card->tsq.next = tsqe;
1525 if (card->tsq.next == card->tsq.last)
1526 tsqe = card->tsq.base;
1527 else
1528 tsqe = card->tsq.next + 1;
1529
1530 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1531 card->tsq.base, card->tsq.next, card->tsq.last);
1532
1533 stat = le32_to_cpu(tsqe->word_2);
1534
1535 } while (!(stat & SAR_TSQE_INVALID));
1536
1537 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1538 SAR_REG_TSQH);
1539
1540 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1541 card->index, readl(SAR_REG_TSQH),
1542 readl(SAR_REG_TSQT), card->tsq.next);
1543}
1544
1545
1546static void
1547tst_timer(unsigned long data)
1548{
1549 struct idt77252_dev *card = (struct idt77252_dev *)data;
1550 unsigned long base, idle, jump;
1551 unsigned long flags;
1552 u32 pc;
1553 int e;
1554
1555 spin_lock_irqsave(&card->tst_lock, flags);
1556
1557 base = card->tst[card->tst_index];
1558 idle = card->tst[card->tst_index ^ 1];
1559
1560 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1561 jump = base + card->tst_size - 2;
1562
1563 pc = readl(SAR_REG_NOW) >> 2;
1564 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1565 mod_timer(&card->tst_timer, jiffies + 1);
1566 goto out;
1567 }
1568
1569 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1570
1571 card->tst_index ^= 1;
1572 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1573
1574 base = card->tst[card->tst_index];
1575 idle = card->tst[card->tst_index ^ 1];
1576
1577 for (e = 0; e < card->tst_size - 2; e++) {
1578 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1579 write_sram(card, idle + e,
1580 card->soft_tst[e].tste & TSTE_MASK);
1581 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1582 }
1583 }
1584 }
1585
1586 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1587
1588 for (e = 0; e < card->tst_size - 2; e++) {
1589 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1590 write_sram(card, idle + e,
1591 card->soft_tst[e].tste & TSTE_MASK);
1592 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1593 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1594 }
1595 }
1596
1597 jump = base + card->tst_size - 2;
1598
1599 write_sram(card, jump, TSTE_OPC_NULL);
1600 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1601
1602 mod_timer(&card->tst_timer, jiffies + 1);
1603 }
1604
1605out:
1606 spin_unlock_irqrestore(&card->tst_lock, flags);
1607}
1608
1609static int
1610__fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1611 int n, unsigned int opc)
1612{
1613 unsigned long cl, avail;
1614 unsigned long idle;
1615 int e, r;
1616 u32 data;
1617
1618 avail = card->tst_size - 2;
1619 for (e = 0; e < avail; e++) {
1620 if (card->soft_tst[e].vc == NULL)
1621 break;
1622 }
1623 if (e >= avail) {
1624 printk("%s: No free TST entries found\n", card->name);
1625 return -1;
1626 }
1627
1628 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1629 card->name, vc ? vc->index : -1, e);
1630
1631 r = n;
1632 cl = avail;
1633 data = opc & TSTE_OPC_MASK;
1634 if (vc && (opc != TSTE_OPC_NULL))
1635 data = opc | vc->index;
1636
1637 idle = card->tst[card->tst_index ^ 1];
1638
1639 /*
1640 * Fill Soft TST.
1641 */
1642 while (r > 0) {
1643 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1644 if (vc)
1645 card->soft_tst[e].vc = vc;
1646 else
1647 card->soft_tst[e].vc = (void *)-1;
1648
1649 card->soft_tst[e].tste = data;
1650 if (timer_pending(&card->tst_timer))
1651 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1652 else {
1653 write_sram(card, idle + e, data);
1654 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1655 }
1656
1657 cl -= card->tst_size;
1658 r--;
1659 }
1660
1661 if (++e == avail)
1662 e = 0;
1663 cl += n;
1664 }
1665
1666 return 0;
1667}
1668
1669static int
1670fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1671{
1672 unsigned long flags;
1673 int res;
1674
1675 spin_lock_irqsave(&card->tst_lock, flags);
1676
1677 res = __fill_tst(card, vc, n, opc);
1678
1679 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1680 if (!timer_pending(&card->tst_timer))
1681 mod_timer(&card->tst_timer, jiffies + 1);
1682
1683 spin_unlock_irqrestore(&card->tst_lock, flags);
1684 return res;
1685}
1686
1687static int
1688__clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1689{
1690 unsigned long idle;
1691 int e;
1692
1693 idle = card->tst[card->tst_index ^ 1];
1694
1695 for (e = 0; e < card->tst_size - 2; e++) {
1696 if (card->soft_tst[e].vc == vc) {
1697 card->soft_tst[e].vc = NULL;
1698
1699 card->soft_tst[e].tste = TSTE_OPC_VAR;
1700 if (timer_pending(&card->tst_timer))
1701 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1702 else {
1703 write_sram(card, idle + e, TSTE_OPC_VAR);
1704 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1705 }
1706 }
1707 }
1708
1709 return 0;
1710}
1711
1712static int
1713clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1714{
1715 unsigned long flags;
1716 int res;
1717
1718 spin_lock_irqsave(&card->tst_lock, flags);
1719
1720 res = __clear_tst(card, vc);
1721
1722 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1723 if (!timer_pending(&card->tst_timer))
1724 mod_timer(&card->tst_timer, jiffies + 1);
1725
1726 spin_unlock_irqrestore(&card->tst_lock, flags);
1727 return res;
1728}
1729
1730static int
1731change_tst(struct idt77252_dev *card, struct vc_map *vc,
1732 int n, unsigned int opc)
1733{
1734 unsigned long flags;
1735 int res;
1736
1737 spin_lock_irqsave(&card->tst_lock, flags);
1738
1739 __clear_tst(card, vc);
1740 res = __fill_tst(card, vc, n, opc);
1741
1742 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1743 if (!timer_pending(&card->tst_timer))
1744 mod_timer(&card->tst_timer, jiffies + 1);
1745
1746 spin_unlock_irqrestore(&card->tst_lock, flags);
1747 return res;
1748}
1749
1750
1751static int
1752set_tct(struct idt77252_dev *card, struct vc_map *vc)
1753{
1754 unsigned long tct;
1755
1756 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1757
1758 switch (vc->class) {
1759 case SCHED_CBR:
1760 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1761 card->name, tct, vc->scq->scd);
1762
1763 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1764 write_sram(card, tct + 1, 0);
1765 write_sram(card, tct + 2, 0);
1766 write_sram(card, tct + 3, 0);
1767 write_sram(card, tct + 4, 0);
1768 write_sram(card, tct + 5, 0);
1769 write_sram(card, tct + 6, 0);
1770 write_sram(card, tct + 7, 0);
1771 break;
1772
1773 case SCHED_UBR:
1774 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1775 card->name, tct, vc->scq->scd);
1776
1777 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1778 write_sram(card, tct + 1, 0);
1779 write_sram(card, tct + 2, TCT_TSIF);
1780 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1781 write_sram(card, tct + 4, 0);
1782 write_sram(card, tct + 5, vc->init_er);
1783 write_sram(card, tct + 6, 0);
1784 write_sram(card, tct + 7, TCT_FLAG_UBR);
1785 break;
1786
1787 case SCHED_VBR:
1788 case SCHED_ABR:
1789 default:
1790 return -ENOSYS;
1791 }
1792
1793 return 0;
1794}
1795
1796/*****************************************************************************/
1797/* */
1798/* FBQ Handling */
1799/* */
1800/*****************************************************************************/
1801
1802static __inline__ int
1803idt77252_fbq_level(struct idt77252_dev *card, int queue)
1804{
1805 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1806}
1807
1808static __inline__ int
1809idt77252_fbq_full(struct idt77252_dev *card, int queue)
1810{
1811 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1812}
1813
1814static int
1815push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1816{
1817 unsigned long flags;
1818 u32 handle;
1819 u32 addr;
1820
1821 skb->data = skb->tail = skb->head;
1822 skb->len = 0;
1823
1824 skb_reserve(skb, 16);
1825
1826 switch (queue) {
1827 case 0:
1828 skb_put(skb, SAR_FB_SIZE_0);
1829 break;
1830 case 1:
1831 skb_put(skb, SAR_FB_SIZE_1);
1832 break;
1833 case 2:
1834 skb_put(skb, SAR_FB_SIZE_2);
1835 break;
1836 case 3:
1837 skb_put(skb, SAR_FB_SIZE_3);
1838 break;
1839 default:
1840 dev_kfree_skb(skb);
1841 return -1;
1842 }
1843
1844 if (idt77252_fbq_full(card, queue))
1845 return -1;
1846
1847 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1848
1849 handle = IDT77252_PRV_POOL(skb);
1850 addr = IDT77252_PRV_PADDR(skb);
1851
1852 spin_lock_irqsave(&card->cmd_lock, flags);
1853 writel(handle, card->fbq[queue]);
1854 writel(addr, card->fbq[queue]);
1855 spin_unlock_irqrestore(&card->cmd_lock, flags);
1856
1857 return 0;
1858}
1859
1860static void
1861add_rx_skb(struct idt77252_dev *card, int queue,
1862 unsigned int size, unsigned int count)
1863{
1864 struct sk_buff *skb;
1865 dma_addr_t paddr;
1866 u32 handle;
1867
1868 while (count--) {
1869 skb = dev_alloc_skb(size);
1870 if (!skb)
1871 return;
1872
1873 if (sb_pool_add(card, skb, queue)) {
1874 printk("%s: SB POOL full\n", __FUNCTION__);
1875 goto outfree;
1876 }
1877
1878 paddr = pci_map_single(card->pcidev, skb->data,
1879 skb->end - skb->data,
1880 PCI_DMA_FROMDEVICE);
1881 IDT77252_PRV_PADDR(skb) = paddr;
1882
1883 if (push_rx_skb(card, skb, queue)) {
1884 printk("%s: FB QUEUE full\n", __FUNCTION__);
1885 goto outunmap;
1886 }
1887 }
1888
1889 return;
1890
1891outunmap:
1892 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1893 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1894
1895 handle = IDT77252_PRV_POOL(skb);
1896 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1897
1898outfree:
1899 dev_kfree_skb(skb);
1900}
1901
1902
1903static void
1904recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1905{
1906 u32 handle = IDT77252_PRV_POOL(skb);
1907 int err;
1908
1909 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1910 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1911
1912 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1913 if (err) {
1914 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1915 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1916 sb_pool_remove(card, skb);
1917 dev_kfree_skb(skb);
1918 }
1919}
1920
1921static void
1922flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1923{
1924 rpp->len = 0;
1925 rpp->count = 0;
1926 rpp->first = NULL;
1927 rpp->last = &rpp->first;
1928}
1929
1930static void
1931recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1932{
1933 struct sk_buff *skb, *next;
1934 int i;
1935
1936 skb = rpp->first;
1937 for (i = 0; i < rpp->count; i++) {
1938 next = skb->next;
1939 skb->next = NULL;
1940 recycle_rx_skb(card, skb);
1941 skb = next;
1942 }
1943 flush_rx_pool(card, rpp);
1944}
1945
1946/*****************************************************************************/
1947/* */
1948/* ATM Interface */
1949/* */
1950/*****************************************************************************/
1951
1952static void
1953idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1954{
1955 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1956}
1957
1958static unsigned char
1959idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1960{
1961 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1962}
1963
1964static inline int
1965idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1966{
1967 struct atm_dev *dev = vcc->dev;
1968 struct idt77252_dev *card = dev->dev_data;
1969 struct vc_map *vc = vcc->dev_data;
1970 int err;
1971
1972 if (vc == NULL) {
1973 printk("%s: NULL connection in send().\n", card->name);
1974 atomic_inc(&vcc->stats->tx_err);
1975 dev_kfree_skb(skb);
1976 return -EINVAL;
1977 }
1978 if (!test_bit(VCF_TX, &vc->flags)) {
1979 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1980 atomic_inc(&vcc->stats->tx_err);
1981 dev_kfree_skb(skb);
1982 return -EINVAL;
1983 }
1984
1985 switch (vcc->qos.aal) {
1986 case ATM_AAL0:
1987 case ATM_AAL1:
1988 case ATM_AAL5:
1989 break;
1990 default:
1991 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1992 atomic_inc(&vcc->stats->tx_err);
1993 dev_kfree_skb(skb);
1994 return -EINVAL;
1995 }
1996
1997 if (skb_shinfo(skb)->nr_frags != 0) {
1998 printk("%s: No scatter-gather yet.\n", card->name);
1999 atomic_inc(&vcc->stats->tx_err);
2000 dev_kfree_skb(skb);
2001 return -EINVAL;
2002 }
2003 ATM_SKB(skb)->vcc = vcc;
2004
2005 err = queue_skb(card, vc, skb, oam);
2006 if (err) {
2007 atomic_inc(&vcc->stats->tx_err);
2008 dev_kfree_skb(skb);
2009 return err;
2010 }
2011
2012 return 0;
2013}
2014
2015int
2016idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2017{
2018 return idt77252_send_skb(vcc, skb, 0);
2019}
2020
2021static int
2022idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2023{
2024 struct atm_dev *dev = vcc->dev;
2025 struct idt77252_dev *card = dev->dev_data;
2026 struct sk_buff *skb;
2027
2028 skb = dev_alloc_skb(64);
2029 if (!skb) {
2030 printk("%s: Out of memory in send_oam().\n", card->name);
2031 atomic_inc(&vcc->stats->tx_err);
2032 return -ENOMEM;
2033 }
2034 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2035
2036 memcpy(skb_put(skb, 52), cell, 52);
2037
2038 return idt77252_send_skb(vcc, skb, 1);
2039}
2040
2041static __inline__ unsigned int
2042idt77252_fls(unsigned int x)
2043{
2044 int r = 1;
2045
2046 if (x == 0)
2047 return 0;
2048 if (x & 0xffff0000) {
2049 x >>= 16;
2050 r += 16;
2051 }
2052 if (x & 0xff00) {
2053 x >>= 8;
2054 r += 8;
2055 }
2056 if (x & 0xf0) {
2057 x >>= 4;
2058 r += 4;
2059 }
2060 if (x & 0xc) {
2061 x >>= 2;
2062 r += 2;
2063 }
2064 if (x & 0x2)
2065 r += 1;
2066 return r;
2067}
2068
2069static u16
2070idt77252_int_to_atmfp(unsigned int rate)
2071{
2072 u16 m, e;
2073
2074 if (rate == 0)
2075 return 0;
2076 e = idt77252_fls(rate) - 1;
2077 if (e < 9)
2078 m = (rate - (1 << e)) << (9 - e);
2079 else if (e == 9)
2080 m = (rate - (1 << e));
2081 else /* e > 9 */
2082 m = (rate - (1 << e)) >> (e - 9);
2083 return 0x4000 | (e << 9) | m;
2084}
2085
2086static u8
2087idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2088{
2089 u16 afp;
2090
2091 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2092 if (pcr < 0)
2093 return rate_to_log[(afp >> 5) & 0x1ff];
2094 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2095}
2096
2097static void
2098idt77252_est_timer(unsigned long data)
2099{
2100 struct vc_map *vc = (struct vc_map *)data;
2101 struct idt77252_dev *card = vc->card;
2102 struct rate_estimator *est;
2103 unsigned long flags;
2104 u32 rate, cps;
2105 u64 ncells;
2106 u8 lacr;
2107
2108 spin_lock_irqsave(&vc->lock, flags);
2109 est = vc->estimator;
2110 if (!est)
2111 goto out;
2112
2113 ncells = est->cells;
2114
2115 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2116 est->last_cells = ncells;
2117 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2118 est->cps = (est->avcps + 0x1f) >> 5;
2119
2120 cps = est->cps;
2121 if (cps < (est->maxcps >> 4))
2122 cps = est->maxcps >> 4;
2123
2124 lacr = idt77252_rate_logindex(card, cps);
2125 if (lacr > vc->max_er)
2126 lacr = vc->max_er;
2127
2128 if (lacr != vc->lacr) {
2129 vc->lacr = lacr;
2130 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2131 }
2132
2133 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2134 add_timer(&est->timer);
2135
2136out:
2137 spin_unlock_irqrestore(&vc->lock, flags);
2138}
2139
2140static struct rate_estimator *
2141idt77252_init_est(struct vc_map *vc, int pcr)
2142{
2143 struct rate_estimator *est;
2144
2145 est = kmalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2146 if (!est)
2147 return NULL;
2148 memset(est, 0, sizeof(*est));
2149
2150 est->maxcps = pcr < 0 ? -pcr : pcr;
2151 est->cps = est->maxcps;
2152 est->avcps = est->cps << 5;
2153
2154 est->interval = 2; /* XXX: make this configurable */
2155 est->ewma_log = 2; /* XXX: make this configurable */
2156 init_timer(&est->timer);
2157 est->timer.data = (unsigned long)vc;
2158 est->timer.function = idt77252_est_timer;
2159
2160 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2161 add_timer(&est->timer);
2162
2163 return est;
2164}
2165
2166static int
2167idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2168 struct atm_vcc *vcc, struct atm_qos *qos)
2169{
2170 int tst_free, tst_used, tst_entries;
2171 unsigned long tmpl, modl;
2172 int tcr, tcra;
2173
2174 if ((qos->txtp.max_pcr == 0) &&
2175 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2176 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2177 card->name);
2178 return -EINVAL;
2179 }
2180
2181 tst_used = 0;
2182 tst_free = card->tst_free;
2183 if (test_bit(VCF_TX, &vc->flags))
2184 tst_used = vc->ntste;
2185 tst_free += tst_used;
2186
2187 tcr = atm_pcr_goal(&qos->txtp);
2188 tcra = tcr >= 0 ? tcr : -tcr;
2189
2190 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2191
2192 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2193 modl = tmpl % (unsigned long)card->utopia_pcr;
2194
2195 tst_entries = (int) (tmpl / card->utopia_pcr);
2196 if (tcr > 0) {
2197 if (modl > 0)
2198 tst_entries++;
2199 } else if (tcr == 0) {
2200 tst_entries = tst_free - SAR_TST_RESERVED;
2201 if (tst_entries <= 0) {
2202 printk("%s: no CBR bandwidth free.\n", card->name);
2203 return -ENOSR;
2204 }
2205 }
2206
2207 if (tst_entries == 0) {
2208 printk("%s: selected CBR bandwidth < granularity.\n",
2209 card->name);
2210 return -EINVAL;
2211 }
2212
2213 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2214 printk("%s: not enough CBR bandwidth free.\n", card->name);
2215 return -ENOSR;
2216 }
2217
2218 vc->ntste = tst_entries;
2219
2220 card->tst_free = tst_free - tst_entries;
2221 if (test_bit(VCF_TX, &vc->flags)) {
2222 if (tst_used == tst_entries)
2223 return 0;
2224
2225 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2226 card->name, tst_used, tst_entries);
2227 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2228 return 0;
2229 }
2230
2231 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2232 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2233 return 0;
2234}
2235
2236static int
2237idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2238 struct atm_vcc *vcc, struct atm_qos *qos)
2239{
2240 unsigned long flags;
2241 int tcr;
2242
2243 spin_lock_irqsave(&vc->lock, flags);
2244 if (vc->estimator) {
2245 del_timer(&vc->estimator->timer);
2246 kfree(vc->estimator);
2247 vc->estimator = NULL;
2248 }
2249 spin_unlock_irqrestore(&vc->lock, flags);
2250
2251 tcr = atm_pcr_goal(&qos->txtp);
2252 if (tcr == 0)
2253 tcr = card->link_pcr;
2254
2255 vc->estimator = idt77252_init_est(vc, tcr);
2256
2257 vc->class = SCHED_UBR;
2258 vc->init_er = idt77252_rate_logindex(card, tcr);
2259 vc->lacr = vc->init_er;
2260 if (tcr < 0)
2261 vc->max_er = vc->init_er;
2262 else
2263 vc->max_er = 0xff;
2264
2265 return 0;
2266}
2267
2268static int
2269idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2270 struct atm_vcc *vcc, struct atm_qos *qos)
2271{
2272 int error;
2273
2274 if (test_bit(VCF_TX, &vc->flags))
2275 return -EBUSY;
2276
2277 switch (qos->txtp.traffic_class) {
2278 case ATM_CBR:
2279 vc->class = SCHED_CBR;
2280 break;
2281
2282 case ATM_UBR:
2283 vc->class = SCHED_UBR;
2284 break;
2285
2286 case ATM_VBR:
2287 case ATM_ABR:
2288 default:
2289 return -EPROTONOSUPPORT;
2290 }
2291
2292 vc->scq = alloc_scq(card, vc->class);
2293 if (!vc->scq) {
2294 printk("%s: can't get SCQ.\n", card->name);
2295 return -ENOMEM;
2296 }
2297
2298 vc->scq->scd = get_free_scd(card, vc);
2299 if (vc->scq->scd == 0) {
2300 printk("%s: no SCD available.\n", card->name);
2301 free_scq(card, vc->scq);
2302 return -ENOMEM;
2303 }
2304
2305 fill_scd(card, vc->scq, vc->class);
2306
2307 if (set_tct(card, vc)) {
2308 printk("%s: class %d not supported.\n",
2309 card->name, qos->txtp.traffic_class);
2310
2311 card->scd2vc[vc->scd_index] = NULL;
2312 free_scq(card, vc->scq);
2313 return -EPROTONOSUPPORT;
2314 }
2315
2316 switch (vc->class) {
2317 case SCHED_CBR:
2318 error = idt77252_init_cbr(card, vc, vcc, qos);
2319 if (error) {
2320 card->scd2vc[vc->scd_index] = NULL;
2321 free_scq(card, vc->scq);
2322 return error;
2323 }
2324
2325 clear_bit(VCF_IDLE, &vc->flags);
2326 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2327 break;
2328
2329 case SCHED_UBR:
2330 error = idt77252_init_ubr(card, vc, vcc, qos);
2331 if (error) {
2332 card->scd2vc[vc->scd_index] = NULL;
2333 free_scq(card, vc->scq);
2334 return error;
2335 }
2336
2337 set_bit(VCF_IDLE, &vc->flags);
2338 break;
2339 }
2340
2341 vc->tx_vcc = vcc;
2342 set_bit(VCF_TX, &vc->flags);
2343 return 0;
2344}
2345
2346static int
2347idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2348 struct atm_vcc *vcc, struct atm_qos *qos)
2349{
2350 unsigned long flags;
2351 unsigned long addr;
2352 u32 rcte = 0;
2353
2354 if (test_bit(VCF_RX, &vc->flags))
2355 return -EBUSY;
2356
2357 vc->rx_vcc = vcc;
2358 set_bit(VCF_RX, &vc->flags);
2359
2360 if ((vcc->vci == 3) || (vcc->vci == 4))
2361 return 0;
2362
2363 flush_rx_pool(card, &vc->rcv.rx_pool);
2364
2365 rcte |= SAR_RCTE_CONNECTOPEN;
2366 rcte |= SAR_RCTE_RAWCELLINTEN;
2367
2368 switch (qos->aal) {
2369 case ATM_AAL0:
2370 rcte |= SAR_RCTE_RCQ;
2371 break;
2372 case ATM_AAL1:
2373 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2374 break;
2375 case ATM_AAL34:
2376 rcte |= SAR_RCTE_AAL34;
2377 break;
2378 case ATM_AAL5:
2379 rcte |= SAR_RCTE_AAL5;
2380 break;
2381 default:
2382 rcte |= SAR_RCTE_RCQ;
2383 break;
2384 }
2385
2386 if (qos->aal != ATM_AAL5)
2387 rcte |= SAR_RCTE_FBP_1;
2388 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2389 rcte |= SAR_RCTE_FBP_3;
2390 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2391 rcte |= SAR_RCTE_FBP_2;
2392 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2393 rcte |= SAR_RCTE_FBP_1;
2394 else
2395 rcte |= SAR_RCTE_FBP_01;
2396
2397 addr = card->rct_base + (vc->index << 2);
2398
2399 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2400 write_sram(card, addr, rcte);
2401
2402 spin_lock_irqsave(&card->cmd_lock, flags);
2403 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2404 waitfor_idle(card);
2405 spin_unlock_irqrestore(&card->cmd_lock, flags);
2406
2407 return 0;
2408}
2409
2410static int
2411idt77252_open(struct atm_vcc *vcc)
2412{
2413 struct atm_dev *dev = vcc->dev;
2414 struct idt77252_dev *card = dev->dev_data;
2415 struct vc_map *vc;
2416 unsigned int index;
2417 unsigned int inuse;
2418 int error;
2419 int vci = vcc->vci;
2420 short vpi = vcc->vpi;
2421
2422 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2423 return 0;
2424
2425 if (vpi >= (1 << card->vpibits)) {
2426 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2427 return -EINVAL;
2428 }
2429
2430 if (vci >= (1 << card->vcibits)) {
2431 printk("%s: unsupported VCI: %d\n", card->name, vci);
2432 return -EINVAL;
2433 }
2434
2435 set_bit(ATM_VF_ADDR, &vcc->flags);
2436
2437 down(&card->mutex);
2438
2439 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2440
2441 switch (vcc->qos.aal) {
2442 case ATM_AAL0:
2443 case ATM_AAL1:
2444 case ATM_AAL5:
2445 break;
2446 default:
2447 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2448 up(&card->mutex);
2449 return -EPROTONOSUPPORT;
2450 }
2451
2452 index = VPCI2VC(card, vpi, vci);
2453 if (!card->vcs[index]) {
2454 card->vcs[index] = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2455 if (!card->vcs[index]) {
2456 printk("%s: can't alloc vc in open()\n", card->name);
2457 up(&card->mutex);
2458 return -ENOMEM;
2459 }
2460 memset(card->vcs[index], 0, sizeof(struct vc_map));
2461
2462 card->vcs[index]->card = card;
2463 card->vcs[index]->index = index;
2464
2465 spin_lock_init(&card->vcs[index]->lock);
2466 }
2467 vc = card->vcs[index];
2468
2469 vcc->dev_data = vc;
2470
2471 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2472 card->name, vc->index, vcc->vpi, vcc->vci,
2473 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2474 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2475 vcc->qos.rxtp.max_sdu);
2476
2477 inuse = 0;
2478 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2479 test_bit(VCF_TX, &vc->flags))
2480 inuse = 1;
2481 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2482 test_bit(VCF_RX, &vc->flags))
2483 inuse += 2;
2484
2485 if (inuse) {
2486 printk("%s: %s vci already in use.\n", card->name,
2487 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2488 up(&card->mutex);
2489 return -EADDRINUSE;
2490 }
2491
2492 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2493 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2494 if (error) {
2495 up(&card->mutex);
2496 return error;
2497 }
2498 }
2499
2500 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2501 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2502 if (error) {
2503 up(&card->mutex);
2504 return error;
2505 }
2506 }
2507
2508 set_bit(ATM_VF_READY, &vcc->flags);
2509
2510 up(&card->mutex);
2511 return 0;
2512}
2513
2514static void
2515idt77252_close(struct atm_vcc *vcc)
2516{
2517 struct atm_dev *dev = vcc->dev;
2518 struct idt77252_dev *card = dev->dev_data;
2519 struct vc_map *vc = vcc->dev_data;
2520 unsigned long flags;
2521 unsigned long addr;
2522 unsigned long timeout;
2523
2524 down(&card->mutex);
2525
2526 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2527 card->name, vc->index, vcc->vpi, vcc->vci);
2528
2529 clear_bit(ATM_VF_READY, &vcc->flags);
2530
2531 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2532
2533 spin_lock_irqsave(&vc->lock, flags);
2534 clear_bit(VCF_RX, &vc->flags);
2535 vc->rx_vcc = NULL;
2536 spin_unlock_irqrestore(&vc->lock, flags);
2537
2538 if ((vcc->vci == 3) || (vcc->vci == 4))
2539 goto done;
2540
2541 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2542
2543 spin_lock_irqsave(&card->cmd_lock, flags);
2544 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2545 waitfor_idle(card);
2546 spin_unlock_irqrestore(&card->cmd_lock, flags);
2547
2548 if (vc->rcv.rx_pool.count) {
2549 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2550 card->name);
2551
2552 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2553 }
2554 }
2555
2556done:
2557 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2558
2559 spin_lock_irqsave(&vc->lock, flags);
2560 clear_bit(VCF_TX, &vc->flags);
2561 clear_bit(VCF_IDLE, &vc->flags);
2562 clear_bit(VCF_RSV, &vc->flags);
2563 vc->tx_vcc = NULL;
2564
2565 if (vc->estimator) {
2566 del_timer(&vc->estimator->timer);
2567 kfree(vc->estimator);
2568 vc->estimator = NULL;
2569 }
2570 spin_unlock_irqrestore(&vc->lock, flags);
2571
2572 timeout = 5 * 1000;
2573 while (atomic_read(&vc->scq->used) > 0) {
2574 timeout = msleep_interruptible(timeout);
2575 if (!timeout)
2576 break;
2577 }
2578 if (!timeout)
2579 printk("%s: SCQ drain timeout: %u used\n",
2580 card->name, atomic_read(&vc->scq->used));
2581
2582 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2583 clear_scd(card, vc->scq, vc->class);
2584
2585 if (vc->class == SCHED_CBR) {
2586 clear_tst(card, vc);
2587 card->tst_free += vc->ntste;
2588 vc->ntste = 0;
2589 }
2590
2591 card->scd2vc[vc->scd_index] = NULL;
2592 free_scq(card, vc->scq);
2593 }
2594
2595 up(&card->mutex);
2596}
2597
2598static int
2599idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2600{
2601 struct atm_dev *dev = vcc->dev;
2602 struct idt77252_dev *card = dev->dev_data;
2603 struct vc_map *vc = vcc->dev_data;
2604 int error = 0;
2605
2606 down(&card->mutex);
2607
2608 if (qos->txtp.traffic_class != ATM_NONE) {
2609 if (!test_bit(VCF_TX, &vc->flags)) {
2610 error = idt77252_init_tx(card, vc, vcc, qos);
2611 if (error)
2612 goto out;
2613 } else {
2614 switch (qos->txtp.traffic_class) {
2615 case ATM_CBR:
2616 error = idt77252_init_cbr(card, vc, vcc, qos);
2617 if (error)
2618 goto out;
2619 break;
2620
2621 case ATM_UBR:
2622 error = idt77252_init_ubr(card, vc, vcc, qos);
2623 if (error)
2624 goto out;
2625
2626 if (!test_bit(VCF_IDLE, &vc->flags)) {
2627 writel(TCMDQ_LACR | (vc->lacr << 16) |
2628 vc->index, SAR_REG_TCMDQ);
2629 }
2630 break;
2631
2632 case ATM_VBR:
2633 case ATM_ABR:
2634 error = -EOPNOTSUPP;
2635 goto out;
2636 }
2637 }
2638 }
2639
2640 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2641 !test_bit(VCF_RX, &vc->flags)) {
2642 error = idt77252_init_rx(card, vc, vcc, qos);
2643 if (error)
2644 goto out;
2645 }
2646
2647 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2648
2649 set_bit(ATM_VF_HASQOS, &vcc->flags);
2650
2651out:
2652 up(&card->mutex);
2653 return error;
2654}
2655
2656static int
2657idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2658{
2659 struct idt77252_dev *card = dev->dev_data;
2660 int i, left;
2661
2662 left = (int) *pos;
2663 if (!left--)
2664 return sprintf(page, "IDT77252 Interrupts:\n");
2665 if (!left--)
2666 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2667 if (!left--)
2668 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2669 if (!left--)
2670 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2671 if (!left--)
2672 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2673 if (!left--)
2674 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2675 if (!left--)
2676 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2677 if (!left--)
2678 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2679 if (!left--)
2680 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2681 if (!left--)
2682 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2683 if (!left--)
2684 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2685 if (!left--)
2686 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2687 if (!left--)
2688 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2689 if (!left--)
2690 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2691 if (!left--)
2692 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2693
2694 for (i = 0; i < card->tct_size; i++) {
2695 unsigned long tct;
2696 struct atm_vcc *vcc;
2697 struct vc_map *vc;
2698 char *p;
2699
2700 vc = card->vcs[i];
2701 if (!vc)
2702 continue;
2703
2704 vcc = NULL;
2705 if (vc->tx_vcc)
2706 vcc = vc->tx_vcc;
2707 if (!vcc)
2708 continue;
2709 if (left--)
2710 continue;
2711
2712 p = page;
2713 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2714 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2715
2716 for (i = 0; i < 8; i++)
2717 p += sprintf(p, " %08x", read_sram(card, tct + i));
2718 p += sprintf(p, "\n");
2719 return p - page;
2720 }
2721 return 0;
2722}
2723
2724/*****************************************************************************/
2725/* */
2726/* Interrupt handler */
2727/* */
2728/*****************************************************************************/
2729
2730static void
2731idt77252_collect_stat(struct idt77252_dev *card)
2732{
2733 u32 cdc, vpec, icc;
2734
2735 cdc = readl(SAR_REG_CDC);
2736 vpec = readl(SAR_REG_VPEC);
2737 icc = readl(SAR_REG_ICC);
2738
2739#ifdef NOTDEF
2740 printk("%s:", card->name);
2741
2742 if (cdc & 0x7f0000) {
2743 char *s = "";
2744
2745 printk(" [");
2746 if (cdc & (1 << 22)) {
2747 printk("%sRM ID", s);
2748 s = " | ";
2749 }
2750 if (cdc & (1 << 21)) {
2751 printk("%sCON TAB", s);
2752 s = " | ";
2753 }
2754 if (cdc & (1 << 20)) {
2755 printk("%sNO FB", s);
2756 s = " | ";
2757 }
2758 if (cdc & (1 << 19)) {
2759 printk("%sOAM CRC", s);
2760 s = " | ";
2761 }
2762 if (cdc & (1 << 18)) {
2763 printk("%sRM CRC", s);
2764 s = " | ";
2765 }
2766 if (cdc & (1 << 17)) {
2767 printk("%sRM FIFO", s);
2768 s = " | ";
2769 }
2770 if (cdc & (1 << 16)) {
2771 printk("%sRX FIFO", s);
2772 s = " | ";
2773 }
2774 printk("]");
2775 }
2776
2777 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2778 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2779#endif
2780}
2781
2782static irqreturn_t
2783idt77252_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2784{
2785 struct idt77252_dev *card = dev_id;
2786 u32 stat;
2787
2788 stat = readl(SAR_REG_STAT) & 0xffff;
2789 if (!stat) /* no interrupt for us */
2790 return IRQ_NONE;
2791
2792 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2793 printk("%s: Re-entering irq_handler()\n", card->name);
2794 goto out;
2795 }
2796
2797 writel(stat, SAR_REG_STAT); /* reset interrupt */
2798
2799 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2800 INTPRINTK("%s: TSIF\n", card->name);
2801 card->irqstat[15]++;
2802 idt77252_tx(card);
2803 }
2804 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2805 INTPRINTK("%s: TXICP\n", card->name);
2806 card->irqstat[14]++;
2807#ifdef CONFIG_ATM_IDT77252_DEBUG
2808 idt77252_tx_dump(card);
2809#endif
2810 }
2811 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2812 INTPRINTK("%s: TSQF\n", card->name);
2813 card->irqstat[12]++;
2814 idt77252_tx(card);
2815 }
2816 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2817 INTPRINTK("%s: TMROF\n", card->name);
2818 card->irqstat[11]++;
2819 idt77252_collect_stat(card);
2820 }
2821
2822 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2823 INTPRINTK("%s: EPDU\n", card->name);
2824 card->irqstat[5]++;
2825 idt77252_rx(card);
2826 }
2827 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2828 INTPRINTK("%s: RSQAF\n", card->name);
2829 card->irqstat[1]++;
2830 idt77252_rx(card);
2831 }
2832 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2833 INTPRINTK("%s: RSQF\n", card->name);
2834 card->irqstat[6]++;
2835 idt77252_rx(card);
2836 }
2837 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2838 INTPRINTK("%s: RAWCF\n", card->name);
2839 card->irqstat[4]++;
2840 idt77252_rx_raw(card);
2841 }
2842
2843 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2844 INTPRINTK("%s: PHYI", card->name);
2845 card->irqstat[10]++;
2846 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2847 card->atmdev->phy->interrupt(card->atmdev);
2848 }
2849
2850 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2851 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2852
2853 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2854
2855 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2856
2857 if (stat & SAR_STAT_FBQ0A)
2858 card->irqstat[2]++;
2859 if (stat & SAR_STAT_FBQ1A)
2860 card->irqstat[3]++;
2861 if (stat & SAR_STAT_FBQ2A)
2862 card->irqstat[7]++;
2863 if (stat & SAR_STAT_FBQ3A)
2864 card->irqstat[8]++;
2865
2866 schedule_work(&card->tqueue);
2867 }
2868
2869out:
2870 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2871 return IRQ_HANDLED;
2872}
2873
2874static void
2875idt77252_softint(void *dev_id)
2876{
2877 struct idt77252_dev *card = dev_id;
2878 u32 stat;
2879 int done;
2880
2881 for (done = 1; ; done = 1) {
2882 stat = readl(SAR_REG_STAT) >> 16;
2883
2884 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2885 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2886 done = 0;
2887 }
2888
2889 stat >>= 4;
2890 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2891 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2892 done = 0;
2893 }
2894
2895 stat >>= 4;
2896 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2897 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2898 done = 0;
2899 }
2900
2901 stat >>= 4;
2902 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2903 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2904 done = 0;
2905 }
2906
2907 if (done)
2908 break;
2909 }
2910
2911 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2912}
2913
2914
2915static int
2916open_card_oam(struct idt77252_dev *card)
2917{
2918 unsigned long flags;
2919 unsigned long addr;
2920 struct vc_map *vc;
2921 int vpi, vci;
2922 int index;
2923 u32 rcte;
2924
2925 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2926 for (vci = 3; vci < 5; vci++) {
2927 index = VPCI2VC(card, vpi, vci);
2928
2929 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2930 if (!vc) {
2931 printk("%s: can't alloc vc\n", card->name);
2932 return -ENOMEM;
2933 }
2934 memset(vc, 0, sizeof(struct vc_map));
2935
2936 vc->index = index;
2937 card->vcs[index] = vc;
2938
2939 flush_rx_pool(card, &vc->rcv.rx_pool);
2940
2941 rcte = SAR_RCTE_CONNECTOPEN |
2942 SAR_RCTE_RAWCELLINTEN |
2943 SAR_RCTE_RCQ |
2944 SAR_RCTE_FBP_1;
2945
2946 addr = card->rct_base + (vc->index << 2);
2947 write_sram(card, addr, rcte);
2948
2949 spin_lock_irqsave(&card->cmd_lock, flags);
2950 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2951 SAR_REG_CMD);
2952 waitfor_idle(card);
2953 spin_unlock_irqrestore(&card->cmd_lock, flags);
2954 }
2955 }
2956
2957 return 0;
2958}
2959
2960static void
2961close_card_oam(struct idt77252_dev *card)
2962{
2963 unsigned long flags;
2964 unsigned long addr;
2965 struct vc_map *vc;
2966 int vpi, vci;
2967 int index;
2968
2969 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2970 for (vci = 3; vci < 5; vci++) {
2971 index = VPCI2VC(card, vpi, vci);
2972 vc = card->vcs[index];
2973
2974 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2975
2976 spin_lock_irqsave(&card->cmd_lock, flags);
2977 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2978 SAR_REG_CMD);
2979 waitfor_idle(card);
2980 spin_unlock_irqrestore(&card->cmd_lock, flags);
2981
2982 if (vc->rcv.rx_pool.count) {
2983 DPRINTK("%s: closing a VC "
2984 "with pending rx buffers.\n",
2985 card->name);
2986
2987 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2988 }
2989 }
2990 }
2991}
2992
2993static int
2994open_card_ubr0(struct idt77252_dev *card)
2995{
2996 struct vc_map *vc;
2997
2998 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2999 if (!vc) {
3000 printk("%s: can't alloc vc\n", card->name);
3001 return -ENOMEM;
3002 }
3003 memset(vc, 0, sizeof(struct vc_map));
3004 card->vcs[0] = vc;
3005 vc->class = SCHED_UBR0;
3006
3007 vc->scq = alloc_scq(card, vc->class);
3008 if (!vc->scq) {
3009 printk("%s: can't get SCQ.\n", card->name);
3010 return -ENOMEM;
3011 }
3012
3013 card->scd2vc[0] = vc;
3014 vc->scd_index = 0;
3015 vc->scq->scd = card->scd_base;
3016
3017 fill_scd(card, vc->scq, vc->class);
3018
3019 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3020 write_sram(card, card->tct_base + 1, 0);
3021 write_sram(card, card->tct_base + 2, 0);
3022 write_sram(card, card->tct_base + 3, 0);
3023 write_sram(card, card->tct_base + 4, 0);
3024 write_sram(card, card->tct_base + 5, 0);
3025 write_sram(card, card->tct_base + 6, 0);
3026 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3027
3028 clear_bit(VCF_IDLE, &vc->flags);
3029 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3030 return 0;
3031}
3032
3033static int
3034idt77252_dev_open(struct idt77252_dev *card)
3035{
3036 u32 conf;
3037
3038 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3039 printk("%s: SAR not yet initialized.\n", card->name);
3040 return -1;
3041 }
3042
3043 conf = SAR_CFG_RXPTH| /* enable receive path */
3044 SAR_RX_DELAY | /* interrupt on complete PDU */
3045 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3046 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3047 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3048 SAR_CFG_FBIE | /* interrupt on low free buffers */
3049 SAR_CFG_TXEN | /* transmit operation enable */
3050 SAR_CFG_TXINT | /* interrupt on transmit status */
3051 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3052 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3053 SAR_CFG_PHYIE /* enable PHY interrupts */
3054 ;
3055
3056#ifdef CONFIG_ATM_IDT77252_RCV_ALL
3057 /* Test RAW cell receive. */
3058 conf |= SAR_CFG_VPECA;
3059#endif
3060
3061 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3062
3063 if (open_card_oam(card)) {
3064 printk("%s: Error initializing OAM.\n", card->name);
3065 return -1;
3066 }
3067
3068 if (open_card_ubr0(card)) {
3069 printk("%s: Error initializing UBR0.\n", card->name);
3070 return -1;
3071 }
3072
3073 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3074 return 0;
3075}
3076
3077void
3078idt77252_dev_close(struct atm_dev *dev)
3079{
3080 struct idt77252_dev *card = dev->dev_data;
3081 u32 conf;
3082
3083 close_card_oam(card);
3084
3085 conf = SAR_CFG_RXPTH | /* enable receive path */
3086 SAR_RX_DELAY | /* interrupt on complete PDU */
3087 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3088 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3089 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3090 SAR_CFG_FBIE | /* interrupt on low free buffers */
3091 SAR_CFG_TXEN | /* transmit operation enable */
3092 SAR_CFG_TXINT | /* interrupt on transmit status */
3093 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3094 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3095 ;
3096
3097 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3098
3099 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3100}
3101
3102
3103/*****************************************************************************/
3104/* */
3105/* Initialisation and Deinitialization of IDT77252 */
3106/* */
3107/*****************************************************************************/
3108
3109
3110static void
3111deinit_card(struct idt77252_dev *card)
3112{
3113 struct sk_buff *skb;
3114 int i, j;
3115
3116 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3117 printk("%s: SAR not yet initialized.\n", card->name);
3118 return;
3119 }
3120 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3121
3122 writel(0, SAR_REG_CFG);
3123
3124 if (card->atmdev)
3125 atm_dev_deregister(card->atmdev);
3126
3127 for (i = 0; i < 4; i++) {
3128 for (j = 0; j < FBQ_SIZE; j++) {
3129 skb = card->sbpool[i].skb[j];
3130 if (skb) {
3131 pci_unmap_single(card->pcidev,
3132 IDT77252_PRV_PADDR(skb),
3133 skb->end - skb->data,
3134 PCI_DMA_FROMDEVICE);
3135 card->sbpool[i].skb[j] = NULL;
3136 dev_kfree_skb(skb);
3137 }
3138 }
3139 }
3140
3141 vfree(card->soft_tst);
3142
3143 vfree(card->scd2vc);
3144
3145 vfree(card->vcs);
3146
3147 if (card->raw_cell_hnd) {
3148 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3149 card->raw_cell_hnd, card->raw_cell_paddr);
3150 }
3151
3152 if (card->rsq.base) {
3153 DIPRINTK("%s: Release RSQ ...\n", card->name);
3154 deinit_rsq(card);
3155 }
3156
3157 if (card->tsq.base) {
3158 DIPRINTK("%s: Release TSQ ...\n", card->name);
3159 deinit_tsq(card);
3160 }
3161
3162 DIPRINTK("idt77252: Release IRQ.\n");
3163 free_irq(card->pcidev->irq, card);
3164
3165 for (i = 0; i < 4; i++) {
3166 if (card->fbq[i])
3167 iounmap(card->fbq[i]);
3168 }
3169
3170 if (card->membase)
3171 iounmap(card->membase);
3172
3173 clear_bit(IDT77252_BIT_INIT, &card->flags);
3174 DIPRINTK("%s: Card deinitialized.\n", card->name);
3175}
3176
3177
3178static int __devinit
3179init_sram(struct idt77252_dev *card)
3180{
3181 int i;
3182
3183 for (i = 0; i < card->sramsize; i += 4)
3184 write_sram(card, (i >> 2), 0);
3185
3186 /* set SRAM layout for THIS card */
3187 if (card->sramsize == (512 * 1024)) {
3188 card->tct_base = SAR_SRAM_TCT_128_BASE;
3189 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3190 / SAR_SRAM_TCT_SIZE;
3191 card->rct_base = SAR_SRAM_RCT_128_BASE;
3192 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3193 / SAR_SRAM_RCT_SIZE;
3194 card->rt_base = SAR_SRAM_RT_128_BASE;
3195 card->scd_base = SAR_SRAM_SCD_128_BASE;
3196 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3197 / SAR_SRAM_SCD_SIZE;
3198 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3199 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3200 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3201 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3202 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3203 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3204 card->fifo_size = SAR_RXFD_SIZE_32K;
3205 } else {
3206 card->tct_base = SAR_SRAM_TCT_32_BASE;
3207 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3208 / SAR_SRAM_TCT_SIZE;
3209 card->rct_base = SAR_SRAM_RCT_32_BASE;
3210 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3211 / SAR_SRAM_RCT_SIZE;
3212 card->rt_base = SAR_SRAM_RT_32_BASE;
3213 card->scd_base = SAR_SRAM_SCD_32_BASE;
3214 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3215 / SAR_SRAM_SCD_SIZE;
3216 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3217 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3218 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3219 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3220 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3221 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3222 card->fifo_size = SAR_RXFD_SIZE_4K;
3223 }
3224
3225 /* Initialize TCT */
3226 for (i = 0; i < card->tct_size; i++) {
3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3232 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3233 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3234 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3235 }
3236
3237 /* Initialize RCT */
3238 for (i = 0; i < card->rct_size; i++) {
3239 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3240 (u32) SAR_RCTE_RAWCELLINTEN);
3241 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3242 (u32) 0);
3243 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3244 (u32) 0);
3245 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3246 (u32) 0xffffffff);
3247 }
3248
3249 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3250 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3251 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3252 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3253 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3254 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3255 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3256 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3257
3258 /* Initialize rate table */
3259 for (i = 0; i < 256; i++) {
3260 write_sram(card, card->rt_base + i, log_to_rate[i]);
3261 }
3262
3263 for (i = 0; i < 128; i++) {
3264 unsigned int tmp;
3265
3266 tmp = rate_to_log[(i << 2) + 0] << 0;
3267 tmp |= rate_to_log[(i << 2) + 1] << 8;
3268 tmp |= rate_to_log[(i << 2) + 2] << 16;
3269 tmp |= rate_to_log[(i << 2) + 3] << 24;
3270 write_sram(card, card->rt_base + 256 + i, tmp);
3271 }
3272
3273#if 0 /* Fill RDF and AIR tables. */
3274 for (i = 0; i < 128; i++) {
3275 unsigned int tmp;
3276
3277 tmp = RDF[0][(i << 1) + 0] << 16;
3278 tmp |= RDF[0][(i << 1) + 1] << 0;
3279 write_sram(card, card->rt_base + 512 + i, tmp);
3280 }
3281
3282 for (i = 0; i < 128; i++) {
3283 unsigned int tmp;
3284
3285 tmp = AIR[0][(i << 1) + 0] << 16;
3286 tmp |= AIR[0][(i << 1) + 1] << 0;
3287 write_sram(card, card->rt_base + 640 + i, tmp);
3288 }
3289#endif
3290
3291 IPRINTK("%s: initialize rate table ...\n", card->name);
3292 writel(card->rt_base << 2, SAR_REG_RTBL);
3293
3294 /* Initialize TSTs */
3295 IPRINTK("%s: initialize TST ...\n", card->name);
3296 card->tst_free = card->tst_size - 2; /* last two are jumps */
3297
3298 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3299 write_sram(card, i, TSTE_OPC_VAR);
3300 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3301 idt77252_sram_write_errors = 1;
3302 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3303 idt77252_sram_write_errors = 0;
3304 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3305 write_sram(card, i, TSTE_OPC_VAR);
3306 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3307 idt77252_sram_write_errors = 1;
3308 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3309 idt77252_sram_write_errors = 0;
3310
3311 card->tst_index = 0;
3312 writel(card->tst[0] << 2, SAR_REG_TSTB);
3313
3314 /* Initialize ABRSTD and Receive FIFO */
3315 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3316 writel(card->abrst_size | (card->abrst_base << 2),
3317 SAR_REG_ABRSTD);
3318
3319 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3320 writel(card->fifo_size | (card->fifo_base << 2),
3321 SAR_REG_RXFD);
3322
3323 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3324 return 0;
3325}
3326
3327static int __devinit
3328init_card(struct atm_dev *dev)
3329{
3330 struct idt77252_dev *card = dev->dev_data;
3331 struct pci_dev *pcidev = card->pcidev;
3332 unsigned long tmpl, modl;
3333 unsigned int linkrate, rsvdcr;
3334 unsigned int tst_entries;
3335 struct net_device *tmp;
3336 char tname[10];
3337
3338 u32 size;
3339 u_char pci_byte;
3340 u32 conf;
3341 int i, k;
3342
3343 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3344 printk("Error: SAR already initialized.\n");
3345 return -1;
3346 }
3347
3348/*****************************************************************/
3349/* P C I C O N F I G U R A T I O N */
3350/*****************************************************************/
3351
3352 /* Set PCI Retry-Timeout and TRDY timeout */
3353 IPRINTK("%s: Checking PCI retries.\n", card->name);
3354 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3355 printk("%s: can't read PCI retry timeout.\n", card->name);
3356 deinit_card(card);
3357 return -1;
3358 }
3359 if (pci_byte != 0) {
3360 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3361 card->name, pci_byte);
3362 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3363 printk("%s: can't set PCI retry timeout.\n",
3364 card->name);
3365 deinit_card(card);
3366 return -1;
3367 }
3368 }
3369 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3370 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3371 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3372 deinit_card(card);
3373 return -1;
3374 }
3375 if (pci_byte != 0) {
3376 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3377 card->name, pci_byte);
3378 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3379 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3380 deinit_card(card);
3381 return -1;
3382 }
3383 }
3384 /* Reset Timer register */
3385 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3386 printk("%s: resetting timer overflow.\n", card->name);
3387 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3388 }
3389 IPRINTK("%s: Request IRQ ... ", card->name);
3390 if (request_irq(pcidev->irq, idt77252_interrupt, SA_INTERRUPT|SA_SHIRQ,
3391 card->name, card) != 0) {
3392 printk("%s: can't allocate IRQ.\n", card->name);
3393 deinit_card(card);
3394 return -1;
3395 }
3396 IPRINTK("got %d.\n", pcidev->irq);
3397
3398/*****************************************************************/
3399/* C H E C K A N D I N I T S R A M */
3400/*****************************************************************/
3401
3402 IPRINTK("%s: Initializing SRAM\n", card->name);
3403
3404 /* preset size of connecton table, so that init_sram() knows about it */
3405 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3406 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3407 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3408#ifndef CONFIG_ATM_IDT77252_SEND_IDLE
3409 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3410#endif
3411 0;
3412
3413 if (card->sramsize == (512 * 1024))
3414 conf |= SAR_CFG_CNTBL_1k;
3415 else
3416 conf |= SAR_CFG_CNTBL_512;
3417
3418 switch (vpibits) {
3419 case 0:
3420 conf |= SAR_CFG_VPVCS_0;
3421 break;
3422 default:
3423 case 1:
3424 conf |= SAR_CFG_VPVCS_1;
3425 break;
3426 case 2:
3427 conf |= SAR_CFG_VPVCS_2;
3428 break;
3429 case 8:
3430 conf |= SAR_CFG_VPVCS_8;
3431 break;
3432 }
3433
3434 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3435
3436 if (init_sram(card) < 0)
3437 return -1;
3438
3439/********************************************************************/
3440/* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3441/********************************************************************/
3442 /* Initialize TSQ */
3443 if (0 != init_tsq(card)) {
3444 deinit_card(card);
3445 return -1;
3446 }
3447 /* Initialize RSQ */
3448 if (0 != init_rsq(card)) {
3449 deinit_card(card);
3450 return -1;
3451 }
3452
3453 card->vpibits = vpibits;
3454 if (card->sramsize == (512 * 1024)) {
3455 card->vcibits = 10 - card->vpibits;
3456 } else {
3457 card->vcibits = 9 - card->vpibits;
3458 }
3459
3460 card->vcimask = 0;
3461 for (k = 0, i = 1; k < card->vcibits; k++) {
3462 card->vcimask |= i;
3463 i <<= 1;
3464 }
3465
3466 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3467 writel(0, SAR_REG_VPM);
3468
3469 /* Little Endian Order */
3470 writel(0, SAR_REG_GP);
3471
3472 /* Initialize RAW Cell Handle Register */
3473 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3474 &card->raw_cell_paddr);
3475 if (!card->raw_cell_hnd) {
3476 printk("%s: memory allocation failure.\n", card->name);
3477 deinit_card(card);
3478 return -1;
3479 }
3480 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3481 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3482 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3483 card->raw_cell_hnd);
3484
3485 size = sizeof(struct vc_map *) * card->tct_size;
3486 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3487 if (NULL == (card->vcs = vmalloc(size))) {
3488 printk("%s: memory allocation failure.\n", card->name);
3489 deinit_card(card);
3490 return -1;
3491 }
3492 memset(card->vcs, 0, size);
3493
3494 size = sizeof(struct vc_map *) * card->scd_size;
3495 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3496 card->name, size);
3497 if (NULL == (card->scd2vc = vmalloc(size))) {
3498 printk("%s: memory allocation failure.\n", card->name);
3499 deinit_card(card);
3500 return -1;
3501 }
3502 memset(card->scd2vc, 0, size);
3503
3504 size = sizeof(struct tst_info) * (card->tst_size - 2);
3505 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3506 card->name, size);
3507 if (NULL == (card->soft_tst = vmalloc(size))) {
3508 printk("%s: memory allocation failure.\n", card->name);
3509 deinit_card(card);
3510 return -1;
3511 }
3512 for (i = 0; i < card->tst_size - 2; i++) {
3513 card->soft_tst[i].tste = TSTE_OPC_VAR;
3514 card->soft_tst[i].vc = NULL;
3515 }
3516
3517 if (dev->phy == NULL) {
3518 printk("%s: No LT device defined.\n", card->name);
3519 deinit_card(card);
3520 return -1;
3521 }
3522 if (dev->phy->ioctl == NULL) {
3523 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3524 deinit_card(card);
3525 return -1;
3526 }
3527
3528#ifdef CONFIG_ATM_IDT77252_USE_SUNI
3529 /*
3530 * this is a jhs hack to get around special functionality in the
3531 * phy driver for the atecom hardware; the functionality doesn't
3532 * exist in the linux atm suni driver
3533 *
3534 * it isn't the right way to do things, but as the guy from NIST
3535 * said, talking about their measurement of the fine structure
3536 * constant, "it's good enough for government work."
3537 */
3538 linkrate = 149760000;
3539#endif
3540
3541 card->link_pcr = (linkrate / 8 / 53);
3542 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3543 card->name, linkrate, card->link_pcr);
3544
3545#ifdef CONFIG_ATM_IDT77252_SEND_IDLE
3546 card->utopia_pcr = card->link_pcr;
3547#else
3548 card->utopia_pcr = (160000000 / 8 / 54);
3549#endif
3550
3551 rsvdcr = 0;
3552 if (card->utopia_pcr > card->link_pcr)
3553 rsvdcr = card->utopia_pcr - card->link_pcr;
3554
3555 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3556 modl = tmpl % (unsigned long)card->utopia_pcr;
3557 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3558 if (modl)
3559 tst_entries++;
3560 card->tst_free -= tst_entries;
3561 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3562
3563#ifdef HAVE_EEPROM
3564 idt77252_eeprom_init(card);
3565 printk("%s: EEPROM: %02x:", card->name,
3566 idt77252_eeprom_read_status(card));
3567
3568 for (i = 0; i < 0x80; i++) {
3569 printk(" %02x",
3570 idt77252_eeprom_read_byte(card, i)
3571 );
3572 }
3573 printk("\n");
3574#endif /* HAVE_EEPROM */
3575
3576 /*
3577 * XXX: <hack>
3578 */
3579 sprintf(tname, "eth%d", card->index);
3580 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */
3581 if (tmp) {
3582 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3583
3584 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3585 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3586 card->atmdev->esi[2], card->atmdev->esi[3],
3587 card->atmdev->esi[4], card->atmdev->esi[5]);
3588 }
3589 /*
3590 * XXX: </hack>
3591 */
3592
3593 /* Set Maximum Deficit Count for now. */
3594 writel(0xffff, SAR_REG_MDFCT);
3595
3596 set_bit(IDT77252_BIT_INIT, &card->flags);
3597
3598 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3599 return 0;
3600}
3601
3602
3603/*****************************************************************************/
3604/* */
3605/* Probing of IDT77252 ABR SAR */
3606/* */
3607/*****************************************************************************/
3608
3609
3610static int __devinit
3611idt77252_preset(struct idt77252_dev *card)
3612{
3613 u16 pci_command;
3614
3615/*****************************************************************/
3616/* P C I C O N F I G U R A T I O N */
3617/*****************************************************************/
3618
3619 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3620 card->name);
3621 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3622 printk("%s: can't read PCI_COMMAND.\n", card->name);
3623 deinit_card(card);
3624 return -1;
3625 }
3626 if (!(pci_command & PCI_COMMAND_IO)) {
3627 printk("%s: PCI_COMMAND: %04x (???)\n",
3628 card->name, pci_command);
3629 deinit_card(card);
3630 return (-1);
3631 }
3632 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3633 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3634 printk("%s: can't write PCI_COMMAND.\n", card->name);
3635 deinit_card(card);
3636 return -1;
3637 }
3638/*****************************************************************/
3639/* G E N E R I C R E S E T */
3640/*****************************************************************/
3641
3642 /* Software reset */
3643 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3644 mdelay(1);
3645 writel(0, SAR_REG_CFG);
3646
3647 IPRINTK("%s: Software resetted.\n", card->name);
3648 return 0;
3649}
3650
3651
3652static unsigned long __devinit
3653probe_sram(struct idt77252_dev *card)
3654{
3655 u32 data, addr;
3656
3657 writel(0, SAR_REG_DR0);
3658 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3659
3660 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3661 writel(0xdeadbeef, SAR_REG_DR0);
3662 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3663
3664 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3665 data = readl(SAR_REG_DR0);
3666
3667 if (data != 0)
3668 break;
3669 }
3670
3671 return addr * sizeof(u32);
3672}
3673
3674static int __devinit
3675idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3676{
3677 static struct idt77252_dev **last = &idt77252_chain;
3678 static int index = 0;
3679
3680 unsigned long membase, srambase;
3681 struct idt77252_dev *card;
3682 struct atm_dev *dev;
3683 ushort revision = 0;
3684 int i, err;
3685
3686
3687 if ((err = pci_enable_device(pcidev))) {
3688 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3689 return err;
3690 }
3691
3692 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
3693 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
3694 err = -ENODEV;
3695 goto err_out_disable_pdev;
3696 }
3697
3698 card = kmalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3699 if (!card) {
3700 printk("idt77252-%d: can't allocate private data\n", index);
3701 err = -ENOMEM;
3702 goto err_out_disable_pdev;
3703 }
3704 memset(card, 0, sizeof(struct idt77252_dev));
3705
3706 card->revision = revision;
3707 card->index = index;
3708 card->pcidev = pcidev;
3709 sprintf(card->name, "idt77252-%d", card->index);
3710
3711 INIT_WORK(&card->tqueue, idt77252_softint, (void *)card);
3712
3713 membase = pci_resource_start(pcidev, 1);
3714 srambase = pci_resource_start(pcidev, 2);
3715
3716 init_MUTEX(&card->mutex);
3717 spin_lock_init(&card->cmd_lock);
3718 spin_lock_init(&card->tst_lock);
3719
3720 init_timer(&card->tst_timer);
3721 card->tst_timer.data = (unsigned long)card;
3722 card->tst_timer.function = tst_timer;
3723
3724 /* Do the I/O remapping... */
3725 card->membase = ioremap(membase, 1024);
3726 if (!card->membase) {
3727 printk("%s: can't ioremap() membase\n", card->name);
3728 err = -EIO;
3729 goto err_out_free_card;
3730 }
3731
3732 if (idt77252_preset(card)) {
3733 printk("%s: preset failed\n", card->name);
3734 err = -EIO;
3735 goto err_out_iounmap;
3736 }
3737
3738 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL);
3739 if (!dev) {
3740 printk("%s: can't register atm device\n", card->name);
3741 err = -EIO;
3742 goto err_out_iounmap;
3743 }
3744 dev->dev_data = card;
3745 card->atmdev = dev;
3746
3747#ifdef CONFIG_ATM_IDT77252_USE_SUNI
3748 suni_init(dev);
3749 if (!dev->phy) {
3750 printk("%s: can't init SUNI\n", card->name);
3751 err = -EIO;
3752 goto err_out_deinit_card;
3753 }
3754#endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3755
3756 card->sramsize = probe_sram(card);
3757
3758 for (i = 0; i < 4; i++) {
3759 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3760 if (!card->fbq[i]) {
3761 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3762 err = -EIO;
3763 goto err_out_deinit_card;
3764 }
3765 }
3766
3767 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3768 card->name, ((revision > 1) && (revision < 25)) ?
3769 'A' + revision - 1 : '?', membase, srambase,
3770 card->sramsize / 1024);
3771
3772 if (init_card(dev)) {
3773 printk("%s: init_card failed\n", card->name);
3774 err = -EIO;
3775 goto err_out_deinit_card;
3776 }
3777
3778 dev->ci_range.vpi_bits = card->vpibits;
3779 dev->ci_range.vci_bits = card->vcibits;
3780 dev->link_rate = card->link_pcr;
3781
3782 if (dev->phy->start)
3783 dev->phy->start(dev);
3784
3785 if (idt77252_dev_open(card)) {
3786 printk("%s: dev_open failed\n", card->name);
3787 err = -EIO;
3788 goto err_out_stop;
3789 }
3790
3791 *last = card;
3792 last = &card->next;
3793 index++;
3794
3795 return 0;
3796
3797err_out_stop:
3798 if (dev->phy->stop)
3799 dev->phy->stop(dev);
3800
3801err_out_deinit_card:
3802 deinit_card(card);
3803
3804err_out_iounmap:
3805 iounmap(card->membase);
3806
3807err_out_free_card:
3808 kfree(card);
3809
3810err_out_disable_pdev:
3811 pci_disable_device(pcidev);
3812 return err;
3813}
3814
3815static struct pci_device_id idt77252_pci_tbl[] =
3816{
3817 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3818 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3819 { 0, }
3820};
3821
3822MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3823
3824static struct pci_driver idt77252_driver = {
3825 .name = "idt77252",
3826 .id_table = idt77252_pci_tbl,
3827 .probe = idt77252_init_one,
3828};
3829
3830static int __init idt77252_init(void)
3831{
3832 struct sk_buff *skb;
3833
3834 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3835
3836 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3837 sizeof(struct idt77252_skb_prv)) {
3838 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3839 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3840 (unsigned long) sizeof(struct atm_skb_data) +
3841 sizeof(struct idt77252_skb_prv));
3842 return -EIO;
3843 }
3844
3845 return pci_register_driver(&idt77252_driver);
3846}
3847
3848static void __exit idt77252_exit(void)
3849{
3850 struct idt77252_dev *card;
3851 struct atm_dev *dev;
3852
3853 pci_unregister_driver(&idt77252_driver);
3854
3855 while (idt77252_chain) {
3856 card = idt77252_chain;
3857 dev = card->atmdev;
3858 idt77252_chain = card->next;
3859
3860 if (dev->phy->stop)
3861 dev->phy->stop(dev);
3862 deinit_card(card);
3863 pci_disable_device(card->pcidev);
3864 kfree(card);
3865 }
3866
3867 DIPRINTK("idt77252: finished cleanup-module().\n");
3868}
3869
3870module_init(idt77252_init);
3871module_exit(idt77252_exit);
3872
3873MODULE_LICENSE("GPL");
3874
3875module_param(vpibits, uint, 0);
3876MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3877#ifdef CONFIG_ATM_IDT77252_DEBUG
3878module_param(debug, ulong, 0644);
3879MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3880#endif
3881
3882MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3883MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");