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Eric Miao14c6b5e2009-03-20 12:50:22 +08001/*
2 * linux/arch/arm/mach-mmp/pxa910.c
3 *
4 * Code specific to PXA910
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/list.h>
15#include <linux/io.h>
16
17#include <asm/mach/time.h>
18#include <mach/addr-map.h>
19#include <mach/regs-apbc.h>
20#include <mach/regs-apmu.h>
21#include <mach/cputype.h>
22#include <mach/irqs.h>
23#include <mach/gpio.h>
24#include <mach/dma.h>
25#include <mach/mfp.h>
26#include <mach/devices.h>
27
28#include "common.h"
29#include "clock.h"
30
31#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
32
33static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
34{
35 MFP_ADDR_X(GPIO0, GPIO54, 0xdc),
36 MFP_ADDR_X(GPIO67, GPIO98, 0x1b8),
37 MFP_ADDR_X(GPIO100, GPIO109, 0x238),
38
39 MFP_ADDR(GPIO123, 0xcc),
40 MFP_ADDR(GPIO124, 0xd0),
41
42 MFP_ADDR(DF_IO0, 0x40),
43 MFP_ADDR(DF_IO1, 0x3c),
44 MFP_ADDR(DF_IO2, 0x38),
45 MFP_ADDR(DF_IO3, 0x34),
46 MFP_ADDR(DF_IO4, 0x30),
47 MFP_ADDR(DF_IO5, 0x2c),
48 MFP_ADDR(DF_IO6, 0x28),
49 MFP_ADDR(DF_IO7, 0x24),
50 MFP_ADDR(DF_IO8, 0x20),
51 MFP_ADDR(DF_IO9, 0x1c),
52 MFP_ADDR(DF_IO10, 0x18),
53 MFP_ADDR(DF_IO11, 0x14),
54 MFP_ADDR(DF_IO12, 0x10),
55 MFP_ADDR(DF_IO13, 0xc),
56 MFP_ADDR(DF_IO14, 0x8),
57 MFP_ADDR(DF_IO15, 0x4),
58
59 MFP_ADDR(DF_nCS0_SM_nCS2, 0x44),
60 MFP_ADDR(DF_nCS1_SM_nCS3, 0x48),
61 MFP_ADDR(SM_nCS0, 0x4c),
62 MFP_ADDR(SM_nCS1, 0x50),
63 MFP_ADDR(DF_WEn, 0x54),
64 MFP_ADDR(DF_REn, 0x58),
65 MFP_ADDR(DF_CLE_SM_OEn, 0x5c),
66 MFP_ADDR(DF_ALE_SM_WEn, 0x60),
67 MFP_ADDR(SM_SCLK, 0x64),
68 MFP_ADDR(DF_RDY0, 0x68),
69 MFP_ADDR(SM_BE0, 0x6c),
70 MFP_ADDR(SM_BE1, 0x70),
71 MFP_ADDR(SM_ADV, 0x74),
72 MFP_ADDR(DF_RDY1, 0x78),
73 MFP_ADDR(SM_ADVMUX, 0x7c),
74 MFP_ADDR(SM_RDY, 0x80),
75
76 MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84),
77
78 MFP_ADDR_END,
79};
80
81#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
82
83static void __init pxa910_init_gpio(void)
84{
85 int i;
86
87 /* enable GPIO clock */
88 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO);
89
90 /* unmask GPIO edge detection for all 4 banks - APMASKx */
91 for (i = 0; i < 4; i++)
92 __raw_writel(0xffffffff, APMASK(i));
93
94 pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL);
95}
96
97void __init pxa910_init_irq(void)
98{
99 icu_init_irq();
100 pxa910_init_gpio();
101}
102
103/* APB peripheral clocks */
104static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
105static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
Eric Miao1a779202009-04-13 15:34:54 +0800106static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
107static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
Eric Miao14c6b5e2009-03-20 12:50:22 +0800108
109/* device and clock bindings */
110static struct clk_lookup pxa910_clkregs[] = {
111 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
112 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
Eric Miao1a779202009-04-13 15:34:54 +0800113 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
114 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
Eric Miao14c6b5e2009-03-20 12:50:22 +0800115};
116
117static int __init pxa910_init(void)
118{
119 if (cpu_is_pxa910()) {
120 mfp_init_base(MFPR_VIRT_BASE);
121 mfp_init_addr(pxa910_mfp_addr_map);
122 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
123 clks_register(ARRAY_AND_SIZE(pxa910_clkregs));
124 }
125
126 return 0;
127}
128postcore_initcall(pxa910_init);
129
130/* system timer - clock enabled, 3.25MHz */
131#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
132
133static void __init pxa910_timer_init(void)
134{
135 /* reset and configure */
136 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
137 __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
138
139 timer_init(IRQ_PXA910_AP1_TIMER1);
140}
141
142struct sys_timer pxa910_timer = {
143 .init = pxa910_timer_init,
144};
145
146/* on-chip devices */
147
148/* NOTE: there are totally 3 UARTs on PXA910:
149 *
150 * UART1 - Slow UART (can be used both by AP and CP)
151 * UART2/3 - Fast UART
152 *
153 * To be backward compatible with the legacy FFUART/BTUART/STUART sequence,
154 * they are re-ordered as:
155 *
156 * pxa910_device_uart1 - UART2 as FFUART
157 * pxa910_device_uart2 - UART3 as BTUART
158 *
159 * UART1 is not used by AP for the moment.
160 */
161PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
162PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
Eric Miao1a779202009-04-13 15:34:54 +0800163PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
164PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);