Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / 1d9f13c49ed750260f40317629bdd66160a3ac16 / . / arch / arm / plat-s5pc1xx / clock.c
blob: 0aff16d1cc2c683c610f20cc9ba08a70c243a49a [file] [log] [blame]
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]1/* linux/arch/arm/plat-s5pc1xx/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * S5PC1XX Base clock support
6 *
7 * Based on plat-s3c64xx/clock.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/regs-clock.h>
25#include <plat/devs.h>
26#include <plat/clock.h>
27
28struct clk clk_27m = {
29 .name = "clk_27m",
30 .id = -1,
31 .rate = 27000000,
32};
33
34static int clk_48m_ctrl(struct clk *clk, int enable)
35{
36 unsigned long flags;
37 u32 val;
38
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
41
42 val = __raw_readl(S5PC100_CLKSRC1);
43 if (enable)
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
45 else
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
47
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
50
51 return 0;
52}
53
54struct clk clk_48m = {
55 .name = "clk_48m",
56 .id = -1,
57 .rate = 48000000,
58 .enable = clk_48m_ctrl,
59};
60
61struct clk clk_54m = {
62 .name = "clk_54m",
63 .id = -1,
64 .rate = 54000000,
65};
66
67static int clk_default_setrate(struct clk *clk, unsigned long rate)
68{
69 clk->rate = rate;
70 return 0;
71}
72
Ben Dooksb3bf41b2009-12-01 01:24:37 +0000[diff] [blame]73static struct clk_ops clk_ops_default_setrate = {
74 .set_rate = clk_default_setrate,
75};
76
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]77static int clk_dummy_enable(struct clk *clk, int enable)
78{
79 return 0;
80}
81
82struct clk clk_hd0 = {
83 .name = "hclkd0",
84 .id = -1,
85 .rate = 0,
86 .parent = NULL,
87 .ctrlbit = 0,
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]88 .enable = clk_dummy_enable,
Ben Dooksb3bf41b2009-12-01 01:24:37 +0000[diff] [blame]89 .ops = &clk_ops_default_setrate,
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]90};
91
92struct clk clk_pd0 = {
93 .name = "pclkd0",
94 .id = -1,
95 .rate = 0,
96 .parent = NULL,
97 .ctrlbit = 0,
Ben Dooksb3bf41b2009-12-01 01:24:37 +0000[diff] [blame]98 .ops = &clk_ops_default_setrate,
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]99 .enable = clk_dummy_enable,
100};
101
102static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
103{
104 unsigned int ctrlbit = clk->ctrlbit;
105 u32 con;
106
107 con = __raw_readl(reg);
108 if (enable)
109 con |= ctrlbit;
110 else
111 con &= ~ctrlbit;
112 __raw_writel(con, reg);
113
114 return 0;
115}
116
117static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
118{
119 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
120}
121
122static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
123{
124 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
125}
126
127static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
128{
129 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
130}
131
132static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
133{
134 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
135}
136
137static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
138{
139 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
140}
141
142static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
143{
144 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
145}
146
147static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
148{
149 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
150}
151
152static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
153{
154 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
155}
156
157static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
158{
159 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
160}
161
162static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
163{
164 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
165}
166
167int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
168{
169 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
170}
171
172int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
173{
174 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
175}
176
177static struct clk s5pc100_init_clocks_disable[] = {
178 {
179 .name = "dsi",
180 .id = -1,
181 .parent = &clk_p,
182 .enable = s5pc100_clk_d11_ctrl,
183 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
184 }, {
185 .name = "csi",
186 .id = -1,
187 .parent = &clk_h,
188 .enable = s5pc100_clk_d11_ctrl,
189 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
190 }, {
191 .name = "ccan",
192 .id = 0,
193 .parent = &clk_p,
194 .enable = s5pc100_clk_d14_ctrl,
195 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
196 }, {
197 .name = "ccan",
198 .id = 1,
199 .parent = &clk_p,
200 .enable = s5pc100_clk_d14_ctrl,
201 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
202 }, {
203 .name = "keypad",
204 .id = -1,
205 .parent = &clk_p,
206 .enable = s5pc100_clk_d15_ctrl,
207 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
208 }, {
209 .name = "hclkd2",
210 .id = -1,
211 .parent = NULL,
212 .enable = s5pc100_clk_d20_ctrl,
213 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
214 }, {
215 .name = "iis-d2",
216 .id = -1,
217 .parent = NULL,
218 .enable = s5pc100_clk_d20_ctrl,
219 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
220 },
221};
222
223static struct clk s5pc100_init_clocks[] = {
224 /* System1 (D0_0) devices */
225 {
226 .name = "intc",
227 .id = -1,
228 .parent = &clk_hd0,
229 .enable = s5pc100_clk_d00_ctrl,
230 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
231 }, {
232 .name = "tzic",
233 .id = -1,
234 .parent = &clk_hd0,
235 .enable = s5pc100_clk_d00_ctrl,
236 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
237 }, {
238 .name = "cf-ata",
239 .id = -1,
240 .parent = &clk_hd0,
241 .enable = s5pc100_clk_d00_ctrl,
242 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
243 }, {
244 .name = "mdma",
245 .id = -1,
246 .parent = &clk_hd0,
247 .enable = s5pc100_clk_d00_ctrl,
248 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
249 }, {
250 .name = "g2d",
251 .id = -1,
252 .parent = &clk_hd0,
253 .enable = s5pc100_clk_d00_ctrl,
254 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
255 }, {
256 .name = "secss",
257 .id = -1,
258 .parent = &clk_hd0,
259 .enable = s5pc100_clk_d00_ctrl,
260 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
261 }, {
262 .name = "cssys",
263 .id = -1,
264 .parent = &clk_hd0,
265 .enable = s5pc100_clk_d00_ctrl,
266 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
267 },
268
269 /* Memory (D0_1) devices */
270 {
271 .name = "dmc",
272 .id = -1,
273 .parent = &clk_hd0,
274 .enable = s5pc100_clk_d01_ctrl,
275 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
276 }, {
277 .name = "sromc",
278 .id = -1,
279 .parent = &clk_hd0,
280 .enable = s5pc100_clk_d01_ctrl,
281 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
282 }, {
283 .name = "onenand",
284 .id = -1,
285 .parent = &clk_hd0,
286 .enable = s5pc100_clk_d01_ctrl,
287 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
288 }, {
289 .name = "nand",
290 .id = -1,
291 .parent = &clk_hd0,
292 .enable = s5pc100_clk_d01_ctrl,
293 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
294 }, {
295 .name = "intmem",
296 .id = -1,
297 .parent = &clk_hd0,
298 .enable = s5pc100_clk_d01_ctrl,
299 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
300 }, {
301 .name = "ebi",
302 .id = -1,
303 .parent = &clk_hd0,
304 .enable = s5pc100_clk_d01_ctrl,
305 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
306 },
307
308 /* System2 (D0_2) devices */
309 {
310 .name = "seckey",
311 .id = -1,
312 .parent = &clk_pd0,
313 .enable = s5pc100_clk_d02_ctrl,
314 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
315 }, {
316 .name = "sdm",
317 .id = -1,
318 .parent = &clk_hd0,
319 .enable = s5pc100_clk_d02_ctrl,
320 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
321 },
322
323 /* File (D1_0) devices */
324 {
325 .name = "pdma",
326 .id = 0,
327 .parent = &clk_h,
328 .enable = s5pc100_clk_d10_ctrl,
329 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
330 }, {
331 .name = "pdma",
332 .id = 1,
333 .parent = &clk_h,
334 .enable = s5pc100_clk_d10_ctrl,
335 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
336 }, {
337 .name = "usb-host",
338 .id = -1,
339 .parent = &clk_h,
340 .enable = s5pc100_clk_d10_ctrl,
341 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
342 }, {
343 .name = "otg",
344 .id = -1,
345 .parent = &clk_h,
346 .enable = s5pc100_clk_d10_ctrl,
347 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
348 }, {
349 .name = "modem",
350 .id = -1,
351 .parent = &clk_h,
352 .enable = s5pc100_clk_d10_ctrl,
353 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
354 }, {
355 .name = "hsmmc",
356 .id = 0,
357 .parent = &clk_48m,
358 .enable = s5pc100_clk_d10_ctrl,
359 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
360 }, {
361 .name = "hsmmc",
362 .id = 1,
363 .parent = &clk_48m,
364 .enable = s5pc100_clk_d10_ctrl,
365 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
366 }, {
367 .name = "hsmmc",
368 .id = 2,
369 .parent = &clk_48m,
370 .enable = s5pc100_clk_d10_ctrl,
371 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
372 },
373
374 /* Multimedia1 (D1_1) devices */
375 {
376 .name = "lcd",
377 .id = -1,
378 .parent = &clk_p,
379 .enable = s5pc100_clk_d11_ctrl,
380 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
381 }, {
382 .name = "rotator",
383 .id = -1,
384 .parent = &clk_p,
385 .enable = s5pc100_clk_d11_ctrl,
386 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
387 }, {
388 .name = "fimc",
389 .id = -1,
390 .parent = &clk_p,
391 .enable = s5pc100_clk_d11_ctrl,
392 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
393 }, {
394 .name = "fimc",
395 .id = -1,
396 .parent = &clk_p,
397 .enable = s5pc100_clk_d11_ctrl,
398 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
399 }, {
400 .name = "fimc",
401 .id = -1,
402 .parent = &clk_p,
403 .enable = s5pc100_clk_d11_ctrl,
404 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
405 }, {
406 .name = "jpeg",
407 .id = -1,
408 .parent = &clk_p,
409 .enable = s5pc100_clk_d11_ctrl,
410 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
411 }, {
412 .name = "g3d",
413 .id = -1,
414 .parent = &clk_p,
415 .enable = s5pc100_clk_d11_ctrl,
416 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
417 },
418
419 /* Multimedia2 (D1_2) devices */
420 {
421 .name = "tv",
422 .id = -1,
423 .parent = &clk_p,
424 .enable = s5pc100_clk_d12_ctrl,
425 .ctrlbit = S5PC100_CLKGATE_D12_TV,
426 }, {
427 .name = "vp",
428 .id = -1,
429 .parent = &clk_p,
430 .enable = s5pc100_clk_d12_ctrl,
431 .ctrlbit = S5PC100_CLKGATE_D12_VP,
432 }, {
433 .name = "mixer",
434 .id = -1,
435 .parent = &clk_p,
436 .enable = s5pc100_clk_d12_ctrl,
437 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
438 }, {
439 .name = "hdmi",
440 .id = -1,
441 .parent = &clk_p,
442 .enable = s5pc100_clk_d12_ctrl,
443 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
444 }, {
445 .name = "mfc",
446 .id = -1,
447 .parent = &clk_p,
448 .enable = s5pc100_clk_d12_ctrl,
449 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
450 },
451
452 /* System (D1_3) devices */
453 {
454 .name = "chipid",
455 .id = -1,
456 .parent = &clk_p,
457 .enable = s5pc100_clk_d13_ctrl,
458 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
459 }, {
460 .name = "gpio",
461 .id = -1,
462 .parent = &clk_p,
463 .enable = s5pc100_clk_d13_ctrl,
464 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
465 }, {
466 .name = "apc",
467 .id = -1,
468 .parent = &clk_p,
469 .enable = s5pc100_clk_d13_ctrl,
470 .ctrlbit = S5PC100_CLKGATE_D13_APC,
471 }, {
472 .name = "iec",
473 .id = -1,
474 .parent = &clk_p,
475 .enable = s5pc100_clk_d13_ctrl,
476 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
477 }, {
478 .name = "timers",
479 .id = -1,
480 .parent = &clk_p,
481 .enable = s5pc100_clk_d13_ctrl,
482 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
483 }, {
484 .name = "systimer",
485 .id = -1,
486 .parent = &clk_p,
487 .enable = s5pc100_clk_d13_ctrl,
488 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
489 }, {
490 .name = "watchdog",
491 .id = -1,
492 .parent = &clk_p,
493 .enable = s5pc100_clk_d13_ctrl,
494 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
495 }, {
496 .name = "rtc",
497 .id = -1,
498 .parent = &clk_p,
499 .enable = s5pc100_clk_d13_ctrl,
500 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
501 },
502
503 /* Connectivity (D1_4) devices */
504 {
505 .name = "uart",
506 .id = 0,
507 .parent = &clk_p,
508 .enable = s5pc100_clk_d14_ctrl,
509 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
510 }, {
511 .name = "uart",
512 .id = 1,
513 .parent = &clk_p,
514 .enable = s5pc100_clk_d14_ctrl,
515 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
516 }, {
517 .name = "uart",
518 .id = 2,
519 .parent = &clk_p,
520 .enable = s5pc100_clk_d14_ctrl,
521 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
522 }, {
523 .name = "uart",
524 .id = 3,
525 .parent = &clk_p,
526 .enable = s5pc100_clk_d14_ctrl,
527 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
528 }, {
529 .name = "i2c",
530 .id = -1,
531 .parent = &clk_p,
532 .enable = s5pc100_clk_d14_ctrl,
533 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
534 }, {
535 .name = "hdmi-i2c",
536 .id = -1,
537 .parent = &clk_p,
538 .enable = s5pc100_clk_d14_ctrl,
539 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
540 }, {
541 .name = "spi",
542 .id = 0,
543 .parent = &clk_p,
544 .enable = s5pc100_clk_d14_ctrl,
545 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
546 }, {
547 .name = "spi",
548 .id = 1,
549 .parent = &clk_p,
550 .enable = s5pc100_clk_d14_ctrl,
551 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
552 }, {
553 .name = "spi",
554 .id = 2,
555 .parent = &clk_p,
556 .enable = s5pc100_clk_d14_ctrl,
557 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
558 }, {
559 .name = "irda",
560 .id = -1,
561 .parent = &clk_p,
562 .enable = s5pc100_clk_d14_ctrl,
563 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
564 }, {
565 .name = "hsitx",
566 .id = -1,
567 .parent = &clk_p,
568 .enable = s5pc100_clk_d14_ctrl,
569 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
570 }, {
571 .name = "hsirx",
572 .id = -1,
573 .parent = &clk_p,
574 .enable = s5pc100_clk_d14_ctrl,
575 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
576 },
577
578 /* Audio (D1_5) devices */
579 {
580 .name = "iis",
581 .id = 0,
582 .parent = &clk_p,
583 .enable = s5pc100_clk_d15_ctrl,
584 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
585 }, {
586 .name = "iis",
587 .id = 1,
588 .parent = &clk_p,
589 .enable = s5pc100_clk_d15_ctrl,
590 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
591 }, {
592 .name = "iis",
593 .id = 2,
594 .parent = &clk_p,
595 .enable = s5pc100_clk_d15_ctrl,
596 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
597 }, {
598 .name = "ac97",
599 .id = -1,
600 .parent = &clk_p,
601 .enable = s5pc100_clk_d15_ctrl,
602 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
603 }, {
604 .name = "pcm",
605 .id = 0,
606 .parent = &clk_p,
607 .enable = s5pc100_clk_d15_ctrl,
608 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
609 }, {
610 .name = "pcm",
611 .id = 1,
612 .parent = &clk_p,
613 .enable = s5pc100_clk_d15_ctrl,
614 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
615 }, {
616 .name = "spdif",
617 .id = -1,
618 .parent = &clk_p,
619 .enable = s5pc100_clk_d15_ctrl,
620 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
621 }, {
622 .name = "adc",
623 .id = -1,
624 .parent = &clk_p,
625 .enable = s5pc100_clk_d15_ctrl,
626 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
627 }, {
628 .name = "cg",
629 .id = -1,
630 .parent = &clk_p,
631 .enable = s5pc100_clk_d15_ctrl,
632 .ctrlbit = S5PC100_CLKGATE_D15_CG,
633 },
634
635 /* Audio (D2_0) devices: all disabled */
636
637 /* Special Clocks 0 */
638 {
639 .name = "sclk_hpm",
640 .id = -1,
641 .parent = NULL,
642 .enable = s5pc100_sclk0_ctrl,
643 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
644 }, {
645 .name = "sclk_onenand",
646 .id = -1,
647 .parent = NULL,
648 .enable = s5pc100_sclk0_ctrl,
649 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
650 }, {
651 .name = "spi_48",
652 .id = 0,
653 .parent = &clk_48m,
654 .enable = s5pc100_sclk0_ctrl,
655 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
656 }, {
657 .name = "spi_48",
658 .id = 1,
659 .parent = &clk_48m,
660 .enable = s5pc100_sclk0_ctrl,
661 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
662 }, {
663 .name = "spi_48",
664 .id = 2,
665 .parent = &clk_48m,
666 .enable = s5pc100_sclk0_ctrl,
667 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
668 }, {
669 .name = "mmc_48",
670 .id = 0,
671 .parent = &clk_48m,
672 .enable = s5pc100_sclk0_ctrl,
673 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
674 }, {
675 .name = "mmc_48",
676 .id = 1,
677 .parent = &clk_48m,
678 .enable = s5pc100_sclk0_ctrl,
679 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
680 }, {
681 .name = "mmc_48",
682 .id = 2,
683 .parent = &clk_48m,
684 .enable = s5pc100_sclk0_ctrl,
685 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
686 },
687 /* Special Clocks 1 */
688};
689
690static struct clk *clks[] __initdata = {
691 &clk_ext,
692 &clk_epll,
693 &clk_27m,
694 &clk_48m,
695 &clk_54m,
696};
697
698void __init s5pc1xx_register_clocks(void)
699{
700 struct clk *clkp;
701 int ret;
702 int ptr;
703 int size;
704
705 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
706
Ben Dooks1d9f13c2010-01-06 01:21:38 +0900[diff] [blame^]707 s3c_register_clocks(s5pc100_init_clocks,
708 ARRAY_SIZE(s5pc100_init_clocks));
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]709
710 clkp = s5pc100_init_clocks_disable;
711 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
712
713 for (ptr = 0; ptr < size; ptr++, clkp++) {
714 ret = s3c24xx_register_clock(clkp);
715 if (ret < 0) {
716 printk(KERN_ERR "Failed to register clock %s (%d)\n",
717 clkp->name, ret);
718 }
719
720 (clkp->enable)(clkp, 0);
721 }
722
723 s3c_pwmclk_init();
724}