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Shuzhen Wangce650862011-08-17 15:27:01 -07001#ifndef __MSM_ISP_H__
2#define __MSM_ISP_H__
3
4/* ISP message IDs */
5#define MSG_ID_RESET_ACK 0
6#define MSG_ID_START_ACK 1
7#define MSG_ID_STOP_ACK 2
8#define MSG_ID_UPDATE_ACK 3
9#define MSG_ID_OUTPUT_P 4
10#define MSG_ID_OUTPUT_T 5
11#define MSG_ID_OUTPUT_S 6
12#define MSG_ID_OUTPUT_V 7
13#define MSG_ID_SNAPSHOT_DONE 8
14#define MSG_ID_STATS_AEC 9
15#define MSG_ID_STATS_AF 10
16#define MSG_ID_STATS_AWB 11
17#define MSG_ID_STATS_RS 12
18#define MSG_ID_STATS_CS 13
19#define MSG_ID_STATS_IHIST 14
20#define MSG_ID_STATS_SKIN 15
21#define MSG_ID_EPOCH1 16
22#define MSG_ID_EPOCH2 17
23#define MSG_ID_SYNC_TIMER0_DONE 18
24#define MSG_ID_SYNC_TIMER1_DONE 19
25#define MSG_ID_SYNC_TIMER2_DONE 20
26#define MSG_ID_ASYNC_TIMER0_DONE 21
27#define MSG_ID_ASYNC_TIMER1_DONE 22
28#define MSG_ID_ASYNC_TIMER2_DONE 23
29#define MSG_ID_ASYNC_TIMER3_DONE 24
30#define MSG_ID_AE_OVERFLOW 25
31#define MSG_ID_AF_OVERFLOW 26
32#define MSG_ID_AWB_OVERFLOW 27
33#define MSG_ID_RS_OVERFLOW 28
34#define MSG_ID_CS_OVERFLOW 29
35#define MSG_ID_IHIST_OVERFLOW 30
36#define MSG_ID_SKIN_OVERFLOW 31
37#define MSG_ID_AXI_ERROR 32
38#define MSG_ID_CAMIF_OVERFLOW 33
39#define MSG_ID_VIOLATION 34
40#define MSG_ID_CAMIF_ERROR 35
41#define MSG_ID_BUS_OVERFLOW 36
42#define MSG_ID_SOF_ACK 37
43#define MSG_ID_STOP_REC_ACK 38
44
45/* ISP command IDs */
46#define VFE_CMD_DUMMY_0 0
47#define VFE_CMD_SET_CLK 1
48#define VFE_CMD_RESET 2
49#define VFE_CMD_START 3
50#define VFE_CMD_TEST_GEN_START 4
51#define VFE_CMD_OPERATION_CFG 5
52#define VFE_CMD_AXI_OUT_CFG 6
53#define VFE_CMD_CAMIF_CFG 7
54#define VFE_CMD_AXI_INPUT_CFG 8
55#define VFE_CMD_BLACK_LEVEL_CFG 9
Ujwal Pateledcbdcc2011-08-24 09:14:14 -070056#define VFE_CMD_MESH_ROLL_OFF_CFG 10
Shuzhen Wangce650862011-08-17 15:27:01 -070057#define VFE_CMD_DEMUX_CFG 11
58#define VFE_CMD_FOV_CFG 12
59#define VFE_CMD_MAIN_SCALER_CFG 13
60#define VFE_CMD_WB_CFG 14
61#define VFE_CMD_COLOR_COR_CFG 15
62#define VFE_CMD_RGB_G_CFG 16
63#define VFE_CMD_LA_CFG 17
64#define VFE_CMD_CHROMA_EN_CFG 18
65#define VFE_CMD_CHROMA_SUP_CFG 19
66#define VFE_CMD_MCE_CFG 20
67#define VFE_CMD_SK_ENHAN_CFG 21
68#define VFE_CMD_ASF_CFG 22
69#define VFE_CMD_S2Y_CFG 23
70#define VFE_CMD_S2CbCr_CFG 24
71#define VFE_CMD_CHROMA_SUBS_CFG 25
72#define VFE_CMD_OUT_CLAMP_CFG 26
73#define VFE_CMD_FRAME_SKIP_CFG 27
74#define VFE_CMD_DUMMY_1 28
75#define VFE_CMD_DUMMY_2 29
76#define VFE_CMD_DUMMY_3 30
77#define VFE_CMD_UPDATE 31
78#define VFE_CMD_BL_LVL_UPDATE 32
79#define VFE_CMD_DEMUX_UPDATE 33
80#define VFE_CMD_FOV_UPDATE 34
81#define VFE_CMD_MAIN_SCALER_UPDATE 35
82#define VFE_CMD_WB_UPDATE 36
83#define VFE_CMD_COLOR_COR_UPDATE 37
84#define VFE_CMD_RGB_G_UPDATE 38
85#define VFE_CMD_LA_UPDATE 39
86#define VFE_CMD_CHROMA_EN_UPDATE 40
87#define VFE_CMD_CHROMA_SUP_UPDATE 41
88#define VFE_CMD_MCE_UPDATE 42
89#define VFE_CMD_SK_ENHAN_UPDATE 43
90#define VFE_CMD_S2CbCr_UPDATE 44
91#define VFE_CMD_S2Y_UPDATE 45
92#define VFE_CMD_ASF_UPDATE 46
93#define VFE_CMD_FRAME_SKIP_UPDATE 47
94#define VFE_CMD_CAMIF_FRAME_UPDATE 48
95#define VFE_CMD_STATS_AF_UPDATE 49
96#define VFE_CMD_STATS_AE_UPDATE 50
97#define VFE_CMD_STATS_AWB_UPDATE 51
98#define VFE_CMD_STATS_RS_UPDATE 52
99#define VFE_CMD_STATS_CS_UPDATE 53
100#define VFE_CMD_STATS_SKIN_UPDATE 54
101#define VFE_CMD_STATS_IHIST_UPDATE 55
102#define VFE_CMD_DUMMY_4 56
103#define VFE_CMD_EPOCH1_ACK 57
104#define VFE_CMD_EPOCH2_ACK 58
105#define VFE_CMD_START_RECORDING 59
106#define VFE_CMD_STOP_RECORDING 60
107#define VFE_CMD_DUMMY_5 61
108#define VFE_CMD_DUMMY_6 62
109#define VFE_CMD_CAPTURE 63
110#define VFE_CMD_DUMMY_7 64
111#define VFE_CMD_STOP 65
112#define VFE_CMD_GET_HW_VERSION 66
113#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
114#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
115#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
116#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
117#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
118#define VFE_CMD_RAW_OUT_BUF_ENQ 72
119#define VFE_CMD_RAW_IN_BUF_ENQ 73
120#define VFE_CMD_STATS_AF_ENQ 74
121#define VFE_CMD_STATS_AE_ENQ 75
122#define VFE_CMD_STATS_AWB_ENQ 76
123#define VFE_CMD_STATS_RS_ENQ 77
124#define VFE_CMD_STATS_CS_ENQ 78
125#define VFE_CMD_STATS_SKIN_ENQ 79
126#define VFE_CMD_STATS_IHIST_ENQ 80
127#define VFE_CMD_DUMMY_8 81
128#define VFE_CMD_JPEG_ENC_CFG 82
129#define VFE_CMD_DUMMY_9 83
130#define VFE_CMD_STATS_AF_START 84
131#define VFE_CMD_STATS_AF_STOP 85
132#define VFE_CMD_STATS_AE_START 86
133#define VFE_CMD_STATS_AE_STOP 87
134#define VFE_CMD_STATS_AWB_START 88
135#define VFE_CMD_STATS_AWB_STOP 89
136#define VFE_CMD_STATS_RS_START 90
137#define VFE_CMD_STATS_RS_STOP 91
138#define VFE_CMD_STATS_CS_START 92
139#define VFE_CMD_STATS_CS_STOP 93
140#define VFE_CMD_STATS_SKIN_START 94
141#define VFE_CMD_STATS_SKIN_STOP 95
142#define VFE_CMD_STATS_IHIST_START 96
143#define VFE_CMD_STATS_IHIST_STOP 97
144#define VFE_CMD_DUMMY_10 98
145#define VFE_CMD_SYNC_TIMER_SETTING 99
146#define VFE_CMD_ASYNC_TIMER_SETTING 100
147#define VFE_CMD_LIVESHOT 101
148#define VFE_CMD_LA_SETUP 102
149#define VFE_CMD_LINEARIZATION_CFG 103
150#define VFE_CMD_DEMOSAICV3 104
151#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
152#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
153#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
154#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
155#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
156#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
157#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
158#define VFE_CMD_XBAR_CFG 112
Ujwal Patel1fe4c9c2011-10-07 12:19:52 -0700159#define VFE_CMD_MODULE_CFG 113
Shuzhen Wangce650862011-08-17 15:27:01 -0700160#define VFE_CMD_ZSL 114
161#define VFE_CMD_LINEARIZATION_UPDATE 115
162#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
163#define VFE_CMD_CLF_CFG 117
164#define VFE_CMD_CLF_LUMA_UPDATE 118
165#define VFE_CMD_CLF_CHROMA_UPDATE 119
Ujwal Pateledcbdcc2011-08-24 09:14:14 -0700166#define VFE_CMD_PCA_ROLL_OFF_CFG 120
167#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
Shuzhen Wangce650862011-08-17 15:27:01 -0700168
Shuzhen Wang6b0f3322011-08-26 12:14:43 -0700169struct msm_isp_cmd {
170 int32_t id;
171 uint16_t length;
172 void *value;
173};
174
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700175
176#define VPE_CMD_DUMMY_0 0
177#define VPE_CMD_INIT 1
178#define VPE_CMD_DEINIT 2
179#define VPE_CMD_ENABLE 3
180#define VPE_CMD_DISABLE 4
181#define VPE_CMD_RESET 5
182#define VPE_CMD_FLUSH 6
183#define VPE_CMD_OPERATION_MODE_CFG 7
184#define VPE_CMD_INPUT_PLANE_CFG 8
185#define VPE_CMD_OUTPUT_PLANE_CFG 9
186#define VPE_CMD_INPUT_PLANE_UPDATE 10
187#define VPE_CMD_SCALE_CFG_TYPE 11
188#define VPE_CMD_DIS_OFFSET_CFG 12
189#define VPE_CMD_ZOOM 13
190
191#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */
192#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */
193#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */
194
195#define MCTL_CMD_DUMMY_0 0 /* not used */
196#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */
197#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */
198#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */
199#define MCTL_CMD_DIVERT_FRAME_PP_DONE 4 /* pp done. buf send to app */
200
201/* event typese sending to MCTL PP module */
202#define MCTL_PP_EVENT_NOTUSED 0
203#define MCTL_PP_EVENT_CMD_ACK 1
204
205#define VPE_OPERATION_MODE_CFG_LEN 8
206#define VPE_INPUT_PLANE_CFG_LEN 24
207#define VPE_OUTPUT_PLANE_CFG_LEN 24
208#define VPE_INPUT_PLANE_UPDATE_LEN 12
209#define VPE_SCALER_CONFIG_LEN 260
210#define VPE_DIS_OFFSET_CFG_LEN 12
211
212struct msm_vpe_op_mode_cfg {
213 uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
214};
215
216struct msm_vpe_input_plane_cfg {
217 uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
218};
219
220struct msm_vpe_output_plane_cfg {
221 uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
222};
223
224struct msm_vpe_input_plane_update_cfg {
225 uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
226};
227
228struct msm_vpe_scaler_cfg {
229 uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
230};
231
232struct msm_vpe_dis_offset_cfg {
233 uint8_t dis_offset_cfg[VPE_DIS_OFFSET_CFG_LEN];
234};
235
236struct msm_vpe_flush_frame_buffer {
237 uint32_t src_buf_handle;
238 uint32_t dest_buf_handle;
239 int path;
240};
241
242struct msm_mctl_pp_frame_buffer {
243 uint32_t buf_handle;
244 int path;
245};
246struct msm_mctl_pp_divert_pp {
247 int path;
248};
249struct msm_vpe_clock_rate {
250 uint32_t rate;
251};
252struct msm_pp_crop {
253 uint32_t src_x;
254 uint32_t src_y;
255 uint32_t src_w;
256 uint32_t src_h;
257 uint32_t dst_x;
258 uint32_t dst_y;
259 uint32_t dst_w;
260 uint32_t dst_h;
261 uint8_t update_flag;
262};
263#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0)
264#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1)
265
266struct msm_mctl_pp_frame_cmd {
267 uint32_t cookie;
268 uint8_t vpe_output_action;
269 uint32_t src_buf_handle;
270 uint32_t dest_buf_handle;
271 struct msm_pp_crop crop;
272 int path;
273 /* TBD: 3D related */
274};
275
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700276struct msm_pp_frame_sp {
277 unsigned long phy_addr;
278 uint32_t y_off;
279 uint32_t cbcr_off;
280 uint32_t length;
281 int32_t fd;
282 uint32_t addr_offset;
283};
284
285struct msm_pp_frame_mp {
286 unsigned long phy_addr;
287 uint32_t data_offset;
288 uint32_t length;
289 int32_t fd;
290 uint32_t addr_offset;
291};
292
293struct msm_pp_frame {
294 uint32_t handle;
295 uint32_t frame_id;
296 unsigned short image_type;
297 unsigned short num_planes; /* 1 for sp */
298 struct timeval timestamp;
299 union {
300 struct msm_pp_frame_sp sp;
301 };
302};
303
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700304#endif /*__MSM_ISP_H__*/
305