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Eilon Greenstein34f80b02008-06-23 20:33:01 -07001/* bnx2x_main.c: Broadcom Everest network driver.
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002 *
Vladislav Zolotarov3359fce2010-02-17 13:35:01 -08003 * Copyright (c) 2007-2010 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
Eilon Greenstein24e3fce2008-06-12 14:30:28 -07009 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
Eilon Greensteinca003922009-08-12 22:53:28 -070013 * Slowpath and fastpath rework by Vladislav Zolotarov
Eliezer Tamirc14423f2008-02-28 11:49:42 -080014 * Statistics and Link management by Yitchak Gertner
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020015 *
16 */
17
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020018#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/kernel.h>
21#include <linux/device.h> /* for dev_info() */
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
26#include <linux/vmalloc.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/dma-mapping.h>
34#include <linux/bitops.h>
35#include <linux/irq.h>
36#include <linux/delay.h>
37#include <asm/byteorder.h>
38#include <linux/time.h>
39#include <linux/ethtool.h>
40#include <linux/mii.h>
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080041#include <linux/if_vlan.h>
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020042#include <net/ip.h>
43#include <net/tcp.h>
44#include <net/checksum.h>
Eilon Greenstein34f80b02008-06-23 20:33:01 -070045#include <net/ip6_checksum.h>
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020046#include <linux/workqueue.h>
47#include <linux/crc32.h>
Eilon Greenstein34f80b02008-06-23 20:33:01 -070048#include <linux/crc32c.h>
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020049#include <linux/prefetch.h>
50#include <linux/zlib.h>
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020051#include <linux/io.h>
Ben Hutchings45229b42009-11-07 11:53:39 +000052#include <linux/stringify.h>
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020053
Eilon Greenstein359d8b12009-02-12 08:38:25 +000054
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020055#include "bnx2x.h"
56#include "bnx2x_init.h"
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070057#include "bnx2x_init_ops.h"
Eilon Greenstein0a64ea52009-03-02 08:01:12 +000058#include "bnx2x_dump.h"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020059
Dmitry Kravkov4fd89b72010-04-01 19:45:34 -070060#define DRV_MODULE_VERSION "1.52.1-8"
61#define DRV_MODULE_RELDATE "2010/04/01"
Eilon Greenstein34f80b02008-06-23 20:33:01 -070062#define BNX2X_BC_VER 0x040200
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020063
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070064#include <linux/firmware.h>
65#include "bnx2x_fw_file_hdr.h"
66/* FW files */
Ben Hutchings45229b42009-11-07 11:53:39 +000067#define FW_FILE_VERSION \
68 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
69 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
70 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
71 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
72#define FW_FILE_NAME_E1 "bnx2x-e1-" FW_FILE_VERSION ".fw"
73#define FW_FILE_NAME_E1H "bnx2x-e1h-" FW_FILE_VERSION ".fw"
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070074
Eilon Greenstein34f80b02008-06-23 20:33:01 -070075/* Time in jiffies before concluding the transmitter is hung */
76#define TX_TIMEOUT (5*HZ)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020077
Andrew Morton53a10562008-02-09 23:16:41 -080078static char version[] __devinitdata =
Eilon Greenstein34f80b02008-06-23 20:33:01 -070079 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020080 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
81
Eilon Greenstein24e3fce2008-06-12 14:30:28 -070082MODULE_AUTHOR("Eliezer Tamir");
Eilon Greensteine47d7e62009-01-14 06:44:28 +000083MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020084MODULE_LICENSE("GPL");
85MODULE_VERSION(DRV_MODULE_VERSION);
Ben Hutchings45229b42009-11-07 11:53:39 +000086MODULE_FIRMWARE(FW_FILE_NAME_E1);
87MODULE_FIRMWARE(FW_FILE_NAME_E1H);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020088
Eilon Greenstein555f6c72009-02-12 08:36:11 +000089static int multi_mode = 1;
90module_param(multi_mode, int, 0);
Eilon Greensteinca003922009-08-12 22:53:28 -070091MODULE_PARM_DESC(multi_mode, " Multi queue mode "
92 "(0 Disable; 1 Enable (default))");
93
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000094static int num_queues;
95module_param(num_queues, int, 0);
96MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
97 " (default is as a number of CPUs)");
Eilon Greenstein555f6c72009-02-12 08:36:11 +000098
Eilon Greenstein19680c42008-08-13 15:47:33 -070099static int disable_tpa;
Eilon Greenstein19680c42008-08-13 15:47:33 -0700100module_param(disable_tpa, int, 0);
Eilon Greenstein9898f862009-02-12 08:38:27 +0000101MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
Eilon Greenstein8badd272009-02-12 08:36:15 +0000102
103static int int_mode;
104module_param(int_mode, int, 0);
105MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
106
Eilon Greensteina18f5122009-08-12 08:23:26 +0000107static int dropless_fc;
108module_param(dropless_fc, int, 0);
109MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
Eilon Greenstein9898f862009-02-12 08:38:27 +0000111static int poll;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200112module_param(poll, int, 0);
Eilon Greenstein9898f862009-02-12 08:38:27 +0000113MODULE_PARM_DESC(poll, " Use polling (for debug)");
Eilon Greenstein8d5726c2009-02-12 08:37:19 +0000114
115static int mrrs = -1;
116module_param(mrrs, int, 0);
117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
Eilon Greenstein9898f862009-02-12 08:38:27 +0000119static int debug;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200120module_param(debug, int, 0);
Eilon Greenstein9898f862009-02-12 08:38:27 +0000121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
123static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200124
Eilon Greenstein1cf167f2009-01-14 21:22:18 -0800125static struct workqueue_struct *bnx2x_wq;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200126
127enum bnx2x_board_type {
128 BCM57710 = 0,
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700129 BCM57711 = 1,
130 BCM57711E = 2,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200131};
132
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700133/* indexed by board_type, above */
Andrew Morton53a10562008-02-09 23:16:41 -0800134static struct {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200135 char *name;
136} board_info[] __devinitdata = {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700137 { "Broadcom NetXtreme II BCM57710 XGb" },
138 { "Broadcom NetXtreme II BCM57711 XGb" },
139 { "Broadcom NetXtreme II BCM57711E XGb" }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200140};
141
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700142
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000143static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
Eilon Greensteine4ed7112009-08-12 08:24:10 +0000144 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
145 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
146 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200147 { 0 }
148};
149
150MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
151
152/****************************************************************************
153* General service functions
154****************************************************************************/
155
156/* used only at init
157 * locking is done by mcp
158 */
Eilon Greenstein573f2032009-08-12 08:24:14 +0000159void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200160{
161 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
162 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
163 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
164 PCICFG_VENDOR_ID_OFFSET);
165}
166
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200167static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
168{
169 u32 val;
170
171 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
172 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
173 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
174 PCICFG_VENDOR_ID_OFFSET);
175
176 return val;
177}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200178
179static const u32 dmae_reg_go_c[] = {
180 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
181 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
182 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
183 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
184};
185
186/* copy command into DMAE command memory and set DMAE command go */
187static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
188 int idx)
189{
190 u32 cmd_offset;
191 int i;
192
193 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
194 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
195 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
196
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700197 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
198 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200199 }
200 REG_WR(bp, dmae_reg_go_c[idx], 1);
201}
202
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700203void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
204 u32 len32)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200205{
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000206 struct dmae_command dmae;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200207 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700208 int cnt = 200;
209
210 if (!bp->dmae_ready) {
211 u32 *data = bnx2x_sp(bp, wb_data[0]);
212
213 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
214 " using indirect\n", dst_addr, len32);
215 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
216 return;
217 }
218
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000219 memset(&dmae, 0, sizeof(struct dmae_command));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200220
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000221 dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
222 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
223 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200224#ifdef __BIG_ENDIAN
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000225 DMAE_CMD_ENDIANITY_B_DW_SWAP |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200226#else
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000227 DMAE_CMD_ENDIANITY_DW_SWAP |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200228#endif
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000229 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
230 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
231 dmae.src_addr_lo = U64_LO(dma_addr);
232 dmae.src_addr_hi = U64_HI(dma_addr);
233 dmae.dst_addr_lo = dst_addr >> 2;
234 dmae.dst_addr_hi = 0;
235 dmae.len = len32;
236 dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
237 dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
238 dmae.comp_val = DMAE_COMP_VAL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200239
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000240 DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200241 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
242 "dst_addr [%x:%08x (%08x)]\n"
243 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000244 dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
245 dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, dst_addr,
246 dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700247 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200248 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
249 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200250
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000251 mutex_lock(&bp->dmae_mutex);
252
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200253 *wb_comp = 0;
254
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000255 bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200256
257 udelay(5);
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700258
259 while (*wb_comp != DMAE_COMP_VAL) {
260 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
261
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700262 if (!cnt) {
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000263 BNX2X_ERR("DMAE timeout!\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200264 break;
265 }
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700266 cnt--;
Yitchak Gertner12469402008-08-13 15:52:08 -0700267 /* adjust delay for emulation/FPGA */
268 if (CHIP_REV_IS_SLOW(bp))
269 msleep(100);
270 else
271 udelay(5);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200272 }
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700273
274 mutex_unlock(&bp->dmae_mutex);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200275}
276
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700277void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200278{
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000279 struct dmae_command dmae;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200280 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700281 int cnt = 200;
282
283 if (!bp->dmae_ready) {
284 u32 *data = bnx2x_sp(bp, wb_data[0]);
285 int i;
286
287 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
288 " using indirect\n", src_addr, len32);
289 for (i = 0; i < len32; i++)
290 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
291 return;
292 }
293
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000294 memset(&dmae, 0, sizeof(struct dmae_command));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200295
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000296 dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
297 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
298 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200299#ifdef __BIG_ENDIAN
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000300 DMAE_CMD_ENDIANITY_B_DW_SWAP |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200301#else
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000302 DMAE_CMD_ENDIANITY_DW_SWAP |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200303#endif
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000304 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
305 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
306 dmae.src_addr_lo = src_addr >> 2;
307 dmae.src_addr_hi = 0;
308 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
309 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
310 dmae.len = len32;
311 dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
312 dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
313 dmae.comp_val = DMAE_COMP_VAL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200314
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000315 DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200316 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
317 "dst_addr [%x:%08x (%08x)]\n"
318 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000319 dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
320 dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, src_addr,
321 dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200322
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000323 mutex_lock(&bp->dmae_mutex);
324
325 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200326 *wb_comp = 0;
327
Eilon Greenstein5ff7b6d2009-08-12 08:23:44 +0000328 bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200329
330 udelay(5);
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700331
332 while (*wb_comp != DMAE_COMP_VAL) {
333
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700334 if (!cnt) {
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000335 BNX2X_ERR("DMAE timeout!\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200336 break;
337 }
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700338 cnt--;
Yitchak Gertner12469402008-08-13 15:52:08 -0700339 /* adjust delay for emulation/FPGA */
340 if (CHIP_REV_IS_SLOW(bp))
341 msleep(100);
342 else
343 udelay(5);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200344 }
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700345 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200346 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
347 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700348
349 mutex_unlock(&bp->dmae_mutex);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200350}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200351
Eilon Greenstein573f2032009-08-12 08:24:14 +0000352void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
353 u32 addr, u32 len)
354{
Vladislav Zolotarov02e3c6c2010-04-19 01:13:33 +0000355 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
Eilon Greenstein573f2032009-08-12 08:24:14 +0000356 int offset = 0;
357
Vladislav Zolotarov02e3c6c2010-04-19 01:13:33 +0000358 while (len > dmae_wr_max) {
Eilon Greenstein573f2032009-08-12 08:24:14 +0000359 bnx2x_write_dmae(bp, phys_addr + offset,
Vladislav Zolotarov02e3c6c2010-04-19 01:13:33 +0000360 addr + offset, dmae_wr_max);
361 offset += dmae_wr_max * 4;
362 len -= dmae_wr_max;
Eilon Greenstein573f2032009-08-12 08:24:14 +0000363 }
364
365 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
366}
367
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700368/* used only for slowpath so not inlined */
369static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
370{
371 u32 wb_write[2];
372
373 wb_write[0] = val_hi;
374 wb_write[1] = val_lo;
375 REG_WR_DMAE(bp, reg, wb_write, 2);
376}
377
378#ifdef USE_WB_RD
379static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
380{
381 u32 wb_data[2];
382
383 REG_RD_DMAE(bp, reg, wb_data, 2);
384
385 return HILO_U64(wb_data[0], wb_data[1]);
386}
387#endif
388
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200389static int bnx2x_mc_assert(struct bnx2x *bp)
390{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200391 char last_idx;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700392 int i, rc = 0;
393 u32 row0, row1, row2, row3;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200394
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700395 /* XSTORM */
396 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
397 XSTORM_ASSERT_LIST_INDEX_OFFSET);
398 if (last_idx)
399 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200400
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700401 /* print the asserts */
402 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200403
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700404 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
405 XSTORM_ASSERT_LIST_OFFSET(i));
406 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
407 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
408 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
409 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
410 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
411 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200412
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700413 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
414 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
415 " 0x%08x 0x%08x 0x%08x\n",
416 i, row3, row2, row1, row0);
417 rc++;
418 } else {
419 break;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200420 }
421 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700422
423 /* TSTORM */
424 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
425 TSTORM_ASSERT_LIST_INDEX_OFFSET);
426 if (last_idx)
427 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
428
429 /* print the asserts */
430 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
431
432 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
433 TSTORM_ASSERT_LIST_OFFSET(i));
434 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
435 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
436 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
437 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
438 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
439 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
440
441 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
442 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
443 " 0x%08x 0x%08x 0x%08x\n",
444 i, row3, row2, row1, row0);
445 rc++;
446 } else {
447 break;
448 }
449 }
450
451 /* CSTORM */
452 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
453 CSTORM_ASSERT_LIST_INDEX_OFFSET);
454 if (last_idx)
455 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
456
457 /* print the asserts */
458 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
459
460 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
461 CSTORM_ASSERT_LIST_OFFSET(i));
462 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
463 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
464 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
465 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
466 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
467 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
468
469 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
470 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
471 " 0x%08x 0x%08x 0x%08x\n",
472 i, row3, row2, row1, row0);
473 rc++;
474 } else {
475 break;
476 }
477 }
478
479 /* USTORM */
480 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
481 USTORM_ASSERT_LIST_INDEX_OFFSET);
482 if (last_idx)
483 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
484
485 /* print the asserts */
486 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
487
488 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
489 USTORM_ASSERT_LIST_OFFSET(i));
490 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
491 USTORM_ASSERT_LIST_OFFSET(i) + 4);
492 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
493 USTORM_ASSERT_LIST_OFFSET(i) + 8);
494 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
495 USTORM_ASSERT_LIST_OFFSET(i) + 12);
496
497 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
498 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
499 " 0x%08x 0x%08x 0x%08x\n",
500 i, row3, row2, row1, row0);
501 rc++;
502 } else {
503 break;
504 }
505 }
506
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200507 return rc;
508}
Eliezer Tamirc14423f2008-02-28 11:49:42 -0800509
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200510static void bnx2x_fw_dump(struct bnx2x *bp)
511{
512 u32 mark, offset;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +0000513 __be32 data[9];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200514 int word;
515
Vladislav Zolotarov2145a922010-04-19 01:13:49 +0000516 if (BP_NOMCP(bp)) {
517 BNX2X_ERR("NO MCP - can not dump\n");
518 return;
519 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200520 mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
Eliezer Tamir49d66772008-02-28 11:53:13 -0800521 mark = ((mark + 0x3) & ~0x3);
Joe Perches7995c642010-02-17 15:01:52 +0000522 pr_err("begin fw dump (mark 0x%x)\n", mark);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200523
Joe Perches7995c642010-02-17 15:01:52 +0000524 pr_err("");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200525 for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
526 for (word = 0; word < 8; word++)
527 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
528 offset + 4*word));
529 data[8] = 0x0;
Joe Perches7995c642010-02-17 15:01:52 +0000530 pr_cont("%s", (char *)data);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200531 }
532 for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
533 for (word = 0; word < 8; word++)
534 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
535 offset + 4*word));
536 data[8] = 0x0;
Joe Perches7995c642010-02-17 15:01:52 +0000537 pr_cont("%s", (char *)data);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200538 }
Joe Perches7995c642010-02-17 15:01:52 +0000539 pr_err("end of fw dump\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200540}
541
542static void bnx2x_panic_dump(struct bnx2x *bp)
543{
544 int i;
545 u16 j, start, end;
546
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700547 bp->stats_state = STATS_STATE_DISABLED;
548 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
549
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200550 BNX2X_ERR("begin crash dump -----------------\n");
551
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000552 /* Indices */
553 /* Common */
554 BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)"
555 " def_t_idx(%u) def_att_idx(%u) attn_state(%u)"
556 " spq_prod_idx(%u)\n",
557 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
558 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
559
560 /* Rx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000561 for_each_queue(bp, i) {
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000562 struct bnx2x_fastpath *fp = &bp->fp[i];
563
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000564 BNX2X_ERR("fp%d: rx_bd_prod(%x) rx_bd_cons(%x)"
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000565 " *rx_bd_cons_sb(%x) rx_comp_prod(%x)"
566 " rx_comp_cons(%x) *rx_cons_sb(%x)\n",
567 i, fp->rx_bd_prod, fp->rx_bd_cons,
568 le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
569 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000570 BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)"
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000571 " fp_u_idx(%x) *sb_u_idx(%x)\n",
572 fp->rx_sge_prod, fp->last_max_sge,
573 le16_to_cpu(fp->fp_u_idx),
574 fp->status_blk->u_status_block.status_block_index);
575 }
576
577 /* Tx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000578 for_each_queue(bp, i) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200579 struct bnx2x_fastpath *fp = &bp->fp[i];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200580
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000581 BNX2X_ERR("fp%d: tx_pkt_prod(%x) tx_pkt_cons(%x)"
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700582 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200583 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700584 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000585 BNX2X_ERR(" fp_c_idx(%x) *sb_c_idx(%x)"
Eilon Greensteinca003922009-08-12 22:53:28 -0700586 " tx_db_prod(%x)\n", le16_to_cpu(fp->fp_c_idx),
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700587 fp->status_blk->c_status_block.status_block_index,
Eilon Greensteinca003922009-08-12 22:53:28 -0700588 fp->tx_db.data.prod);
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000589 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200590
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000591 /* Rings */
592 /* Rx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000593 for_each_queue(bp, i) {
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000594 struct bnx2x_fastpath *fp = &bp->fp[i];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200595
596 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
597 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000598 for (j = start; j != end; j = RX_BD(j + 1)) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200599 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
600 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
601
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000602 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
603 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200604 }
605
Eilon Greenstein3196a882008-08-13 15:58:49 -0700606 start = RX_SGE(fp->rx_sge_prod);
607 end = RX_SGE(fp->last_max_sge);
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000608 for (j = start; j != end; j = RX_SGE(j + 1)) {
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700609 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
610 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
611
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000612 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
613 i, j, rx_sge[1], rx_sge[0], sw_page->page);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700614 }
615
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200616 start = RCQ_BD(fp->rx_comp_cons - 10);
617 end = RCQ_BD(fp->rx_comp_cons + 503);
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000618 for (j = start; j != end; j = RCQ_BD(j + 1)) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200619 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
620
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000621 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
622 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200623 }
624 }
625
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000626 /* Tx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000627 for_each_queue(bp, i) {
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000628 struct bnx2x_fastpath *fp = &bp->fp[i];
629
630 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
631 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
632 for (j = start; j != end; j = TX_BD(j + 1)) {
633 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
634
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000635 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
636 i, j, sw_bd->skb, sw_bd->first_bd);
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000637 }
638
639 start = TX_BD(fp->tx_bd_cons - 10);
640 end = TX_BD(fp->tx_bd_cons + 254);
641 for (j = start; j != end; j = TX_BD(j + 1)) {
642 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
643
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +0000644 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
645 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
Eilon Greenstein8440d2b2009-02-12 08:38:22 +0000646 }
647 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200648
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700649 bnx2x_fw_dump(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200650 bnx2x_mc_assert(bp);
651 BNX2X_ERR("end crash dump -----------------\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200652}
653
Eliezer Tamir615f8fd2008-02-28 11:54:54 -0800654static void bnx2x_int_enable(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200655{
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700656 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200657 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
658 u32 val = REG_RD(bp, addr);
659 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
Eilon Greenstein8badd272009-02-12 08:36:15 +0000660 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200661
662 if (msix) {
Eilon Greenstein8badd272009-02-12 08:36:15 +0000663 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
664 HC_CONFIG_0_REG_INT_LINE_EN_0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200665 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
666 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
Eilon Greenstein8badd272009-02-12 08:36:15 +0000667 } else if (msi) {
668 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
669 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
670 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
671 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200672 } else {
673 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
Eliezer Tamir615f8fd2008-02-28 11:54:54 -0800674 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200675 HC_CONFIG_0_REG_INT_LINE_EN_0 |
676 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
Eliezer Tamir615f8fd2008-02-28 11:54:54 -0800677
Eilon Greenstein8badd272009-02-12 08:36:15 +0000678 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
679 val, port, addr);
Eliezer Tamir615f8fd2008-02-28 11:54:54 -0800680
681 REG_WR(bp, addr, val);
682
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200683 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
684 }
685
Eilon Greenstein8badd272009-02-12 08:36:15 +0000686 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
687 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200688
689 REG_WR(bp, addr, val);
Eilon Greenstein37dbbf32009-07-21 05:47:33 +0000690 /*
691 * Ensure that HC_CONFIG is written before leading/trailing edge config
692 */
693 mmiowb();
694 barrier();
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700695
696 if (CHIP_IS_E1H(bp)) {
697 /* init leading/trailing edge */
698 if (IS_E1HMF(bp)) {
Eilon Greenstein8badd272009-02-12 08:36:15 +0000699 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700700 if (bp->port.pmf)
Eilon Greenstein4acac6a2009-02-12 08:36:52 +0000701 /* enable nig and gpio3 attention */
702 val |= 0x1100;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700703 } else
704 val = 0xffff;
705
706 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
707 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
708 }
Eilon Greenstein37dbbf32009-07-21 05:47:33 +0000709
710 /* Make sure that interrupts are indeed enabled from here on */
711 mmiowb();
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200712}
713
Eliezer Tamir615f8fd2008-02-28 11:54:54 -0800714static void bnx2x_int_disable(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200715{
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700716 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200717 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
718 u32 val = REG_RD(bp, addr);
719
720 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
721 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
722 HC_CONFIG_0_REG_INT_LINE_EN_0 |
723 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
724
725 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
726 val, port, addr);
727
Eilon Greenstein8badd272009-02-12 08:36:15 +0000728 /* flush all outstanding writes */
729 mmiowb();
730
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200731 REG_WR(bp, addr, val);
732 if (REG_RD(bp, addr) != val)
733 BNX2X_ERR("BUG! proper val not read from IGU!\n");
734}
735
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -0700736static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200737{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200738 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
Eilon Greenstein8badd272009-02-12 08:36:15 +0000739 int i, offset;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200740
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700741 /* disable interrupt handling */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200742 atomic_inc(&bp->intr_sem);
Eilon Greensteine1510702009-07-21 05:47:41 +0000743 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
744
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -0700745 if (disable_hw)
746 /* prevent the HW from sending interrupts */
747 bnx2x_int_disable(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200748
749 /* make sure all ISRs are done */
750 if (msix) {
Eilon Greenstein8badd272009-02-12 08:36:15 +0000751 synchronize_irq(bp->msix_table[0].vector);
752 offset = 1;
Michael Chan37b091b2009-10-10 13:46:55 +0000753#ifdef BCM_CNIC
754 offset++;
755#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200756 for_each_queue(bp, i)
Eilon Greenstein8badd272009-02-12 08:36:15 +0000757 synchronize_irq(bp->msix_table[i + offset].vector);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200758 } else
759 synchronize_irq(bp->pdev->irq);
760
761 /* make sure sp_task is not running */
Eilon Greenstein1cf167f2009-01-14 21:22:18 -0800762 cancel_delayed_work(&bp->sp_task);
763 flush_workqueue(bnx2x_wq);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200764}
765
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700766/* fast path */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200767
768/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700769 * General service functions
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200770 */
771
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +0000772/* Return true if succeeded to acquire the lock */
773static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
774{
775 u32 lock_status;
776 u32 resource_bit = (1 << resource);
777 int func = BP_FUNC(bp);
778 u32 hw_lock_control_reg;
779
780 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
781
782 /* Validating that the resource is within range */
783 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
784 DP(NETIF_MSG_HW,
785 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
786 resource, HW_LOCK_MAX_RESOURCE_VALUE);
787 return -EINVAL;
788 }
789
790 if (func <= 5)
791 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
792 else
793 hw_lock_control_reg =
794 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
795
796 /* Try to acquire the lock */
797 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
798 lock_status = REG_RD(bp, hw_lock_control_reg);
799 if (lock_status & resource_bit)
800 return true;
801
802 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
803 return false;
804}
805
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700806static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200807 u8 storm, u16 index, u8 op, u8 update)
808{
Eilon Greenstein5c862842008-08-13 15:51:48 -0700809 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
810 COMMAND_REG_INT_ACK);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200811 struct igu_ack_register igu_ack;
812
813 igu_ack.status_block_index = index;
814 igu_ack.sb_id_and_flags =
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700815 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200816 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
817 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
818 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
819
Eilon Greenstein5c862842008-08-13 15:51:48 -0700820 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
821 (*(u32 *)&igu_ack), hc_addr);
822 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
Eilon Greenstein37dbbf32009-07-21 05:47:33 +0000823
824 /* Make sure that ACK is written */
825 mmiowb();
826 barrier();
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200827}
828
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000829static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200830{
831 struct host_status_block *fpsb = fp->status_blk;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200832
833 barrier(); /* status block is written to by the chip */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000834 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
835 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200836}
837
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200838static u16 bnx2x_ack_int(struct bnx2x *bp)
839{
Eilon Greenstein5c862842008-08-13 15:51:48 -0700840 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
841 COMMAND_REG_SIMD_MASK);
842 u32 result = REG_RD(bp, hc_addr);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200843
Eilon Greenstein5c862842008-08-13 15:51:48 -0700844 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
845 result, hc_addr);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200846
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200847 return result;
848}
849
850
851/*
852 * fast path service functions
853 */
854
Vladislav Zolotarove8b5fc52009-01-26 12:36:42 -0800855static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
856{
857 /* Tell compiler that consumer and producer can change */
858 barrier();
859 return (fp->tx_pkt_prod != fp->tx_pkt_cons);
Eilon Greenstein237907c2009-01-14 06:42:44 +0000860}
861
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200862/* free skb in the packet ring at pos idx
863 * return idx of last bd freed
864 */
865static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
866 u16 idx)
867{
868 struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
Eilon Greensteinca003922009-08-12 22:53:28 -0700869 struct eth_tx_start_bd *tx_start_bd;
870 struct eth_tx_bd *tx_data_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200871 struct sk_buff *skb = tx_buf->skb;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700872 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200873 int nbd;
874
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000875 /* prefetch skb end pointer to speedup dev_kfree_skb() */
876 prefetch(&skb->end);
877
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200878 DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n",
879 idx, tx_buf, skb);
880
881 /* unmap first bd */
882 DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
Eilon Greensteinca003922009-08-12 22:53:28 -0700883 tx_start_bd = &fp->tx_desc_ring[bd_idx].start_bd;
FUJITA Tomonori1a983142010-04-04 01:51:03 +0000884 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
Eilon Greensteinca003922009-08-12 22:53:28 -0700885 BD_UNMAP_LEN(tx_start_bd), PCI_DMA_TODEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200886
Eilon Greensteinca003922009-08-12 22:53:28 -0700887 nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200888#ifdef BNX2X_STOP_ON_ERROR
Eilon Greensteinca003922009-08-12 22:53:28 -0700889 if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700890 BNX2X_ERR("BAD nbd!\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200891 bnx2x_panic();
892 }
893#endif
Eilon Greensteinca003922009-08-12 22:53:28 -0700894 new_cons = nbd + tx_buf->first_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200895
Eilon Greensteinca003922009-08-12 22:53:28 -0700896 /* Get the next bd */
897 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
898
899 /* Skip a parse bd... */
900 --nbd;
901 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
902
903 /* ...and the TSO split header bd since they have no mapping */
904 if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
905 --nbd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200906 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200907 }
908
909 /* now free frags */
910 while (nbd > 0) {
911
912 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
Eilon Greensteinca003922009-08-12 22:53:28 -0700913 tx_data_bd = &fp->tx_desc_ring[bd_idx].reg_bd;
FUJITA Tomonori1a983142010-04-04 01:51:03 +0000914 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
915 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200916 if (--nbd)
917 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
918 }
919
920 /* release skb */
Ilpo Järvinen53e5e962008-07-25 21:40:45 -0700921 WARN_ON(!skb);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000922 dev_kfree_skb(skb);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200923 tx_buf->first_bd = 0;
924 tx_buf->skb = NULL;
925
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700926 return new_cons;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200927}
928
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700929static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200930{
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700931 s16 used;
932 u16 prod;
933 u16 cons;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200934
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200935 prod = fp->tx_bd_prod;
936 cons = fp->tx_bd_cons;
937
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700938 /* NUM_TX_RINGS = number of "next-page" entries
939 It will be used as a threshold */
940 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200941
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700942#ifdef BNX2X_STOP_ON_ERROR
Ilpo Järvinen53e5e962008-07-25 21:40:45 -0700943 WARN_ON(used < 0);
944 WARN_ON(used > fp->bp->tx_ring_size);
945 WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700946#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200947
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700948 return (s16)(fp->bp->tx_ring_size) - used;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200949}
950
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000951static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
952{
953 u16 hw_cons;
954
955 /* Tell compiler that status block fields can change */
956 barrier();
957 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
958 return hw_cons != fp->tx_pkt_cons;
959}
960
961static int bnx2x_tx_int(struct bnx2x_fastpath *fp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200962{
963 struct bnx2x *bp = fp->bp;
Eilon Greenstein555f6c72009-02-12 08:36:11 +0000964 struct netdev_queue *txq;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200965 u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200966
967#ifdef BNX2X_STOP_ON_ERROR
968 if (unlikely(bp->panic))
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000969 return -1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200970#endif
971
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +0000972 txq = netdev_get_tx_queue(bp->dev, fp->index);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200973 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
974 sw_cons = fp->tx_pkt_cons;
975
976 while (sw_cons != hw_cons) {
977 u16 pkt_cons;
978
979 pkt_cons = TX_BD(sw_cons);
980
981 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
982
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700983 DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %u\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200984 hw_cons, sw_cons, pkt_cons);
985
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700986/* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200987 rmb();
988 prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
989 }
990*/
991 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
992 sw_cons++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200993 }
994
995 fp->tx_pkt_cons = sw_cons;
996 fp->tx_bd_cons = bd_cons;
997
Vladislav Zolotarovc16cc0b2010-02-28 00:12:02 +0000998 /* Need to make the tx_bd_cons update visible to start_xmit()
999 * before checking for netif_tx_queue_stopped(). Without the
1000 * memory barrier, there is a small possibility that
1001 * start_xmit() will miss it and cause the queue to be stopped
1002 * forever.
1003 */
Stanislaw Gruszka2d99cf12010-03-09 06:55:00 +00001004 smp_mb();
Vladislav Zolotarovc16cc0b2010-02-28 00:12:02 +00001005
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001006 /* TBD need a thresh? */
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001007 if (unlikely(netif_tx_queue_stopped(txq))) {
Vladislav Zolotarovc16cc0b2010-02-28 00:12:02 +00001008 /* Taking tx_lock() is needed to prevent reenabling the queue
1009 * while it's empty. This could have happen if rx_action() gets
1010 * suspended in bnx2x_tx_int() after the condition before
1011 * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
1012 *
1013 * stops the queue->sees fresh tx_bd_cons->releases the queue->
1014 * sends some packets consuming the whole queue again->
1015 * stops the queue
Eilon Greenstein60447352009-03-02 07:59:24 +00001016 */
Vladislav Zolotarovc16cc0b2010-02-28 00:12:02 +00001017
1018 __netif_tx_lock(txq, smp_processor_id());
Eilon Greenstein60447352009-03-02 07:59:24 +00001019
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001020 if ((netif_tx_queue_stopped(txq)) &&
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07001021 (bp->state == BNX2X_STATE_OPEN) &&
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001022 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001023 netif_tx_wake_queue(txq);
Vladislav Zolotarovc16cc0b2010-02-28 00:12:02 +00001024
1025 __netif_tx_unlock(txq);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001026 }
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00001027 return 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001028}
1029
Michael Chan993ac7b2009-10-10 13:46:56 +00001030#ifdef BCM_CNIC
1031static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1032#endif
Eilon Greenstein3196a882008-08-13 15:58:49 -07001033
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001034static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1035 union eth_rx_cqe *rr_cqe)
1036{
1037 struct bnx2x *bp = fp->bp;
1038 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1039 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1040
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001041 DP(BNX2X_MSG_SP,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001042 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
Eilon Greenstein0626b892009-02-12 08:38:14 +00001043 fp->index, cid, command, bp->state,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001044 rr_cqe->ramrod_cqe.ramrod_type);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001045
1046 bp->spq_left++;
1047
Eilon Greenstein0626b892009-02-12 08:38:14 +00001048 if (fp->index) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001049 switch (command | fp->state) {
1050 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
1051 BNX2X_FP_STATE_OPENING):
1052 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
1053 cid);
1054 fp->state = BNX2X_FP_STATE_OPEN;
1055 break;
1056
1057 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1058 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
1059 cid);
1060 fp->state = BNX2X_FP_STATE_HALTED;
1061 break;
1062
1063 default:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001064 BNX2X_ERR("unexpected MC reply (%d) "
1065 "fp->state is %x\n", command, fp->state);
1066 break;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001067 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001068 mb(); /* force bnx2x_wait_ramrod() to see the change */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001069 return;
1070 }
Eliezer Tamirc14423f2008-02-28 11:49:42 -08001071
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001072 switch (command | bp->state) {
1073 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
1074 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
1075 bp->state = BNX2X_STATE_OPEN;
1076 break;
1077
1078 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
1079 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
1080 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
1081 fp->state = BNX2X_FP_STATE_HALTED;
1082 break;
1083
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001084 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001085 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
Eliezer Tamir49d66772008-02-28 11:53:13 -08001086 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001087 break;
1088
Michael Chan993ac7b2009-10-10 13:46:56 +00001089#ifdef BCM_CNIC
1090 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_OPEN):
1091 DP(NETIF_MSG_IFDOWN, "got delete ramrod for CID %d\n", cid);
1092 bnx2x_cnic_cfc_comp(bp, cid);
1093 break;
1094#endif
Eilon Greenstein3196a882008-08-13 15:58:49 -07001095
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001096 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001097 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001098 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
Michael Chane665bfd2009-10-10 13:46:54 +00001099 bp->set_mac_pending--;
1100 smp_wmb();
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001101 break;
1102
Eliezer Tamir49d66772008-02-28 11:53:13 -08001103 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001104 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
Michael Chane665bfd2009-10-10 13:46:54 +00001105 bp->set_mac_pending--;
1106 smp_wmb();
Eliezer Tamir49d66772008-02-28 11:53:13 -08001107 break;
1108
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001109 default:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001110 BNX2X_ERR("unexpected MC reply (%d) bp->state is %x\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001111 command, bp->state);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001112 break;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001113 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001114 mb(); /* force bnx2x_wait_ramrod() to see the change */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001115}
1116
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001117static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
1118 struct bnx2x_fastpath *fp, u16 index)
1119{
1120 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1121 struct page *page = sw_buf->page;
1122 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1123
1124 /* Skip "next page" elements */
1125 if (!page)
1126 return;
1127
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001128 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08001129 SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001130 __free_pages(page, PAGES_PER_SGE_SHIFT);
1131
1132 sw_buf->page = NULL;
1133 sge->addr_hi = 0;
1134 sge->addr_lo = 0;
1135}
1136
1137static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
1138 struct bnx2x_fastpath *fp, int last)
1139{
1140 int i;
1141
1142 for (i = 0; i < last; i++)
1143 bnx2x_free_rx_sge(bp, fp, i);
1144}
1145
1146static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
1147 struct bnx2x_fastpath *fp, u16 index)
1148{
1149 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1150 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1151 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1152 dma_addr_t mapping;
1153
1154 if (unlikely(page == NULL))
1155 return -ENOMEM;
1156
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001157 mapping = dma_map_page(&bp->pdev->dev, page, 0,
1158 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -07001159 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001160 __free_pages(page, PAGES_PER_SGE_SHIFT);
1161 return -ENOMEM;
1162 }
1163
1164 sw_buf->page = page;
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001165 dma_unmap_addr_set(sw_buf, mapping, mapping);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001166
1167 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1168 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1169
1170 return 0;
1171}
1172
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001173static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1174 struct bnx2x_fastpath *fp, u16 index)
1175{
1176 struct sk_buff *skb;
1177 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1178 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1179 dma_addr_t mapping;
1180
1181 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1182 if (unlikely(skb == NULL))
1183 return -ENOMEM;
1184
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001185 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size,
1186 DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -07001187 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001188 dev_kfree_skb(skb);
1189 return -ENOMEM;
1190 }
1191
1192 rx_buf->skb = skb;
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001193 dma_unmap_addr_set(rx_buf, mapping, mapping);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001194
1195 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1196 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1197
1198 return 0;
1199}
1200
1201/* note that we are not allocating a new skb,
1202 * we are just moving one from cons to prod
1203 * we are not creating a new mapping,
1204 * so there is no need to check for dma_mapping_error().
1205 */
1206static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1207 struct sk_buff *skb, u16 cons, u16 prod)
1208{
1209 struct bnx2x *bp = fp->bp;
1210 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1211 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1212 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1213 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1214
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001215 dma_sync_single_for_device(&bp->pdev->dev,
1216 dma_unmap_addr(cons_rx_buf, mapping),
1217 RX_COPY_THRESH, DMA_FROM_DEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001218
1219 prod_rx_buf->skb = cons_rx_buf->skb;
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001220 dma_unmap_addr_set(prod_rx_buf, mapping,
1221 dma_unmap_addr(cons_rx_buf, mapping));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001222 *prod_bd = *cons_bd;
1223}
1224
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001225static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1226 u16 idx)
1227{
1228 u16 last_max = fp->last_max_sge;
1229
1230 if (SUB_S16(idx, last_max) > 0)
1231 fp->last_max_sge = idx;
1232}
1233
1234static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1235{
1236 int i, j;
1237
1238 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1239 int idx = RX_SGE_CNT * i - 1;
1240
1241 for (j = 0; j < 2; j++) {
1242 SGE_MASK_CLEAR_BIT(fp, idx);
1243 idx--;
1244 }
1245 }
1246}
1247
1248static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1249 struct eth_fast_path_rx_cqe *fp_cqe)
1250{
1251 struct bnx2x *bp = fp->bp;
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08001252 u16 sge_len = SGE_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001253 le16_to_cpu(fp_cqe->len_on_bd)) >>
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08001254 SGE_PAGE_SHIFT;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001255 u16 last_max, last_elem, first_elem;
1256 u16 delta = 0;
1257 u16 i;
1258
1259 if (!sge_len)
1260 return;
1261
1262 /* First mark all used pages */
1263 for (i = 0; i < sge_len; i++)
1264 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1265
1266 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1267 sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1268
1269 /* Here we assume that the last SGE index is the biggest */
1270 prefetch((void *)(fp->sge_mask));
1271 bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1272
1273 last_max = RX_SGE(fp->last_max_sge);
1274 last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1275 first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1276
1277 /* If ring is not full */
1278 if (last_elem + 1 != first_elem)
1279 last_elem++;
1280
1281 /* Now update the prod */
1282 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1283 if (likely(fp->sge_mask[i]))
1284 break;
1285
1286 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1287 delta += RX_SGE_MASK_ELEM_SZ;
1288 }
1289
1290 if (delta > 0) {
1291 fp->rx_sge_prod += delta;
1292 /* clear page-end entries */
1293 bnx2x_clear_sge_mask_next_elems(fp);
1294 }
1295
1296 DP(NETIF_MSG_RX_STATUS,
1297 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
1298 fp->last_max_sge, fp->rx_sge_prod);
1299}
1300
1301static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1302{
1303 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1304 memset(fp->sge_mask, 0xff,
1305 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1306
Eilon Greenstein33471622008-08-13 15:59:08 -07001307 /* Clear the two last indices in the page to 1:
1308 these are the indices that correspond to the "next" element,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001309 hence will never be indicated and should be removed from
1310 the calculations. */
1311 bnx2x_clear_sge_mask_next_elems(fp);
1312}
1313
1314static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1315 struct sk_buff *skb, u16 cons, u16 prod)
1316{
1317 struct bnx2x *bp = fp->bp;
1318 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1319 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1320 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1321 dma_addr_t mapping;
1322
1323 /* move empty skb from pool to prod and map it */
1324 prod_rx_buf->skb = fp->tpa_pool[queue].skb;
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001325 mapping = dma_map_single(&bp->pdev->dev, fp->tpa_pool[queue].skb->data,
1326 bp->rx_buf_size, DMA_FROM_DEVICE);
1327 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001328
1329 /* move partial skb from cons to pool (don't unmap yet) */
1330 fp->tpa_pool[queue] = *cons_rx_buf;
1331
1332 /* mark bin state as start - print error if current state != stop */
1333 if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1334 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1335
1336 fp->tpa_state[queue] = BNX2X_TPA_START;
1337
1338 /* point prod_bd to new skb */
1339 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1340 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1341
1342#ifdef BNX2X_STOP_ON_ERROR
1343 fp->tpa_queue_used |= (1 << queue);
1344#ifdef __powerpc64__
1345 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1346#else
1347 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1348#endif
1349 fp->tpa_queue_used);
1350#endif
1351}
1352
1353static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1354 struct sk_buff *skb,
1355 struct eth_fast_path_rx_cqe *fp_cqe,
1356 u16 cqe_idx)
1357{
1358 struct sw_rx_page *rx_pg, old_rx_pg;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001359 u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1360 u32 i, frag_len, frag_size, pages;
1361 int err;
1362 int j;
1363
1364 frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08001365 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001366
1367 /* This is needed in order to enable forwarding support */
1368 if (frag_size)
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08001369 skb_shinfo(skb)->gso_size = min((u32)SGE_PAGE_SIZE,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001370 max(frag_size, (u32)len_on_bd));
1371
1372#ifdef BNX2X_STOP_ON_ERROR
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08001373 if (pages >
1374 min((u32)8, (u32)MAX_SKB_FRAGS) * SGE_PAGE_SIZE * PAGES_PER_SGE) {
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001375 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1376 pages, cqe_idx);
1377 BNX2X_ERR("fp_cqe->pkt_len = %d fp_cqe->len_on_bd = %d\n",
1378 fp_cqe->pkt_len, len_on_bd);
1379 bnx2x_panic();
1380 return -EINVAL;
1381 }
1382#endif
1383
1384 /* Run through the SGL and compose the fragmented skb */
1385 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1386 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1387
1388 /* FW gives the indices of the SGE as if the ring is an array
1389 (meaning that "next" element will consume 2 indices) */
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08001390 frag_len = min(frag_size, (u32)(SGE_PAGE_SIZE*PAGES_PER_SGE));
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001391 rx_pg = &fp->rx_page_ring[sge_idx];
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001392 old_rx_pg = *rx_pg;
1393
1394 /* If we fail to allocate a substitute page, we simply stop
1395 where we are and drop the whole packet */
1396 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1397 if (unlikely(err)) {
Eilon Greensteinde832a52009-02-12 08:36:33 +00001398 fp->eth_q_stats.rx_skb_alloc_failed++;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001399 return err;
1400 }
1401
1402 /* Unmap the page as we r going to pass it to the stack */
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001403 dma_unmap_page(&bp->pdev->dev,
1404 dma_unmap_addr(&old_rx_pg, mapping),
1405 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001406
1407 /* Add one frag and update the appropriate fields in the skb */
1408 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1409
1410 skb->data_len += frag_len;
1411 skb->truesize += frag_len;
1412 skb->len += frag_len;
1413
1414 frag_size -= frag_len;
1415 }
1416
1417 return 0;
1418}
1419
1420static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1421 u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1422 u16 cqe_idx)
1423{
1424 struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1425 struct sk_buff *skb = rx_buf->skb;
1426 /* alloc new skb */
1427 struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1428
1429 /* Unmap skb in the pool anyway, as we are going to change
1430 pool entry status to BNX2X_TPA_STOP even if new skb allocation
1431 fails. */
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001432 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
1433 bp->rx_buf_size, DMA_FROM_DEVICE);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001434
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001435 if (likely(new_skb)) {
Yitchak Gertner66e855f2008-08-13 15:49:05 -07001436 /* fix ip xsum and give it to the stack */
1437 /* (no need to map the new skb) */
Eilon Greenstein0c6671b2009-01-14 21:26:51 -08001438#ifdef BCM_VLAN
1439 int is_vlan_cqe =
1440 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1441 PARSING_FLAGS_VLAN);
1442 int is_not_hwaccel_vlan_cqe =
1443 (is_vlan_cqe && (!(bp->flags & HW_VLAN_RX_FLAG)));
1444#endif
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001445
1446 prefetch(skb);
1447 prefetch(((char *)(skb)) + 128);
1448
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001449#ifdef BNX2X_STOP_ON_ERROR
1450 if (pad + len > bp->rx_buf_size) {
1451 BNX2X_ERR("skb_put is about to fail... "
1452 "pad %d len %d rx_buf_size %d\n",
1453 pad, len, bp->rx_buf_size);
1454 bnx2x_panic();
1455 return;
1456 }
1457#endif
1458
1459 skb_reserve(skb, pad);
1460 skb_put(skb, len);
1461
1462 skb->protocol = eth_type_trans(skb, bp->dev);
1463 skb->ip_summed = CHECKSUM_UNNECESSARY;
1464
1465 {
1466 struct iphdr *iph;
1467
1468 iph = (struct iphdr *)skb->data;
Eilon Greenstein0c6671b2009-01-14 21:26:51 -08001469#ifdef BCM_VLAN
1470 /* If there is no Rx VLAN offloading -
1471 take VLAN tag into an account */
1472 if (unlikely(is_not_hwaccel_vlan_cqe))
1473 iph = (struct iphdr *)((u8 *)iph + VLAN_HLEN);
1474#endif
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001475 iph->check = 0;
1476 iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1477 }
1478
1479 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1480 &cqe->fast_path_cqe, cqe_idx)) {
1481#ifdef BCM_VLAN
Eilon Greenstein0c6671b2009-01-14 21:26:51 -08001482 if ((bp->vlgrp != NULL) && is_vlan_cqe &&
1483 (!is_not_hwaccel_vlan_cqe))
Dmitry Kravkov4fd89b72010-04-01 19:45:34 -07001484 vlan_gro_receive(&fp->napi, bp->vlgrp,
1485 le16_to_cpu(cqe->fast_path_cqe.
1486 vlan_tag), skb);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001487 else
1488#endif
Dmitry Kravkov4fd89b72010-04-01 19:45:34 -07001489 napi_gro_receive(&fp->napi, skb);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001490 } else {
1491 DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1492 " - dropping packet!\n");
1493 dev_kfree_skb(skb);
1494 }
1495
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001496
1497 /* put new skb in bin */
1498 fp->tpa_pool[queue].skb = new_skb;
1499
1500 } else {
Yitchak Gertner66e855f2008-08-13 15:49:05 -07001501 /* else drop the packet and keep the buffer in the bin */
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001502 DP(NETIF_MSG_RX_STATUS,
1503 "Failed to allocate new skb - dropping packet!\n");
Eilon Greensteinde832a52009-02-12 08:36:33 +00001504 fp->eth_q_stats.rx_skb_alloc_failed++;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001505 }
1506
1507 fp->tpa_state[queue] = BNX2X_TPA_STOP;
1508}
1509
1510static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1511 struct bnx2x_fastpath *fp,
1512 u16 bd_prod, u16 rx_comp_prod,
1513 u16 rx_sge_prod)
1514{
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08001515 struct ustorm_eth_rx_producers rx_prods = {0};
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001516 int i;
1517
1518 /* Update producers */
1519 rx_prods.bd_prod = bd_prod;
1520 rx_prods.cqe_prod = rx_comp_prod;
1521 rx_prods.sge_prod = rx_sge_prod;
1522
Eilon Greenstein58f4c4c2009-01-14 21:23:36 -08001523 /*
1524 * Make sure that the BD and SGE data is updated before updating the
1525 * producers since FW might read the BD/SGE right after the producer
1526 * is updated.
1527 * This is only applicable for weak-ordered memory model archs such
1528 * as IA-64. The following barrier is also mandatory since FW will
1529 * assumes BDs must have buffers.
1530 */
1531 wmb();
1532
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08001533 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
1534 REG_WR(bp, BAR_USTRORM_INTMEM +
Eilon Greenstein0626b892009-02-12 08:38:14 +00001535 USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001536 ((u32 *)&rx_prods)[i]);
1537
Eilon Greenstein58f4c4c2009-01-14 21:23:36 -08001538 mmiowb(); /* keep prod updates ordered */
1539
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001540 DP(NETIF_MSG_RX_STATUS,
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001541 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
1542 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001543}
1544
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001545static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1546{
1547 struct bnx2x *bp = fp->bp;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001548 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001549 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1550 int rx_pkt = 0;
1551
1552#ifdef BNX2X_STOP_ON_ERROR
1553 if (unlikely(bp->panic))
1554 return 0;
1555#endif
1556
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001557 /* CQ "next element" is of the size of the regular element,
1558 that's why it's ok here */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001559 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1560 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1561 hw_comp_cons++;
1562
1563 bd_cons = fp->rx_bd_cons;
1564 bd_prod = fp->rx_bd_prod;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001565 bd_prod_fw = bd_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001566 sw_comp_cons = fp->rx_comp_cons;
1567 sw_comp_prod = fp->rx_comp_prod;
1568
1569 /* Memory barrier necessary as speculative reads of the rx
1570 * buffer can be ahead of the index in the status block
1571 */
1572 rmb();
1573
1574 DP(NETIF_MSG_RX_STATUS,
1575 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
Eilon Greenstein0626b892009-02-12 08:38:14 +00001576 fp->index, hw_comp_cons, sw_comp_cons);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001577
1578 while (sw_comp_cons != hw_comp_cons) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001579 struct sw_rx_bd *rx_buf = NULL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001580 struct sk_buff *skb;
1581 union eth_rx_cqe *cqe;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001582 u8 cqe_fp_flags;
1583 u16 len, pad;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001584
1585 comp_ring_cons = RCQ_BD(sw_comp_cons);
1586 bd_prod = RX_BD(bd_prod);
1587 bd_cons = RX_BD(bd_cons);
1588
Eilon Greenstein619e7a62009-08-12 08:23:20 +00001589 /* Prefetch the page containing the BD descriptor
1590 at producer's index. It will be needed when new skb is
1591 allocated */
1592 prefetch((void *)(PAGE_ALIGN((unsigned long)
1593 (&fp->rx_desc_ring[bd_prod])) -
1594 PAGE_SIZE + 1));
1595
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001596 cqe = &fp->rx_comp_ring[comp_ring_cons];
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001597 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001598
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001599 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001600 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags),
1601 cqe_fp_flags, cqe->fast_path_cqe.status_flags,
Eilon Greenstein68d59482009-01-14 21:27:36 -08001602 le32_to_cpu(cqe->fast_path_cqe.rss_hash_result),
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001603 le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1604 le16_to_cpu(cqe->fast_path_cqe.pkt_len));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001605
1606 /* is this a slowpath msg? */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001607 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001608 bnx2x_sp_event(fp, cqe);
1609 goto next_cqe;
1610
1611 /* this is an rx packet */
1612 } else {
1613 rx_buf = &fp->rx_buf_ring[bd_cons];
1614 skb = rx_buf->skb;
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00001615 prefetch(skb);
1616 prefetch((u8 *)skb + 256);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001617 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1618 pad = cqe->fast_path_cqe.placement_offset;
1619
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001620 /* If CQE is marked both TPA_START and TPA_END
1621 it is a non-TPA CQE */
1622 if ((!fp->disable_tpa) &&
1623 (TPA_TYPE(cqe_fp_flags) !=
1624 (TPA_TYPE_START | TPA_TYPE_END))) {
Eilon Greenstein3196a882008-08-13 15:58:49 -07001625 u16 queue = cqe->fast_path_cqe.queue_index;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001626
1627 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1628 DP(NETIF_MSG_RX_STATUS,
1629 "calling tpa_start on queue %d\n",
1630 queue);
1631
1632 bnx2x_tpa_start(fp, queue, skb,
1633 bd_cons, bd_prod);
1634 goto next_rx;
1635 }
1636
1637 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1638 DP(NETIF_MSG_RX_STATUS,
1639 "calling tpa_stop on queue %d\n",
1640 queue);
1641
1642 if (!BNX2X_RX_SUM_FIX(cqe))
1643 BNX2X_ERR("STOP on none TCP "
1644 "data\n");
1645
1646 /* This is a size of the linear data
1647 on this skb */
1648 len = le16_to_cpu(cqe->fast_path_cqe.
1649 len_on_bd);
1650 bnx2x_tpa_stop(bp, fp, queue, pad,
1651 len, cqe, comp_ring_cons);
1652#ifdef BNX2X_STOP_ON_ERROR
1653 if (bp->panic)
Stanislaw Gruszka17cb40062009-05-05 23:22:12 +00001654 return 0;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001655#endif
1656
1657 bnx2x_update_sge_prod(fp,
1658 &cqe->fast_path_cqe);
1659 goto next_cqe;
1660 }
1661 }
1662
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001663 dma_sync_single_for_device(&bp->pdev->dev,
1664 dma_unmap_addr(rx_buf, mapping),
1665 pad + RX_COPY_THRESH,
1666 DMA_FROM_DEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001667 prefetch(skb);
1668 prefetch(((char *)(skb)) + 128);
1669
1670 /* is this an error packet? */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001671 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001672 DP(NETIF_MSG_RX_ERR,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001673 "ERROR flags %x rx packet %u\n",
1674 cqe_fp_flags, sw_comp_cons);
Eilon Greensteinde832a52009-02-12 08:36:33 +00001675 fp->eth_q_stats.rx_err_discard_pkt++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001676 goto reuse_rx;
1677 }
1678
1679 /* Since we don't have a jumbo ring
1680 * copy small packets if mtu > 1500
1681 */
1682 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1683 (len <= RX_COPY_THRESH)) {
1684 struct sk_buff *new_skb;
1685
1686 new_skb = netdev_alloc_skb(bp->dev,
1687 len + pad);
1688 if (new_skb == NULL) {
1689 DP(NETIF_MSG_RX_ERR,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001690 "ERROR packet dropped "
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001691 "because of alloc failure\n");
Eilon Greensteinde832a52009-02-12 08:36:33 +00001692 fp->eth_q_stats.rx_skb_alloc_failed++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001693 goto reuse_rx;
1694 }
1695
1696 /* aligned copy */
1697 skb_copy_from_linear_data_offset(skb, pad,
1698 new_skb->data + pad, len);
1699 skb_reserve(new_skb, pad);
1700 skb_put(new_skb, len);
1701
1702 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1703
1704 skb = new_skb;
1705
Eilon Greensteina119a062009-08-12 08:23:23 +00001706 } else
1707 if (likely(bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0)) {
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001708 dma_unmap_single(&bp->pdev->dev,
1709 dma_unmap_addr(rx_buf, mapping),
Eilon Greenstein437cf2f2008-09-03 14:38:00 -07001710 bp->rx_buf_size,
FUJITA Tomonori1a983142010-04-04 01:51:03 +00001711 DMA_FROM_DEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001712 skb_reserve(skb, pad);
1713 skb_put(skb, len);
1714
1715 } else {
1716 DP(NETIF_MSG_RX_ERR,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001717 "ERROR packet dropped because "
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001718 "of alloc failure\n");
Eilon Greensteinde832a52009-02-12 08:36:33 +00001719 fp->eth_q_stats.rx_skb_alloc_failed++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001720reuse_rx:
1721 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1722 goto next_rx;
1723 }
1724
1725 skb->protocol = eth_type_trans(skb, bp->dev);
1726
1727 skb->ip_summed = CHECKSUM_NONE;
Yitchak Gertner66e855f2008-08-13 15:49:05 -07001728 if (bp->rx_csum) {
Eilon Greenstein1adcd8b2008-08-13 15:48:29 -07001729 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1730 skb->ip_summed = CHECKSUM_UNNECESSARY;
Yitchak Gertner66e855f2008-08-13 15:49:05 -07001731 else
Eilon Greensteinde832a52009-02-12 08:36:33 +00001732 fp->eth_q_stats.hw_csum_err++;
Yitchak Gertner66e855f2008-08-13 15:49:05 -07001733 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001734 }
1735
Eilon Greenstein748e5432009-02-12 08:36:37 +00001736 skb_record_rx_queue(skb, fp->index);
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00001737
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001738#ifdef BCM_VLAN
Eilon Greenstein0c6671b2009-01-14 21:26:51 -08001739 if ((bp->vlgrp != NULL) && (bp->flags & HW_VLAN_RX_FLAG) &&
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001740 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1741 PARSING_FLAGS_VLAN))
Dmitry Kravkov4fd89b72010-04-01 19:45:34 -07001742 vlan_gro_receive(&fp->napi, bp->vlgrp,
1743 le16_to_cpu(cqe->fast_path_cqe.vlan_tag), skb);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001744 else
1745#endif
Dmitry Kravkov4fd89b72010-04-01 19:45:34 -07001746 napi_gro_receive(&fp->napi, skb);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001747
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001748
1749next_rx:
1750 rx_buf->skb = NULL;
1751
1752 bd_cons = NEXT_RX_IDX(bd_cons);
1753 bd_prod = NEXT_RX_IDX(bd_prod);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001754 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1755 rx_pkt++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001756next_cqe:
1757 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1758 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001759
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001760 if (rx_pkt == budget)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001761 break;
1762 } /* while */
1763
1764 fp->rx_bd_cons = bd_cons;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001765 fp->rx_bd_prod = bd_prod_fw;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001766 fp->rx_comp_cons = sw_comp_cons;
1767 fp->rx_comp_prod = sw_comp_prod;
1768
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001769 /* Update producers */
1770 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1771 fp->rx_sge_prod);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001772
1773 fp->rx_pkt += rx_pkt;
1774 fp->rx_calls++;
1775
1776 return rx_pkt;
1777}
1778
1779static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1780{
1781 struct bnx2x_fastpath *fp = fp_cookie;
1782 struct bnx2x *bp = fp->bp;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001783
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07001784 /* Return here if interrupt is disabled */
1785 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1786 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1787 return IRQ_HANDLED;
1788 }
1789
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001790 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
Eilon Greensteinca003922009-08-12 22:53:28 -07001791 fp->index, fp->sb_id);
Eilon Greenstein0626b892009-02-12 08:38:14 +00001792 bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001793
1794#ifdef BNX2X_STOP_ON_ERROR
1795 if (unlikely(bp->panic))
1796 return IRQ_HANDLED;
1797#endif
1798
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00001799 /* Handle Rx and Tx according to MSI-X vector */
1800 prefetch(fp->rx_cons_sb);
1801 prefetch(fp->tx_cons_sb);
1802 prefetch(&fp->status_blk->u_status_block.status_block_index);
1803 prefetch(&fp->status_blk->c_status_block.status_block_index);
1804 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001805
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001806 return IRQ_HANDLED;
1807}
1808
1809static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1810{
Eilon Greenstein555f6c72009-02-12 08:36:11 +00001811 struct bnx2x *bp = netdev_priv(dev_instance);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001812 u16 status = bnx2x_ack_int(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001813 u16 mask;
Eilon Greensteinca003922009-08-12 22:53:28 -07001814 int i;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001815
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001816 /* Return here if interrupt is shared and it's not for us */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001817 if (unlikely(status == 0)) {
1818 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1819 return IRQ_NONE;
1820 }
Eilon Greensteinf5372252009-02-12 08:38:30 +00001821 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001822
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001823 /* Return here if interrupt is disabled */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001824 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1825 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1826 return IRQ_HANDLED;
1827 }
1828
Eilon Greenstein3196a882008-08-13 15:58:49 -07001829#ifdef BNX2X_STOP_ON_ERROR
1830 if (unlikely(bp->panic))
1831 return IRQ_HANDLED;
1832#endif
1833
Eilon Greensteinca003922009-08-12 22:53:28 -07001834 for (i = 0; i < BNX2X_NUM_QUEUES(bp); i++) {
1835 struct bnx2x_fastpath *fp = &bp->fp[i];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001836
Eilon Greensteinca003922009-08-12 22:53:28 -07001837 mask = 0x2 << fp->sb_id;
1838 if (status & mask) {
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00001839 /* Handle Rx and Tx according to SB id */
1840 prefetch(fp->rx_cons_sb);
1841 prefetch(&fp->status_blk->u_status_block.
1842 status_block_index);
1843 prefetch(fp->tx_cons_sb);
1844 prefetch(&fp->status_blk->c_status_block.
1845 status_block_index);
1846 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
Eilon Greensteinca003922009-08-12 22:53:28 -07001847 status &= ~mask;
1848 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001849 }
1850
Michael Chan993ac7b2009-10-10 13:46:56 +00001851#ifdef BCM_CNIC
1852 mask = 0x2 << CNIC_SB_ID(bp);
1853 if (status & (mask | 0x1)) {
1854 struct cnic_ops *c_ops = NULL;
1855
1856 rcu_read_lock();
1857 c_ops = rcu_dereference(bp->cnic_ops);
1858 if (c_ops)
1859 c_ops->cnic_handler(bp->cnic_data, NULL);
1860 rcu_read_unlock();
1861
1862 status &= ~mask;
1863 }
1864#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001865
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001866 if (unlikely(status & 0x1)) {
Eilon Greenstein1cf167f2009-01-14 21:22:18 -08001867 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001868
1869 status &= ~0x1;
1870 if (!status)
1871 return IRQ_HANDLED;
1872 }
1873
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001874 if (status)
1875 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1876 status);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001877
1878 return IRQ_HANDLED;
1879}
1880
1881/* end of fast path */
1882
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001883static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001884
1885/* Link */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001886
1887/*
1888 * General service functions
1889 */
1890
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001891static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
Eliezer Tamirf1410642008-02-28 11:51:50 -08001892{
Eliezer Tamirf1410642008-02-28 11:51:50 -08001893 u32 lock_status;
1894 u32 resource_bit = (1 << resource);
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001895 int func = BP_FUNC(bp);
1896 u32 hw_lock_control_reg;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001897 int cnt;
Eliezer Tamirf1410642008-02-28 11:51:50 -08001898
1899 /* Validating that the resource is within range */
1900 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1901 DP(NETIF_MSG_HW,
1902 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1903 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1904 return -EINVAL;
1905 }
1906
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001907 if (func <= 5) {
1908 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1909 } else {
1910 hw_lock_control_reg =
1911 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1912 }
1913
Eliezer Tamirf1410642008-02-28 11:51:50 -08001914 /* Validating that the resource is not already taken */
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001915 lock_status = REG_RD(bp, hw_lock_control_reg);
Eliezer Tamirf1410642008-02-28 11:51:50 -08001916 if (lock_status & resource_bit) {
1917 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1918 lock_status, resource_bit);
1919 return -EEXIST;
1920 }
1921
Eilon Greenstein46230472008-08-25 15:23:30 -07001922 /* Try for 5 second every 5ms */
1923 for (cnt = 0; cnt < 1000; cnt++) {
Eliezer Tamirf1410642008-02-28 11:51:50 -08001924 /* Try to acquire the lock */
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001925 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1926 lock_status = REG_RD(bp, hw_lock_control_reg);
Eliezer Tamirf1410642008-02-28 11:51:50 -08001927 if (lock_status & resource_bit)
1928 return 0;
1929
1930 msleep(5);
1931 }
1932 DP(NETIF_MSG_HW, "Timeout\n");
1933 return -EAGAIN;
1934}
1935
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001936static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
Eliezer Tamirf1410642008-02-28 11:51:50 -08001937{
1938 u32 lock_status;
1939 u32 resource_bit = (1 << resource);
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001940 int func = BP_FUNC(bp);
1941 u32 hw_lock_control_reg;
Eliezer Tamirf1410642008-02-28 11:51:50 -08001942
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00001943 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1944
Eliezer Tamirf1410642008-02-28 11:51:50 -08001945 /* Validating that the resource is within range */
1946 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1947 DP(NETIF_MSG_HW,
1948 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1949 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1950 return -EINVAL;
1951 }
1952
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001953 if (func <= 5) {
1954 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1955 } else {
1956 hw_lock_control_reg =
1957 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1958 }
1959
Eliezer Tamirf1410642008-02-28 11:51:50 -08001960 /* Validating that the resource is currently taken */
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001961 lock_status = REG_RD(bp, hw_lock_control_reg);
Eliezer Tamirf1410642008-02-28 11:51:50 -08001962 if (!(lock_status & resource_bit)) {
1963 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1964 lock_status, resource_bit);
1965 return -EFAULT;
1966 }
1967
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001968 REG_WR(bp, hw_lock_control_reg, resource_bit);
Eliezer Tamirf1410642008-02-28 11:51:50 -08001969 return 0;
1970}
1971
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001972/* HW Lock for shared dual port PHYs */
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001973static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001974{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001975 mutex_lock(&bp->port.phy_mutex);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001976
Eilon Greenstein46c6a672009-02-12 08:36:58 +00001977 if (bp->port.need_hw_lock)
1978 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001979}
1980
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001981static void bnx2x_release_phy_lock(struct bnx2x *bp)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001982{
Eilon Greenstein46c6a672009-02-12 08:36:58 +00001983 if (bp->port.need_hw_lock)
1984 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001985
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001986 mutex_unlock(&bp->port.phy_mutex);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001987}
1988
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00001989int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1990{
1991 /* The GPIO should be swapped if swap register is set and active */
1992 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1993 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1994 int gpio_shift = gpio_num +
1995 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1996 u32 gpio_mask = (1 << gpio_shift);
1997 u32 gpio_reg;
1998 int value;
1999
2000 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2001 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2002 return -EINVAL;
2003 }
2004
2005 /* read GPIO value */
2006 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2007
2008 /* get the requested pin value */
2009 if ((gpio_reg & gpio_mask) == gpio_mask)
2010 value = 1;
2011 else
2012 value = 0;
2013
2014 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2015
2016 return value;
2017}
2018
Eilon Greenstein17de50b2008-08-13 15:56:59 -07002019int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
Eliezer Tamirf1410642008-02-28 11:51:50 -08002020{
2021 /* The GPIO should be swapped if swap register is set and active */
2022 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
Eilon Greenstein17de50b2008-08-13 15:56:59 -07002023 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
Eliezer Tamirf1410642008-02-28 11:51:50 -08002024 int gpio_shift = gpio_num +
2025 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2026 u32 gpio_mask = (1 << gpio_shift);
2027 u32 gpio_reg;
2028
2029 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2030 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2031 return -EINVAL;
2032 }
2033
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002034 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
Eliezer Tamirf1410642008-02-28 11:51:50 -08002035 /* read GPIO and mask except the float bits */
2036 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2037
2038 switch (mode) {
2039 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2040 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
2041 gpio_num, gpio_shift);
2042 /* clear FLOAT and set CLR */
2043 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2044 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2045 break;
2046
2047 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2048 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
2049 gpio_num, gpio_shift);
2050 /* clear FLOAT and set SET */
2051 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2052 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2053 break;
2054
Eilon Greenstein17de50b2008-08-13 15:56:59 -07002055 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
Eliezer Tamirf1410642008-02-28 11:51:50 -08002056 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
2057 gpio_num, gpio_shift);
2058 /* set FLOAT */
2059 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2060 break;
2061
2062 default:
2063 break;
2064 }
2065
2066 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002067 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
Eliezer Tamirf1410642008-02-28 11:51:50 -08002068
2069 return 0;
2070}
2071
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00002072int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2073{
2074 /* The GPIO should be swapped if swap register is set and active */
2075 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2076 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2077 int gpio_shift = gpio_num +
2078 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2079 u32 gpio_mask = (1 << gpio_shift);
2080 u32 gpio_reg;
2081
2082 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2083 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2084 return -EINVAL;
2085 }
2086
2087 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2088 /* read GPIO int */
2089 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2090
2091 switch (mode) {
2092 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2093 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2094 "output low\n", gpio_num, gpio_shift);
2095 /* clear SET and set CLR */
2096 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2097 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2098 break;
2099
2100 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2101 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2102 "output high\n", gpio_num, gpio_shift);
2103 /* clear CLR and set SET */
2104 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2105 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2106 break;
2107
2108 default:
2109 break;
2110 }
2111
2112 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2113 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2114
2115 return 0;
2116}
2117
Eliezer Tamirf1410642008-02-28 11:51:50 -08002118static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2119{
2120 u32 spio_mask = (1 << spio_num);
2121 u32 spio_reg;
2122
2123 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2124 (spio_num > MISC_REGISTERS_SPIO_7)) {
2125 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2126 return -EINVAL;
2127 }
2128
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002129 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
Eliezer Tamirf1410642008-02-28 11:51:50 -08002130 /* read SPIO and mask except the float bits */
2131 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2132
2133 switch (mode) {
Eilon Greenstein6378c022008-08-13 15:59:25 -07002134 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
Eliezer Tamirf1410642008-02-28 11:51:50 -08002135 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2136 /* clear FLOAT and set CLR */
2137 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2138 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2139 break;
2140
Eilon Greenstein6378c022008-08-13 15:59:25 -07002141 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
Eliezer Tamirf1410642008-02-28 11:51:50 -08002142 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2143 /* clear FLOAT and set SET */
2144 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2145 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2146 break;
2147
2148 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2149 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2150 /* set FLOAT */
2151 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2152 break;
2153
2154 default:
2155 break;
2156 }
2157
2158 REG_WR(bp, MISC_REG_SPIO, spio_reg);
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002159 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
Eliezer Tamirf1410642008-02-28 11:51:50 -08002160
2161 return 0;
2162}
2163
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002164static void bnx2x_calc_fc_adv(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002165{
Eilon Greensteinad33ea32009-01-14 21:24:57 -08002166 switch (bp->link_vars.ieee_fc &
2167 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002168 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002169 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002170 ADVERTISED_Pause);
Eliezer Tamirf1410642008-02-28 11:51:50 -08002171 break;
Eilon Greenstein356e2382009-02-12 08:38:32 +00002172
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002173 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002174 bp->port.advertising |= (ADVERTISED_Asym_Pause |
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002175 ADVERTISED_Pause);
Eliezer Tamirf1410642008-02-28 11:51:50 -08002176 break;
Eilon Greenstein356e2382009-02-12 08:38:32 +00002177
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002178 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002179 bp->port.advertising |= ADVERTISED_Asym_Pause;
Eliezer Tamirf1410642008-02-28 11:51:50 -08002180 break;
Eilon Greenstein356e2382009-02-12 08:38:32 +00002181
Eliezer Tamirf1410642008-02-28 11:51:50 -08002182 default:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002183 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002184 ADVERTISED_Pause);
Eliezer Tamirf1410642008-02-28 11:51:50 -08002185 break;
2186 }
2187}
2188
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002189static void bnx2x_link_report(struct bnx2x *bp)
2190{
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07002191 if (bp->flags & MF_FUNC_DIS) {
Eilon Greenstein2691d512009-08-12 08:22:08 +00002192 netif_carrier_off(bp->dev);
Joe Perches7995c642010-02-17 15:01:52 +00002193 netdev_err(bp->dev, "NIC Link is Down\n");
Eilon Greenstein2691d512009-08-12 08:22:08 +00002194 return;
2195 }
2196
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002197 if (bp->link_vars.link_up) {
Eilon Greenstein35c5f8f2009-10-15 00:19:05 -07002198 u16 line_speed;
2199
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002200 if (bp->state == BNX2X_STATE_OPEN)
2201 netif_carrier_on(bp->dev);
Joe Perches7995c642010-02-17 15:01:52 +00002202 netdev_info(bp->dev, "NIC Link is Up, ");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002203
Eilon Greenstein35c5f8f2009-10-15 00:19:05 -07002204 line_speed = bp->link_vars.line_speed;
2205 if (IS_E1HMF(bp)) {
2206 u16 vn_max_rate;
2207
2208 vn_max_rate =
2209 ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
2210 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2211 if (vn_max_rate < line_speed)
2212 line_speed = vn_max_rate;
2213 }
Joe Perches7995c642010-02-17 15:01:52 +00002214 pr_cont("%d Mbps ", line_speed);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002215
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002216 if (bp->link_vars.duplex == DUPLEX_FULL)
Joe Perches7995c642010-02-17 15:01:52 +00002217 pr_cont("full duplex");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002218 else
Joe Perches7995c642010-02-17 15:01:52 +00002219 pr_cont("half duplex");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002220
David S. Millerc0700f92008-12-16 23:53:20 -08002221 if (bp->link_vars.flow_ctrl != BNX2X_FLOW_CTRL_NONE) {
2222 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) {
Joe Perches7995c642010-02-17 15:01:52 +00002223 pr_cont(", receive ");
Eilon Greenstein356e2382009-02-12 08:38:32 +00002224 if (bp->link_vars.flow_ctrl &
2225 BNX2X_FLOW_CTRL_TX)
Joe Perches7995c642010-02-17 15:01:52 +00002226 pr_cont("& transmit ");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002227 } else {
Joe Perches7995c642010-02-17 15:01:52 +00002228 pr_cont(", transmit ");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002229 }
Joe Perches7995c642010-02-17 15:01:52 +00002230 pr_cont("flow control ON");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002231 }
Joe Perches7995c642010-02-17 15:01:52 +00002232 pr_cont("\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002233
2234 } else { /* link_down */
2235 netif_carrier_off(bp->dev);
Joe Perches7995c642010-02-17 15:01:52 +00002236 netdev_err(bp->dev, "NIC Link is Down\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002237 }
2238}
2239
Eilon Greensteinb5bf9062009-02-12 08:38:08 +00002240static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002241{
Eilon Greenstein19680c42008-08-13 15:47:33 -07002242 if (!BP_NOMCP(bp)) {
2243 u8 rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002244
Eilon Greenstein19680c42008-08-13 15:47:33 -07002245 /* Initialize link parameters structure variables */
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002246 /* It is recommended to turn off RX FC for jumbo frames
2247 for better performance */
Eilon Greenstein0c593272009-08-12 08:22:13 +00002248 if (bp->dev->mtu > 5000)
David S. Millerc0700f92008-12-16 23:53:20 -08002249 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07002250 else
David S. Millerc0700f92008-12-16 23:53:20 -08002251 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002252
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002253 bnx2x_acquire_phy_lock(bp);
Eilon Greensteinb5bf9062009-02-12 08:38:08 +00002254
2255 if (load_mode == LOAD_DIAG)
2256 bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
2257
Eilon Greenstein19680c42008-08-13 15:47:33 -07002258 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
Eilon Greensteinb5bf9062009-02-12 08:38:08 +00002259
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002260 bnx2x_release_phy_lock(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002261
Eilon Greenstein3c96c682009-01-14 21:25:31 -08002262 bnx2x_calc_fc_adv(bp);
2263
Eilon Greensteinb5bf9062009-02-12 08:38:08 +00002264 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2265 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
Eilon Greenstein19680c42008-08-13 15:47:33 -07002266 bnx2x_link_report(bp);
Eilon Greensteinb5bf9062009-02-12 08:38:08 +00002267 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002268
Eilon Greenstein19680c42008-08-13 15:47:33 -07002269 return rc;
2270 }
Eilon Greensteinf5372252009-02-12 08:38:30 +00002271 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
Eilon Greenstein19680c42008-08-13 15:47:33 -07002272 return -EINVAL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002273}
2274
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002275static void bnx2x_link_set(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002276{
Eilon Greenstein19680c42008-08-13 15:47:33 -07002277 if (!BP_NOMCP(bp)) {
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002278 bnx2x_acquire_phy_lock(bp);
Eilon Greenstein19680c42008-08-13 15:47:33 -07002279 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002280 bnx2x_release_phy_lock(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002281
Eilon Greenstein19680c42008-08-13 15:47:33 -07002282 bnx2x_calc_fc_adv(bp);
2283 } else
Eilon Greensteinf5372252009-02-12 08:38:30 +00002284 BNX2X_ERR("Bootcode is missing - can not set link\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002285}
2286
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002287static void bnx2x__link_reset(struct bnx2x *bp)
2288{
Eilon Greenstein19680c42008-08-13 15:47:33 -07002289 if (!BP_NOMCP(bp)) {
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002290 bnx2x_acquire_phy_lock(bp);
Eilon Greenstein589abe32009-02-12 08:36:55 +00002291 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002292 bnx2x_release_phy_lock(bp);
Eilon Greenstein19680c42008-08-13 15:47:33 -07002293 } else
Eilon Greensteinf5372252009-02-12 08:38:30 +00002294 BNX2X_ERR("Bootcode is missing - can not reset link\n");
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002295}
2296
2297static u8 bnx2x_link_test(struct bnx2x *bp)
2298{
Vladislav Zolotarov2145a922010-04-19 01:13:49 +00002299 u8 rc = 0;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002300
Vladislav Zolotarov2145a922010-04-19 01:13:49 +00002301 if (!BP_NOMCP(bp)) {
2302 bnx2x_acquire_phy_lock(bp);
2303 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2304 bnx2x_release_phy_lock(bp);
2305 } else
2306 BNX2X_ERR("Bootcode is missing - can not test link\n");
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002307
2308 return rc;
2309}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002310
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002311static void bnx2x_init_port_minmax(struct bnx2x *bp)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002312{
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002313 u32 r_param = bp->link_vars.line_speed / 8;
2314 u32 fair_periodic_timeout_usec;
2315 u32 t_fair;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002316
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002317 memset(&(bp->cmng.rs_vars), 0,
2318 sizeof(struct rate_shaping_vars_per_port));
2319 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002320
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002321 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2322 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002323
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002324 /* this is the threshold below which no timer arming will occur
2325 1.25 coefficient is for the threshold to be a little bigger
2326 than the real time, to compensate for timer in-accuracy */
2327 bp->cmng.rs_vars.rs_threshold =
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002328 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2329
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002330 /* resolution of fairness timer */
2331 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2332 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2333 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002334
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002335 /* this is the threshold below which we won't arm the timer anymore */
2336 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002337
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002338 /* we multiply by 1e3/8 to get bytes/msec.
2339 We don't want the credits to pass a credit
2340 of the t_fair*FAIR_MEM (algorithm resolution) */
2341 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2342 /* since each tick is 4 usec */
2343 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002344}
2345
Eilon Greenstein2691d512009-08-12 08:22:08 +00002346/* Calculates the sum of vn_min_rates.
2347 It's needed for further normalizing of the min_rates.
2348 Returns:
2349 sum of vn_min_rates.
2350 or
2351 0 - if all the min_rates are 0.
2352 In the later case fainess algorithm should be deactivated.
2353 If not all min_rates are zero then those that are zeroes will be set to 1.
2354 */
2355static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2356{
2357 int all_zero = 1;
2358 int port = BP_PORT(bp);
2359 int vn;
2360
2361 bp->vn_weight_sum = 0;
2362 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2363 int func = 2*vn + port;
2364 u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2365 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2366 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2367
2368 /* Skip hidden vns */
2369 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2370 continue;
2371
2372 /* If min rate is zero - set it to 1 */
2373 if (!vn_min_rate)
2374 vn_min_rate = DEF_MIN_RATE;
2375 else
2376 all_zero = 0;
2377
2378 bp->vn_weight_sum += vn_min_rate;
2379 }
2380
2381 /* ... only if all min rates are zeros - disable fairness */
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07002382 if (all_zero) {
2383 bp->cmng.flags.cmng_enables &=
2384 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2385 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2386 " fairness will be disabled\n");
2387 } else
2388 bp->cmng.flags.cmng_enables |=
2389 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
Eilon Greenstein2691d512009-08-12 08:22:08 +00002390}
2391
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002392static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002393{
2394 struct rate_shaping_vars_per_vn m_rs_vn;
2395 struct fairness_vars_per_vn m_fair_vn;
2396 u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2397 u16 vn_min_rate, vn_max_rate;
2398 int i;
2399
2400 /* If function is hidden - set min and max to zeroes */
2401 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2402 vn_min_rate = 0;
2403 vn_max_rate = 0;
2404
2405 } else {
2406 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2407 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07002408 /* If min rate is zero - set it to 1 */
2409 if (!vn_min_rate)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002410 vn_min_rate = DEF_MIN_RATE;
2411 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2412 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2413 }
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002414 DP(NETIF_MSG_IFUP,
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07002415 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002416 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002417
2418 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2419 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2420
2421 /* global vn counter - maximal Mbps for this vn */
2422 m_rs_vn.vn_counter.rate = vn_max_rate;
2423
2424 /* quota - number of bytes transmitted in this period */
2425 m_rs_vn.vn_counter.quota =
2426 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2427
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002428 if (bp->vn_weight_sum) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002429 /* credit for each period of the fairness algorithm:
2430 number of bytes in T_FAIR (the vn share the port rate).
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002431 vn_weight_sum should not be larger than 10000, thus
2432 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2433 than zero */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002434 m_fair_vn.vn_credit_delta =
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002435 max((u32)(vn_min_rate * (T_FAIR_COEF /
2436 (8 * bp->vn_weight_sum))),
2437 (u32)(bp->cmng.fair_vars.fair_threshold * 2));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002438 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2439 m_fair_vn.vn_credit_delta);
2440 }
2441
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002442 /* Store it to internal memory */
2443 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2444 REG_WR(bp, BAR_XSTRORM_INTMEM +
2445 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2446 ((u32 *)(&m_rs_vn))[i]);
2447
2448 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2449 REG_WR(bp, BAR_XSTRORM_INTMEM +
2450 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2451 ((u32 *)(&m_fair_vn))[i]);
2452}
2453
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002454
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002455/* This function is called upon link interrupt */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002456static void bnx2x_link_attn(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002457{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002458 /* Make sure that we are synced with the current statistics */
2459 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2460
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002461 bnx2x_link_update(&bp->link_params, &bp->link_vars);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002462
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002463 if (bp->link_vars.link_up) {
2464
Eilon Greenstein1c063282009-02-12 08:36:43 +00002465 /* dropless flow control */
Eilon Greensteina18f5122009-08-12 08:23:26 +00002466 if (CHIP_IS_E1H(bp) && bp->dropless_fc) {
Eilon Greenstein1c063282009-02-12 08:36:43 +00002467 int port = BP_PORT(bp);
2468 u32 pause_enabled = 0;
2469
2470 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2471 pause_enabled = 1;
2472
2473 REG_WR(bp, BAR_USTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07002474 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
Eilon Greenstein1c063282009-02-12 08:36:43 +00002475 pause_enabled);
2476 }
2477
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002478 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2479 struct host_port_stats *pstats;
2480
2481 pstats = bnx2x_sp(bp, port_stats);
2482 /* reset old bmac stats */
2483 memset(&(pstats->mac_stx[0]), 0,
2484 sizeof(struct mac_stx));
2485 }
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07002486 if (bp->state == BNX2X_STATE_OPEN)
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002487 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2488 }
2489
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002490 /* indicate link status */
2491 bnx2x_link_report(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002492
2493 if (IS_E1HMF(bp)) {
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002494 int port = BP_PORT(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002495 int func;
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002496 int vn;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002497
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00002498 /* Set the attention towards other drivers on the same port */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002499 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2500 if (vn == BP_E1HVN(bp))
2501 continue;
2502
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002503 func = ((vn << 1) | port);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002504 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2505 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2506 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002507
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002508 if (bp->link_vars.link_up) {
2509 int i;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002510
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002511 /* Init rate shaping and fairness contexts */
2512 bnx2x_init_port_minmax(bp);
2513
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002514 for (vn = VN_0; vn < E1HVN_MAX; vn++)
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00002515 bnx2x_init_vn_minmax(bp, 2*vn + port);
2516
2517 /* Store it to internal memory */
2518 for (i = 0;
2519 i < sizeof(struct cmng_struct_per_port) / 4; i++)
2520 REG_WR(bp, BAR_XSTRORM_INTMEM +
2521 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
2522 ((u32 *)(&bp->cmng))[i]);
2523 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002524 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002525}
2526
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002527static void bnx2x__link_status_update(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002528{
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07002529 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002530 return;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002531
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002532 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2533
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002534 if (bp->link_vars.link_up)
2535 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2536 else
2537 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2538
Eilon Greenstein2691d512009-08-12 08:22:08 +00002539 bnx2x_calc_vn_weight_sum(bp);
2540
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002541 /* indicate link status */
2542 bnx2x_link_report(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002543}
2544
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002545static void bnx2x_pmf_update(struct bnx2x *bp)
2546{
2547 int port = BP_PORT(bp);
2548 u32 val;
2549
2550 bp->port.pmf = 1;
2551 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2552
2553 /* enable nig attention */
2554 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2555 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2556 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07002557
2558 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002559}
2560
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002561/* end of Link */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002562
2563/* slow path */
2564
2565/*
2566 * General service functions
2567 */
2568
Eilon Greenstein2691d512009-08-12 08:22:08 +00002569/* send the MCP a request, block until there is a reply */
2570u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
2571{
2572 int func = BP_FUNC(bp);
2573 u32 seq = ++bp->fw_seq;
2574 u32 rc = 0;
2575 u32 cnt = 1;
2576 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2577
Eilon Greensteinc4ff7cb2009-10-15 00:18:27 -07002578 mutex_lock(&bp->fw_mb_mutex);
Eilon Greenstein2691d512009-08-12 08:22:08 +00002579 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
2580 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2581
2582 do {
2583 /* let the FW do it's magic ... */
2584 msleep(delay);
2585
2586 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
2587
Eilon Greensteinc4ff7cb2009-10-15 00:18:27 -07002588 /* Give the FW up to 5 second (500*10ms) */
2589 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
Eilon Greenstein2691d512009-08-12 08:22:08 +00002590
2591 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2592 cnt*delay, rc, seq);
2593
2594 /* is this a reply to our command? */
2595 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2596 rc &= FW_MSG_CODE_MASK;
2597 else {
2598 /* FW BUG! */
2599 BNX2X_ERR("FW failed to respond!\n");
2600 bnx2x_fw_dump(bp);
2601 rc = 0;
2602 }
Eilon Greensteinc4ff7cb2009-10-15 00:18:27 -07002603 mutex_unlock(&bp->fw_mb_mutex);
Eilon Greenstein2691d512009-08-12 08:22:08 +00002604
2605 return rc;
2606}
2607
2608static void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
Michael Chane665bfd2009-10-10 13:46:54 +00002609static void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set);
Eilon Greenstein2691d512009-08-12 08:22:08 +00002610static void bnx2x_set_rx_mode(struct net_device *dev);
2611
2612static void bnx2x_e1h_disable(struct bnx2x *bp)
2613{
2614 int port = BP_PORT(bp);
Eilon Greenstein2691d512009-08-12 08:22:08 +00002615
2616 netif_tx_disable(bp->dev);
Eilon Greenstein2691d512009-08-12 08:22:08 +00002617
2618 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2619
Eilon Greenstein2691d512009-08-12 08:22:08 +00002620 netif_carrier_off(bp->dev);
2621}
2622
2623static void bnx2x_e1h_enable(struct bnx2x *bp)
2624{
2625 int port = BP_PORT(bp);
2626
2627 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2628
Eilon Greenstein2691d512009-08-12 08:22:08 +00002629 /* Tx queue should be only reenabled */
2630 netif_tx_wake_all_queues(bp->dev);
2631
Eilon Greenstein061bc702009-10-15 00:18:47 -07002632 /*
2633 * Should not call netif_carrier_on since it will be called if the link
2634 * is up when checking for link state
2635 */
Eilon Greenstein2691d512009-08-12 08:22:08 +00002636}
2637
2638static void bnx2x_update_min_max(struct bnx2x *bp)
2639{
2640 int port = BP_PORT(bp);
2641 int vn, i;
2642
2643 /* Init rate shaping and fairness contexts */
2644 bnx2x_init_port_minmax(bp);
2645
2646 bnx2x_calc_vn_weight_sum(bp);
2647
2648 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2649 bnx2x_init_vn_minmax(bp, 2*vn + port);
2650
2651 if (bp->port.pmf) {
2652 int func;
2653
2654 /* Set the attention towards other drivers on the same port */
2655 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2656 if (vn == BP_E1HVN(bp))
2657 continue;
2658
2659 func = ((vn << 1) | port);
2660 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2661 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2662 }
2663
2664 /* Store it to internal memory */
2665 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2666 REG_WR(bp, BAR_XSTRORM_INTMEM +
2667 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
2668 ((u32 *)(&bp->cmng))[i]);
2669 }
2670}
2671
2672static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2673{
Eilon Greenstein2691d512009-08-12 08:22:08 +00002674 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
Eilon Greenstein2691d512009-08-12 08:22:08 +00002675
2676 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2677
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07002678 /*
2679 * This is the only place besides the function initialization
2680 * where the bp->flags can change so it is done without any
2681 * locks
2682 */
Eilon Greenstein2691d512009-08-12 08:22:08 +00002683 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
2684 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07002685 bp->flags |= MF_FUNC_DIS;
Eilon Greenstein2691d512009-08-12 08:22:08 +00002686
2687 bnx2x_e1h_disable(bp);
2688 } else {
2689 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07002690 bp->flags &= ~MF_FUNC_DIS;
Eilon Greenstein2691d512009-08-12 08:22:08 +00002691
2692 bnx2x_e1h_enable(bp);
2693 }
2694 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2695 }
2696 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2697
2698 bnx2x_update_min_max(bp);
2699 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2700 }
2701
2702 /* Report results to MCP */
2703 if (dcc_event)
2704 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE);
2705 else
2706 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK);
2707}
2708
Michael Chan28912902009-10-10 13:46:53 +00002709/* must be called under the spq lock */
2710static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2711{
2712 struct eth_spe *next_spe = bp->spq_prod_bd;
2713
2714 if (bp->spq_prod_bd == bp->spq_last_bd) {
2715 bp->spq_prod_bd = bp->spq;
2716 bp->spq_prod_idx = 0;
2717 DP(NETIF_MSG_TIMER, "end of spq\n");
2718 } else {
2719 bp->spq_prod_bd++;
2720 bp->spq_prod_idx++;
2721 }
2722 return next_spe;
2723}
2724
2725/* must be called under the spq lock */
2726static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2727{
2728 int func = BP_FUNC(bp);
2729
2730 /* Make sure that BD data is updated before writing the producer */
2731 wmb();
2732
2733 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2734 bp->spq_prod_idx);
2735 mmiowb();
2736}
2737
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002738/* the slow path queue is odd since completions arrive on the fastpath ring */
2739static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2740 u32 data_hi, u32 data_lo, int common)
2741{
Michael Chan28912902009-10-10 13:46:53 +00002742 struct eth_spe *spe;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002743
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002744 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2745 "SPQE (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002746 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2747 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2748 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2749
2750#ifdef BNX2X_STOP_ON_ERROR
2751 if (unlikely(bp->panic))
2752 return -EIO;
2753#endif
2754
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002755 spin_lock_bh(&bp->spq_lock);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002756
2757 if (!bp->spq_left) {
2758 BNX2X_ERR("BUG! SPQ ring full!\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002759 spin_unlock_bh(&bp->spq_lock);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002760 bnx2x_panic();
2761 return -EBUSY;
2762 }
Eliezer Tamirf1410642008-02-28 11:51:50 -08002763
Michael Chan28912902009-10-10 13:46:53 +00002764 spe = bnx2x_sp_get_next(bp);
2765
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002766 /* CID needs port number to be encoded int it */
Michael Chan28912902009-10-10 13:46:53 +00002767 spe->hdr.conn_and_cmd_data =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002768 cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2769 HW_CID(bp, cid)));
Michael Chan28912902009-10-10 13:46:53 +00002770 spe->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002771 if (common)
Michael Chan28912902009-10-10 13:46:53 +00002772 spe->hdr.type |=
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002773 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2774
Michael Chan28912902009-10-10 13:46:53 +00002775 spe->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2776 spe->data.mac_config_addr.lo = cpu_to_le32(data_lo);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002777
2778 bp->spq_left--;
2779
Michael Chan28912902009-10-10 13:46:53 +00002780 bnx2x_sp_prod_update(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002781 spin_unlock_bh(&bp->spq_lock);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002782 return 0;
2783}
2784
2785/* acquire split MCP access lock register */
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002786static int bnx2x_acquire_alr(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002787{
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00002788 u32 j, val;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002789 int rc = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002790
2791 might_sleep();
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00002792 for (j = 0; j < 1000; j++) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002793 val = (1UL << 31);
2794 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2795 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2796 if (val & (1L << 31))
2797 break;
2798
2799 msleep(5);
2800 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002801 if (!(val & (1L << 31))) {
Eilon Greenstein19680c42008-08-13 15:47:33 -07002802 BNX2X_ERR("Cannot acquire MCP access lock register\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002803 rc = -EBUSY;
2804 }
2805
2806 return rc;
2807}
2808
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07002809/* release split MCP access lock register */
2810static void bnx2x_release_alr(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002811{
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00002812 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002813}
2814
2815static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2816{
2817 struct host_def_status_block *def_sb = bp->def_status_blk;
2818 u16 rc = 0;
2819
2820 barrier(); /* status block is written to by the chip */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002821 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2822 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2823 rc |= 1;
2824 }
2825 if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2826 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2827 rc |= 2;
2828 }
2829 if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2830 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2831 rc |= 4;
2832 }
2833 if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2834 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2835 rc |= 8;
2836 }
2837 if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2838 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2839 rc |= 16;
2840 }
2841 return rc;
2842}
2843
2844/*
2845 * slow path service functions
2846 */
2847
2848static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2849{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002850 int port = BP_PORT(bp);
Eilon Greenstein5c862842008-08-13 15:51:48 -07002851 u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2852 COMMAND_REG_ATTN_BITS_SET);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002853 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2854 MISC_REG_AEU_MASK_ATTN_FUNC_0;
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002855 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2856 NIG_REG_MASK_INTERRUPT_PORT0;
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07002857 u32 aeu_mask;
Eilon Greenstein87942b42009-02-12 08:36:49 +00002858 u32 nig_mask = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002859
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002860 if (bp->attn_state & asserted)
2861 BNX2X_ERR("IGU ERROR\n");
2862
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07002863 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2864 aeu_mask = REG_RD(bp, aeu_addr);
2865
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002866 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07002867 aeu_mask, asserted);
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00002868 aeu_mask &= ~(asserted & 0x3ff);
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07002869 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002870
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07002871 REG_WR(bp, aeu_addr, aeu_mask);
2872 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002873
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07002874 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002875 bp->attn_state |= asserted;
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07002876 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002877
2878 if (asserted & ATTN_HARD_WIRED_MASK) {
2879 if (asserted & ATTN_NIG_FOR_FUNC) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002880
Eilon Greensteina5e9a7c2009-01-14 21:26:01 -08002881 bnx2x_acquire_phy_lock(bp);
2882
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002883 /* save nig interrupt mask */
Eilon Greenstein87942b42009-02-12 08:36:49 +00002884 nig_mask = REG_RD(bp, nig_int_mask_addr);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002885 REG_WR(bp, nig_int_mask_addr, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002886
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002887 bnx2x_link_attn(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002888
2889 /* handle unicore attn? */
2890 }
2891 if (asserted & ATTN_SW_TIMER_4_FUNC)
2892 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2893
2894 if (asserted & GPIO_2_FUNC)
2895 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2896
2897 if (asserted & GPIO_3_FUNC)
2898 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2899
2900 if (asserted & GPIO_4_FUNC)
2901 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2902
2903 if (port == 0) {
2904 if (asserted & ATTN_GENERAL_ATTN_1) {
2905 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2906 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2907 }
2908 if (asserted & ATTN_GENERAL_ATTN_2) {
2909 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2910 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2911 }
2912 if (asserted & ATTN_GENERAL_ATTN_3) {
2913 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2914 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2915 }
2916 } else {
2917 if (asserted & ATTN_GENERAL_ATTN_4) {
2918 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2919 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2920 }
2921 if (asserted & ATTN_GENERAL_ATTN_5) {
2922 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2923 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2924 }
2925 if (asserted & ATTN_GENERAL_ATTN_6) {
2926 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2927 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2928 }
2929 }
2930
2931 } /* if hardwired */
2932
Eilon Greenstein5c862842008-08-13 15:51:48 -07002933 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2934 asserted, hc_addr);
2935 REG_WR(bp, hc_addr, asserted);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002936
2937 /* now set back the mask */
Eilon Greensteina5e9a7c2009-01-14 21:26:01 -08002938 if (asserted & ATTN_NIG_FOR_FUNC) {
Eilon Greenstein87942b42009-02-12 08:36:49 +00002939 REG_WR(bp, nig_int_mask_addr, nig_mask);
Eilon Greensteina5e9a7c2009-01-14 21:26:01 -08002940 bnx2x_release_phy_lock(bp);
2941 }
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002942}
2943
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00002944static inline void bnx2x_fan_failure(struct bnx2x *bp)
2945{
2946 int port = BP_PORT(bp);
2947
2948 /* mark the failure */
2949 bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2950 bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2951 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2952 bp->link_params.ext_phy_config);
2953
2954 /* log the failure */
Joe Perches7995c642010-02-17 15:01:52 +00002955 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
2956 "Please contact Dell Support for assistance.\n");
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00002957}
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00002958
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002959static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2960{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002961 int port = BP_PORT(bp);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002962 int reg_offset;
Eilon Greenstein4d295db2009-07-21 05:47:47 +00002963 u32 val, swap_val, swap_override;
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002964
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002965 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2966 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002967
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002968 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002969
2970 val = REG_RD(bp, reg_offset);
2971 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2972 REG_WR(bp, reg_offset, val);
2973
2974 BNX2X_ERR("SPIO5 hw attention\n");
2975
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00002976 /* Fan failure attention */
Eilon Greenstein35b19ba2009-02-12 08:36:47 +00002977 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
2978 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
Eilon Greenstein17de50b2008-08-13 15:56:59 -07002979 /* Low power mode is controlled by GPIO 2 */
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002980 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Eilon Greenstein17de50b2008-08-13 15:56:59 -07002981 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00002982 /* The PHY reset is controlled by GPIO 1 */
2983 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2984 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002985 break;
2986
Eilon Greenstein4d295db2009-07-21 05:47:47 +00002987 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
2988 /* The PHY reset is controlled by GPIO 1 */
2989 /* fake the port number to cancel the swap done in
2990 set_gpio() */
2991 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
2992 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
2993 port = (swap_val && swap_override) ^ 1;
2994 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2995 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2996 break;
2997
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08002998 default:
2999 break;
3000 }
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00003001 bnx2x_fan_failure(bp);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003002 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003003
Eilon Greenstein589abe32009-02-12 08:36:55 +00003004 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3005 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3006 bnx2x_acquire_phy_lock(bp);
3007 bnx2x_handle_module_detect_int(&bp->link_params);
3008 bnx2x_release_phy_lock(bp);
3009 }
3010
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003011 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3012
3013 val = REG_RD(bp, reg_offset);
3014 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3015 REG_WR(bp, reg_offset, val);
3016
3017 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
Eilon Greenstein0fc5d002009-08-12 08:24:05 +00003018 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003019 bnx2x_panic();
3020 }
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003021}
3022
3023static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3024{
3025 u32 val;
3026
Eilon Greenstein0626b892009-02-12 08:38:14 +00003027 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003028
3029 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3030 BNX2X_ERR("DB hw attention 0x%x\n", val);
3031 /* DORQ discard attention */
3032 if (val & 0x2)
3033 BNX2X_ERR("FATAL error from DORQ\n");
3034 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003035
3036 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3037
3038 int port = BP_PORT(bp);
3039 int reg_offset;
3040
3041 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3042 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3043
3044 val = REG_RD(bp, reg_offset);
3045 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3046 REG_WR(bp, reg_offset, val);
3047
3048 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
Eilon Greenstein0fc5d002009-08-12 08:24:05 +00003049 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003050 bnx2x_panic();
3051 }
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003052}
3053
3054static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3055{
3056 u32 val;
3057
3058 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3059
3060 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3061 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3062 /* CFC error attention */
3063 if (val & 0x2)
3064 BNX2X_ERR("FATAL error from CFC\n");
3065 }
3066
3067 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3068
3069 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3070 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3071 /* RQ_USDMDP_FIFO_OVERFLOW */
3072 if (val & 0x18000)
3073 BNX2X_ERR("FATAL error from PXP\n");
3074 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003075
3076 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3077
3078 int port = BP_PORT(bp);
3079 int reg_offset;
3080
3081 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3082 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3083
3084 val = REG_RD(bp, reg_offset);
3085 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3086 REG_WR(bp, reg_offset, val);
3087
3088 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
Eilon Greenstein0fc5d002009-08-12 08:24:05 +00003089 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003090 bnx2x_panic();
3091 }
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003092}
3093
3094static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3095{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003096 u32 val;
3097
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003098 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3099
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003100 if (attn & BNX2X_PMF_LINK_ASSERT) {
3101 int func = BP_FUNC(bp);
3102
3103 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07003104 bp->mf_config = SHMEM_RD(bp,
3105 mf_cfg.func_mf_config[func].config);
Eilon Greenstein2691d512009-08-12 08:22:08 +00003106 val = SHMEM_RD(bp, func_mb[func].drv_status);
3107 if (val & DRV_STATUS_DCC_EVENT_MASK)
3108 bnx2x_dcc_event(bp,
3109 (val & DRV_STATUS_DCC_EVENT_MASK));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003110 bnx2x__link_status_update(bp);
Eilon Greenstein2691d512009-08-12 08:22:08 +00003111 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003112 bnx2x_pmf_update(bp);
3113
3114 } else if (attn & BNX2X_MC_ASSERT_BITS) {
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003115
3116 BNX2X_ERR("MC assert!\n");
3117 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3121 bnx2x_panic();
3122
3123 } else if (attn & BNX2X_MCP_ASSERT) {
3124
3125 BNX2X_ERR("MCP assert!\n");
3126 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003127 bnx2x_fw_dump(bp);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003128
3129 } else
3130 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3131 }
3132
3133 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003134 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3135 if (attn & BNX2X_GRC_TIMEOUT) {
3136 val = CHIP_IS_E1H(bp) ?
3137 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
3138 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3139 }
3140 if (attn & BNX2X_GRC_RSV) {
3141 val = CHIP_IS_E1H(bp) ?
3142 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
3143 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3144 }
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003145 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003146 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003147}
3148
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003149static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
3150static int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
3151
3152
3153#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3154#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3155#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3156#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3157#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
3158#define CHIP_PARITY_SUPPORTED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
3159/*
3160 * should be run under rtnl lock
3161 */
3162static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3163{
3164 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3165 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3166 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3167 barrier();
3168 mmiowb();
3169}
3170
3171/*
3172 * should be run under rtnl lock
3173 */
3174static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3175{
3176 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3177 val |= (1 << 16);
3178 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3179 barrier();
3180 mmiowb();
3181}
3182
3183/*
3184 * should be run under rtnl lock
3185 */
3186static inline bool bnx2x_reset_is_done(struct bnx2x *bp)
3187{
3188 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3189 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3190 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3191}
3192
3193/*
3194 * should be run under rtnl lock
3195 */
3196static inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3197{
3198 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3199
3200 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3201
3202 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3203 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3204 barrier();
3205 mmiowb();
3206}
3207
3208/*
3209 * should be run under rtnl lock
3210 */
3211static inline u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3212{
3213 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3214
3215 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3216
3217 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3218 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3219 barrier();
3220 mmiowb();
3221
3222 return val1;
3223}
3224
3225/*
3226 * should be run under rtnl lock
3227 */
3228static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3229{
3230 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3231}
3232
3233static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3234{
3235 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3236 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3237}
3238
3239static inline void _print_next_block(int idx, const char *blk)
3240{
3241 if (idx)
3242 pr_cont(", ");
3243 pr_cont("%s", blk);
3244}
3245
3246static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3247{
3248 int i = 0;
3249 u32 cur_bit = 0;
3250 for (i = 0; sig; i++) {
3251 cur_bit = ((u32)0x1 << i);
3252 if (sig & cur_bit) {
3253 switch (cur_bit) {
3254 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3255 _print_next_block(par_num++, "BRB");
3256 break;
3257 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3258 _print_next_block(par_num++, "PARSER");
3259 break;
3260 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3261 _print_next_block(par_num++, "TSDM");
3262 break;
3263 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3264 _print_next_block(par_num++, "SEARCHER");
3265 break;
3266 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3267 _print_next_block(par_num++, "TSEMI");
3268 break;
3269 }
3270
3271 /* Clear the bit */
3272 sig &= ~cur_bit;
3273 }
3274 }
3275
3276 return par_num;
3277}
3278
3279static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3280{
3281 int i = 0;
3282 u32 cur_bit = 0;
3283 for (i = 0; sig; i++) {
3284 cur_bit = ((u32)0x1 << i);
3285 if (sig & cur_bit) {
3286 switch (cur_bit) {
3287 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3288 _print_next_block(par_num++, "PBCLIENT");
3289 break;
3290 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3291 _print_next_block(par_num++, "QM");
3292 break;
3293 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3294 _print_next_block(par_num++, "XSDM");
3295 break;
3296 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3297 _print_next_block(par_num++, "XSEMI");
3298 break;
3299 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3300 _print_next_block(par_num++, "DOORBELLQ");
3301 break;
3302 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3303 _print_next_block(par_num++, "VAUX PCI CORE");
3304 break;
3305 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3306 _print_next_block(par_num++, "DEBUG");
3307 break;
3308 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3309 _print_next_block(par_num++, "USDM");
3310 break;
3311 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3312 _print_next_block(par_num++, "USEMI");
3313 break;
3314 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3315 _print_next_block(par_num++, "UPB");
3316 break;
3317 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3318 _print_next_block(par_num++, "CSDM");
3319 break;
3320 }
3321
3322 /* Clear the bit */
3323 sig &= ~cur_bit;
3324 }
3325 }
3326
3327 return par_num;
3328}
3329
3330static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3331{
3332 int i = 0;
3333 u32 cur_bit = 0;
3334 for (i = 0; sig; i++) {
3335 cur_bit = ((u32)0x1 << i);
3336 if (sig & cur_bit) {
3337 switch (cur_bit) {
3338 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3339 _print_next_block(par_num++, "CSEMI");
3340 break;
3341 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3342 _print_next_block(par_num++, "PXP");
3343 break;
3344 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3345 _print_next_block(par_num++,
3346 "PXPPCICLOCKCLIENT");
3347 break;
3348 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3349 _print_next_block(par_num++, "CFC");
3350 break;
3351 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3352 _print_next_block(par_num++, "CDU");
3353 break;
3354 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3355 _print_next_block(par_num++, "IGU");
3356 break;
3357 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3358 _print_next_block(par_num++, "MISC");
3359 break;
3360 }
3361
3362 /* Clear the bit */
3363 sig &= ~cur_bit;
3364 }
3365 }
3366
3367 return par_num;
3368}
3369
3370static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3371{
3372 int i = 0;
3373 u32 cur_bit = 0;
3374 for (i = 0; sig; i++) {
3375 cur_bit = ((u32)0x1 << i);
3376 if (sig & cur_bit) {
3377 switch (cur_bit) {
3378 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3379 _print_next_block(par_num++, "MCP ROM");
3380 break;
3381 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3382 _print_next_block(par_num++, "MCP UMP RX");
3383 break;
3384 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3385 _print_next_block(par_num++, "MCP UMP TX");
3386 break;
3387 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3388 _print_next_block(par_num++, "MCP SCPAD");
3389 break;
3390 }
3391
3392 /* Clear the bit */
3393 sig &= ~cur_bit;
3394 }
3395 }
3396
3397 return par_num;
3398}
3399
3400static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3401 u32 sig2, u32 sig3)
3402{
3403 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3404 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3405 int par_num = 0;
3406 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3407 "[0]:0x%08x [1]:0x%08x "
3408 "[2]:0x%08x [3]:0x%08x\n",
3409 sig0 & HW_PRTY_ASSERT_SET_0,
3410 sig1 & HW_PRTY_ASSERT_SET_1,
3411 sig2 & HW_PRTY_ASSERT_SET_2,
3412 sig3 & HW_PRTY_ASSERT_SET_3);
3413 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3414 bp->dev->name);
3415 par_num = bnx2x_print_blocks_with_parity0(
3416 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3417 par_num = bnx2x_print_blocks_with_parity1(
3418 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3419 par_num = bnx2x_print_blocks_with_parity2(
3420 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3421 par_num = bnx2x_print_blocks_with_parity3(
3422 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3423 printk("\n");
3424 return true;
3425 } else
3426 return false;
3427}
3428
3429static bool bnx2x_chk_parity_attn(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003430{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003431 struct attn_route attn;
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003432 int port = BP_PORT(bp);
3433
3434 attn.sig[0] = REG_RD(bp,
3435 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3436 port*4);
3437 attn.sig[1] = REG_RD(bp,
3438 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3439 port*4);
3440 attn.sig[2] = REG_RD(bp,
3441 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3442 port*4);
3443 attn.sig[3] = REG_RD(bp,
3444 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3445 port*4);
3446
3447 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3448 attn.sig[3]);
3449}
3450
3451static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3452{
3453 struct attn_route attn, *group_mask;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003454 int port = BP_PORT(bp);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003455 int index;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003456 u32 reg_addr;
3457 u32 val;
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07003458 u32 aeu_mask;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003459
3460 /* need to take HW lock because MCP or other port might also
3461 try to handle this event */
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07003462 bnx2x_acquire_alr(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003463
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003464 if (bnx2x_chk_parity_attn(bp)) {
3465 bp->recovery_state = BNX2X_RECOVERY_INIT;
3466 bnx2x_set_reset_in_progress(bp);
3467 schedule_delayed_work(&bp->reset_task, 0);
3468 /* Disable HW interrupts */
3469 bnx2x_int_disable(bp);
3470 bnx2x_release_alr(bp);
3471 /* In case of parity errors don't handle attentions so that
3472 * other function would "see" parity errors.
3473 */
3474 return;
3475 }
3476
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003477 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3478 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3479 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3480 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003481 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
3482 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003483
3484 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3485 if (deasserted & (1 << index)) {
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003486 group_mask = &bp->attn_group[index];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003487
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003488 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003489 index, group_mask->sig[0], group_mask->sig[1],
3490 group_mask->sig[2], group_mask->sig[3]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003491
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003492 bnx2x_attn_int_deasserted3(bp,
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003493 attn.sig[3] & group_mask->sig[3]);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003494 bnx2x_attn_int_deasserted1(bp,
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003495 attn.sig[1] & group_mask->sig[1]);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003496 bnx2x_attn_int_deasserted2(bp,
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003497 attn.sig[2] & group_mask->sig[2]);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003498 bnx2x_attn_int_deasserted0(bp,
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003499 attn.sig[0] & group_mask->sig[0]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003500 }
3501 }
3502
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07003503 bnx2x_release_alr(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003504
Eilon Greenstein5c862842008-08-13 15:51:48 -07003505 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003506
3507 val = ~deasserted;
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07003508 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
3509 val, reg_addr);
Eilon Greenstein5c862842008-08-13 15:51:48 -07003510 REG_WR(bp, reg_addr, val);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003511
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003512 if (~bp->attn_state & deasserted)
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07003513 BNX2X_ERR("IGU ERROR\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003514
3515 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3516 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3517
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07003518 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3519 aeu_mask = REG_RD(bp, reg_addr);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003520
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07003521 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3522 aeu_mask, deasserted);
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003523 aeu_mask |= (deasserted & 0x3ff);
Eilon Greenstein3fcaf2e2008-08-13 15:50:45 -07003524 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3525
3526 REG_WR(bp, reg_addr, aeu_mask);
3527 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003528
3529 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3530 bp->attn_state &= ~deasserted;
3531 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3532}
3533
3534static void bnx2x_attn_int(struct bnx2x *bp)
3535{
3536 /* read local copy of bits */
Eilon Greenstein68d59482009-01-14 21:27:36 -08003537 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3538 attn_bits);
3539 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3540 attn_bits_ack);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003541 u32 attn_state = bp->attn_state;
3542
3543 /* look for changed bits */
3544 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3545 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3546
3547 DP(NETIF_MSG_HW,
3548 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3549 attn_bits, attn_ack, asserted, deasserted);
3550
3551 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003552 BNX2X_ERR("BAD attention state\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003553
3554 /* handle bits that were raised */
3555 if (asserted)
3556 bnx2x_attn_int_asserted(bp, asserted);
3557
3558 if (deasserted)
3559 bnx2x_attn_int_deasserted(bp, deasserted);
3560}
3561
3562static void bnx2x_sp_task(struct work_struct *work)
3563{
Eilon Greenstein1cf167f2009-01-14 21:22:18 -08003564 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003565 u16 status;
3566
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003567
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003568 /* Return here if interrupt is disabled */
3569 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
Eilon Greenstein3196a882008-08-13 15:58:49 -07003570 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003571 return;
3572 }
3573
3574 status = bnx2x_update_dsb_idx(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003575/* if (status == 0) */
3576/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003577
Eilon Greenstein3196a882008-08-13 15:58:49 -07003578 DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003579
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003580 /* HW attentions */
3581 if (status & 0x1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003582 bnx2x_attn_int(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003583
Eilon Greenstein68d59482009-01-14 21:27:36 -08003584 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003585 IGU_INT_NOP, 1);
3586 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
3587 IGU_INT_NOP, 1);
3588 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
3589 IGU_INT_NOP, 1);
3590 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
3591 IGU_INT_NOP, 1);
3592 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
3593 IGU_INT_ENABLE, 1);
Eliezer Tamir877e9aa2008-02-28 11:55:53 -08003594
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003595}
3596
3597static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3598{
3599 struct net_device *dev = dev_instance;
3600 struct bnx2x *bp = netdev_priv(dev);
3601
3602 /* Return here if interrupt is disabled */
3603 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
Eilon Greenstein3196a882008-08-13 15:58:49 -07003604 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003605 return IRQ_HANDLED;
3606 }
3607
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08003608 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003609
3610#ifdef BNX2X_STOP_ON_ERROR
3611 if (unlikely(bp->panic))
3612 return IRQ_HANDLED;
3613#endif
3614
Michael Chan993ac7b2009-10-10 13:46:56 +00003615#ifdef BCM_CNIC
3616 {
3617 struct cnic_ops *c_ops;
3618
3619 rcu_read_lock();
3620 c_ops = rcu_dereference(bp->cnic_ops);
3621 if (c_ops)
3622 c_ops->cnic_handler(bp->cnic_data, NULL);
3623 rcu_read_unlock();
3624 }
3625#endif
Eilon Greenstein1cf167f2009-01-14 21:22:18 -08003626 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003627
3628 return IRQ_HANDLED;
3629}
3630
3631/* end of slow path */
3632
3633/* Statistics */
3634
3635/****************************************************************************
3636* Macros
3637****************************************************************************/
3638
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003639/* sum[hi:lo] += add[hi:lo] */
3640#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
3641 do { \
3642 s_lo += a_lo; \
Eilon Greensteinf5ba6772009-01-14 21:29:18 -08003643 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003644 } while (0)
3645
3646/* difference = minuend - subtrahend */
3647#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
3648 do { \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003649 if (m_lo < s_lo) { \
3650 /* underflow */ \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003651 d_hi = m_hi - s_hi; \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003652 if (d_hi > 0) { \
Eilon Greenstein6378c022008-08-13 15:59:25 -07003653 /* we can 'loan' 1 */ \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003654 d_hi--; \
3655 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003656 } else { \
Eilon Greenstein6378c022008-08-13 15:59:25 -07003657 /* m_hi <= s_hi */ \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003658 d_hi = 0; \
3659 d_lo = 0; \
3660 } \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003661 } else { \
3662 /* m_lo >= s_lo */ \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003663 if (m_hi < s_hi) { \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003664 d_hi = 0; \
3665 d_lo = 0; \
3666 } else { \
Eilon Greenstein6378c022008-08-13 15:59:25 -07003667 /* m_hi >= s_hi */ \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003668 d_hi = m_hi - s_hi; \
3669 d_lo = m_lo - s_lo; \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003670 } \
3671 } \
3672 } while (0)
3673
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003674#define UPDATE_STAT64(s, t) \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003675 do { \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003676 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
3677 diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
3678 pstats->mac_stx[0].t##_hi = new->s##_hi; \
3679 pstats->mac_stx[0].t##_lo = new->s##_lo; \
3680 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
3681 pstats->mac_stx[1].t##_lo, diff.lo); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003682 } while (0)
3683
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003684#define UPDATE_STAT64_NIG(s, t) \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003685 do { \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003686 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
3687 diff.lo, new->s##_lo, old->s##_lo); \
3688 ADD_64(estats->t##_hi, diff.hi, \
3689 estats->t##_lo, diff.lo); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003690 } while (0)
3691
3692/* sum[hi:lo] += add */
3693#define ADD_EXTEND_64(s_hi, s_lo, a) \
3694 do { \
3695 s_lo += a; \
3696 s_hi += (s_lo < a) ? 1 : 0; \
3697 } while (0)
3698
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003699#define UPDATE_EXTEND_STAT(s) \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003700 do { \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003701 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
3702 pstats->mac_stx[1].s##_lo, \
3703 new->s); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003704 } while (0)
3705
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003706#define UPDATE_EXTEND_TSTAT(s, t) \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003707 do { \
Eilon Greenstein4781bfa2009-02-12 08:38:17 +00003708 diff = le32_to_cpu(tclient->s) - le32_to_cpu(old_tclient->s); \
3709 old_tclient->s = tclient->s; \
Eilon Greensteinde832a52009-02-12 08:36:33 +00003710 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3711 } while (0)
3712
3713#define UPDATE_EXTEND_USTAT(s, t) \
3714 do { \
3715 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
3716 old_uclient->s = uclient->s; \
3717 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003718 } while (0)
3719
3720#define UPDATE_EXTEND_XSTAT(s, t) \
3721 do { \
Eilon Greenstein4781bfa2009-02-12 08:38:17 +00003722 diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \
3723 old_xclient->s = xclient->s; \
Eilon Greensteinde832a52009-02-12 08:36:33 +00003724 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
3725 } while (0)
3726
3727/* minuend -= subtrahend */
3728#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
3729 do { \
3730 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
3731 } while (0)
3732
3733/* minuend[hi:lo] -= subtrahend */
3734#define SUB_EXTEND_64(m_hi, m_lo, s) \
3735 do { \
3736 SUB_64(m_hi, 0, m_lo, s); \
3737 } while (0)
3738
3739#define SUB_EXTEND_USTAT(s, t) \
3740 do { \
3741 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
3742 SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003743 } while (0)
3744
3745/*
3746 * General service functions
3747 */
3748
3749static inline long bnx2x_hilo(u32 *hiref)
3750{
3751 u32 lo = *(hiref + 1);
3752#if (BITS_PER_LONG == 64)
3753 u32 hi = *hiref;
3754
3755 return HILO_U64(hi, lo);
3756#else
3757 return lo;
3758#endif
3759}
3760
3761/*
3762 * Init service functions
3763 */
3764
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003765static void bnx2x_storm_stats_post(struct bnx2x *bp)
3766{
3767 if (!bp->stats_pending) {
3768 struct eth_query_ramrod_data ramrod_data = {0};
Eilon Greensteinde832a52009-02-12 08:36:33 +00003769 int i, rc;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003770
3771 ramrod_data.drv_counter = bp->stats_counter++;
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08003772 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
Eilon Greensteinde832a52009-02-12 08:36:33 +00003773 for_each_queue(bp, i)
3774 ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003775
3776 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3777 ((u32 *)&ramrod_data)[1],
3778 ((u32 *)&ramrod_data)[0], 0);
3779 if (rc == 0) {
3780 /* stats ramrod has it's own slot on the spq */
3781 bp->spq_left++;
3782 bp->stats_pending = 1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003783 }
3784 }
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003785}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003786
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003787static void bnx2x_hw_stats_post(struct bnx2x *bp)
3788{
3789 struct dmae_command *dmae = &bp->stats_dmae;
3790 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3791
3792 *stats_comp = DMAE_COMP_VAL;
Eilon Greensteinde832a52009-02-12 08:36:33 +00003793 if (CHIP_REV_IS_SLOW(bp))
3794 return;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003795
3796 /* loader */
3797 if (bp->executer_idx) {
3798 int loader_idx = PMF_DMAE_C(bp);
3799
3800 memset(dmae, 0, sizeof(struct dmae_command));
3801
3802 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3803 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3804 DMAE_CMD_DST_RESET |
3805#ifdef __BIG_ENDIAN
3806 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3807#else
3808 DMAE_CMD_ENDIANITY_DW_SWAP |
3809#endif
3810 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3811 DMAE_CMD_PORT_0) |
3812 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3813 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3814 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3815 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3816 sizeof(struct dmae_command) *
3817 (loader_idx + 1)) >> 2;
3818 dmae->dst_addr_hi = 0;
3819 dmae->len = sizeof(struct dmae_command) >> 2;
3820 if (CHIP_IS_E1(bp))
3821 dmae->len--;
3822 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3823 dmae->comp_addr_hi = 0;
3824 dmae->comp_val = 1;
3825
3826 *stats_comp = 0;
3827 bnx2x_post_dmae(bp, dmae, loader_idx);
3828
3829 } else if (bp->func_stx) {
3830 *stats_comp = 0;
3831 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3832 }
3833}
3834
3835static int bnx2x_stats_comp(struct bnx2x *bp)
3836{
3837 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3838 int cnt = 10;
3839
3840 might_sleep();
3841 while (*stats_comp != DMAE_COMP_VAL) {
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003842 if (!cnt) {
3843 BNX2X_ERR("timeout waiting for stats finished\n");
3844 break;
3845 }
3846 cnt--;
Yitchak Gertner12469402008-08-13 15:52:08 -07003847 msleep(1);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003848 }
3849 return 1;
3850}
3851
3852/*
3853 * Statistics service functions
3854 */
3855
3856static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3857{
3858 struct dmae_command *dmae;
3859 u32 opcode;
3860 int loader_idx = PMF_DMAE_C(bp);
3861 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3862
3863 /* sanity */
3864 if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3865 BNX2X_ERR("BUG!\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003866 return;
3867 }
3868
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003869 bp->executer_idx = 0;
3870
3871 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3872 DMAE_CMD_C_ENABLE |
3873 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3874#ifdef __BIG_ENDIAN
3875 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3876#else
3877 DMAE_CMD_ENDIANITY_DW_SWAP |
3878#endif
3879 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3880 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3881
3882 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3883 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3884 dmae->src_addr_lo = bp->port.port_stx >> 2;
3885 dmae->src_addr_hi = 0;
3886 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3887 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3888 dmae->len = DMAE_LEN32_RD_MAX;
3889 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3890 dmae->comp_addr_hi = 0;
3891 dmae->comp_val = 1;
3892
3893 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3894 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3895 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3896 dmae->src_addr_hi = 0;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07003897 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3898 DMAE_LEN32_RD_MAX * 4);
3899 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3900 DMAE_LEN32_RD_MAX * 4);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003901 dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3902 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3903 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3904 dmae->comp_val = DMAE_COMP_VAL;
3905
3906 *stats_comp = 0;
3907 bnx2x_hw_stats_post(bp);
3908 bnx2x_stats_comp(bp);
3909}
3910
3911static void bnx2x_port_stats_init(struct bnx2x *bp)
3912{
3913 struct dmae_command *dmae;
3914 int port = BP_PORT(bp);
3915 int vn = BP_E1HVN(bp);
3916 u32 opcode;
3917 int loader_idx = PMF_DMAE_C(bp);
3918 u32 mac_addr;
3919 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3920
3921 /* sanity */
3922 if (!bp->link_vars.link_up || !bp->port.pmf) {
3923 BNX2X_ERR("BUG!\n");
3924 return;
3925 }
3926
3927 bp->executer_idx = 0;
3928
3929 /* MCP */
3930 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3931 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3932 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3933#ifdef __BIG_ENDIAN
3934 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3935#else
3936 DMAE_CMD_ENDIANITY_DW_SWAP |
3937#endif
3938 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3939 (vn << DMAE_CMD_E1HVN_SHIFT));
3940
3941 if (bp->port.port_stx) {
3942
3943 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3944 dmae->opcode = opcode;
3945 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3946 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3947 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3948 dmae->dst_addr_hi = 0;
3949 dmae->len = sizeof(struct host_port_stats) >> 2;
3950 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3951 dmae->comp_addr_hi = 0;
3952 dmae->comp_val = 1;
3953 }
3954
3955 if (bp->func_stx) {
3956
3957 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3958 dmae->opcode = opcode;
3959 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3960 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3961 dmae->dst_addr_lo = bp->func_stx >> 2;
3962 dmae->dst_addr_hi = 0;
3963 dmae->len = sizeof(struct host_func_stats) >> 2;
3964 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3965 dmae->comp_addr_hi = 0;
3966 dmae->comp_val = 1;
3967 }
3968
3969 /* MAC */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003970 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3971 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3972 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3973#ifdef __BIG_ENDIAN
3974 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3975#else
3976 DMAE_CMD_ENDIANITY_DW_SWAP |
3977#endif
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07003978 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3979 (vn << DMAE_CMD_E1HVN_SHIFT));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003980
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003981 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003982
3983 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3984 NIG_REG_INGRESS_BMAC0_MEM);
3985
3986 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3987 BIGMAC_REGISTER_TX_STAT_GTBYT */
3988 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3989 dmae->opcode = opcode;
3990 dmae->src_addr_lo = (mac_addr +
3991 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3992 dmae->src_addr_hi = 0;
3993 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3994 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3995 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3996 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3997 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3998 dmae->comp_addr_hi = 0;
3999 dmae->comp_val = 1;
4000
4001 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
4002 BIGMAC_REGISTER_RX_STAT_GRIPJ */
4003 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4004 dmae->opcode = opcode;
4005 dmae->src_addr_lo = (mac_addr +
4006 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
4007 dmae->src_addr_hi = 0;
4008 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004009 offsetof(struct bmac_stats, rx_stat_gr64_lo));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004010 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004011 offsetof(struct bmac_stats, rx_stat_gr64_lo));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004012 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
4013 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
4014 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4015 dmae->comp_addr_hi = 0;
4016 dmae->comp_val = 1;
4017
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004018 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004019
4020 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
4021
4022 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
4023 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4024 dmae->opcode = opcode;
4025 dmae->src_addr_lo = (mac_addr +
4026 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
4027 dmae->src_addr_hi = 0;
4028 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
4029 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
4030 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
4031 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4032 dmae->comp_addr_hi = 0;
4033 dmae->comp_val = 1;
4034
4035 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
4036 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4037 dmae->opcode = opcode;
4038 dmae->src_addr_lo = (mac_addr +
4039 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
4040 dmae->src_addr_hi = 0;
4041 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004042 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004043 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004044 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004045 dmae->len = 1;
4046 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4047 dmae->comp_addr_hi = 0;
4048 dmae->comp_val = 1;
4049
4050 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
4051 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4052 dmae->opcode = opcode;
4053 dmae->src_addr_lo = (mac_addr +
4054 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
4055 dmae->src_addr_hi = 0;
4056 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004057 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004058 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004059 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004060 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
4061 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4062 dmae->comp_addr_hi = 0;
4063 dmae->comp_val = 1;
4064 }
4065
4066 /* NIG */
4067 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004068 dmae->opcode = opcode;
4069 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
4070 NIG_REG_STAT0_BRB_DISCARD) >> 2;
4071 dmae->src_addr_hi = 0;
4072 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
4073 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
4074 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
4075 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4076 dmae->comp_addr_hi = 0;
4077 dmae->comp_val = 1;
4078
4079 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4080 dmae->opcode = opcode;
4081 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
4082 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
4083 dmae->src_addr_hi = 0;
4084 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
4085 offsetof(struct nig_stats, egress_mac_pkt0_lo));
4086 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
4087 offsetof(struct nig_stats, egress_mac_pkt0_lo));
4088 dmae->len = (2*sizeof(u32)) >> 2;
4089 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4090 dmae->comp_addr_hi = 0;
4091 dmae->comp_val = 1;
4092
4093 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004094 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
4095 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4096 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4097#ifdef __BIG_ENDIAN
4098 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4099#else
4100 DMAE_CMD_ENDIANITY_DW_SWAP |
4101#endif
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004102 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4103 (vn << DMAE_CMD_E1HVN_SHIFT));
4104 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
4105 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004106 dmae->src_addr_hi = 0;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004107 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
4108 offsetof(struct nig_stats, egress_mac_pkt1_lo));
4109 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
4110 offsetof(struct nig_stats, egress_mac_pkt1_lo));
4111 dmae->len = (2*sizeof(u32)) >> 2;
4112 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4113 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4114 dmae->comp_val = DMAE_COMP_VAL;
4115
4116 *stats_comp = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004117}
4118
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004119static void bnx2x_func_stats_init(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004120{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004121 struct dmae_command *dmae = &bp->stats_dmae;
4122 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004123
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004124 /* sanity */
4125 if (!bp->func_stx) {
4126 BNX2X_ERR("BUG!\n");
4127 return;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004128 }
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004129
4130 bp->executer_idx = 0;
4131 memset(dmae, 0, sizeof(struct dmae_command));
4132
4133 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4134 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4135 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4136#ifdef __BIG_ENDIAN
4137 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4138#else
4139 DMAE_CMD_ENDIANITY_DW_SWAP |
4140#endif
4141 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4142 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
4143 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
4144 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
4145 dmae->dst_addr_lo = bp->func_stx >> 2;
4146 dmae->dst_addr_hi = 0;
4147 dmae->len = sizeof(struct host_func_stats) >> 2;
4148 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4149 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4150 dmae->comp_val = DMAE_COMP_VAL;
4151
4152 *stats_comp = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004153}
4154
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004155static void bnx2x_stats_start(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004156{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004157 if (bp->port.pmf)
4158 bnx2x_port_stats_init(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004159
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004160 else if (bp->func_stx)
4161 bnx2x_func_stats_init(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004162
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004163 bnx2x_hw_stats_post(bp);
4164 bnx2x_storm_stats_post(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004165}
4166
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004167static void bnx2x_stats_pmf_start(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004168{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004169 bnx2x_stats_comp(bp);
4170 bnx2x_stats_pmf_update(bp);
4171 bnx2x_stats_start(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004172}
4173
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004174static void bnx2x_stats_restart(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004175{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004176 bnx2x_stats_comp(bp);
4177 bnx2x_stats_start(bp);
4178}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004179
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004180static void bnx2x_bmac_stats_update(struct bnx2x *bp)
4181{
4182 struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
4183 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004184 struct bnx2x_eth_stats *estats = &bp->eth_stats;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +00004185 struct {
4186 u32 lo;
4187 u32 hi;
4188 } diff;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004189
4190 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
4191 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
4192 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
4193 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
4194 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
4195 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
Yitchak Gertner66e855f2008-08-13 15:49:05 -07004196 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004197 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004198 UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004199 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
4200 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
4201 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
4202 UPDATE_STAT64(tx_stat_gt127,
4203 tx_stat_etherstatspkts65octetsto127octets);
4204 UPDATE_STAT64(tx_stat_gt255,
4205 tx_stat_etherstatspkts128octetsto255octets);
4206 UPDATE_STAT64(tx_stat_gt511,
4207 tx_stat_etherstatspkts256octetsto511octets);
4208 UPDATE_STAT64(tx_stat_gt1023,
4209 tx_stat_etherstatspkts512octetsto1023octets);
4210 UPDATE_STAT64(tx_stat_gt1518,
4211 tx_stat_etherstatspkts1024octetsto1522octets);
4212 UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
4213 UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
4214 UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
4215 UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
4216 UPDATE_STAT64(tx_stat_gterr,
4217 tx_stat_dot3statsinternalmactransmiterrors);
4218 UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004219
4220 estats->pause_frames_received_hi =
4221 pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
4222 estats->pause_frames_received_lo =
4223 pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
4224
4225 estats->pause_frames_sent_hi =
4226 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
4227 estats->pause_frames_sent_lo =
4228 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004229}
4230
4231static void bnx2x_emac_stats_update(struct bnx2x *bp)
4232{
4233 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
4234 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004235 struct bnx2x_eth_stats *estats = &bp->eth_stats;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004236
4237 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
4238 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
4239 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
4240 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
4241 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
4242 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
4243 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
4244 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
4245 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
4246 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
4247 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
4248 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
4249 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
4250 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
4251 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
4252 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
4253 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
4254 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
4255 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
4256 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
4257 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
4258 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
4259 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
4260 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
4261 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
4262 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
4263 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
4264 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
4265 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
4266 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
4267 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004268
4269 estats->pause_frames_received_hi =
4270 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
4271 estats->pause_frames_received_lo =
4272 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
4273 ADD_64(estats->pause_frames_received_hi,
4274 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
4275 estats->pause_frames_received_lo,
4276 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
4277
4278 estats->pause_frames_sent_hi =
4279 pstats->mac_stx[1].tx_stat_outxonsent_hi;
4280 estats->pause_frames_sent_lo =
4281 pstats->mac_stx[1].tx_stat_outxonsent_lo;
4282 ADD_64(estats->pause_frames_sent_hi,
4283 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
4284 estats->pause_frames_sent_lo,
4285 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004286}
4287
4288static int bnx2x_hw_stats_update(struct bnx2x *bp)
4289{
4290 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
4291 struct nig_stats *old = &(bp->port.old_nig_stats);
4292 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
4293 struct bnx2x_eth_stats *estats = &bp->eth_stats;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +00004294 struct {
4295 u32 lo;
4296 u32 hi;
4297 } diff;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004298
4299 if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
4300 bnx2x_bmac_stats_update(bp);
4301
4302 else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
4303 bnx2x_emac_stats_update(bp);
4304
4305 else { /* unreached */
Eilon Greensteinc3eefaf2009-03-02 08:01:09 +00004306 BNX2X_ERR("stats updated by DMAE but no MAC active\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004307 return -1;
4308 }
4309
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004310 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
4311 new->brb_discard - old->brb_discard);
Yitchak Gertner66e855f2008-08-13 15:49:05 -07004312 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
4313 new->brb_truncate - old->brb_truncate);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004314
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004315 UPDATE_STAT64_NIG(egress_mac_pkt0,
4316 etherstatspkts1024octetsto1522octets);
4317 UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004318
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004319 memcpy(old, new, sizeof(struct nig_stats));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004320
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004321 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
4322 sizeof(struct mac_stx));
4323 estats->brb_drop_hi = pstats->brb_drop_hi;
4324 estats->brb_drop_lo = pstats->brb_drop_lo;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004325
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004326 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004327
Vladislav Zolotarov2145a922010-04-19 01:13:49 +00004328 if (!BP_NOMCP(bp)) {
4329 u32 nig_timer_max =
4330 SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
4331 if (nig_timer_max != estats->nig_timer_max) {
4332 estats->nig_timer_max = nig_timer_max;
4333 BNX2X_ERR("NIG timer max (%u)\n",
4334 estats->nig_timer_max);
4335 }
Eilon Greensteinde832a52009-02-12 08:36:33 +00004336 }
4337
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004338 return 0;
4339}
4340
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004341static int bnx2x_storm_stats_update(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004342{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004343 struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004344 struct tstorm_per_port_stats *tport =
Eilon Greensteinde832a52009-02-12 08:36:33 +00004345 &stats->tstorm_common.port_statistics;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004346 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
4347 struct bnx2x_eth_stats *estats = &bp->eth_stats;
Eilon Greensteinde832a52009-02-12 08:36:33 +00004348 int i;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004349
Eilon Greenstein6fe49bb2009-08-12 08:23:17 +00004350 memcpy(&(fstats->total_bytes_received_hi),
4351 &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
Eilon Greensteinde832a52009-02-12 08:36:33 +00004352 sizeof(struct host_func_stats) - 2*sizeof(u32));
4353 estats->error_bytes_received_hi = 0;
4354 estats->error_bytes_received_lo = 0;
4355 estats->etherstatsoverrsizepkts_hi = 0;
4356 estats->etherstatsoverrsizepkts_lo = 0;
4357 estats->no_buff_discard_hi = 0;
4358 estats->no_buff_discard_lo = 0;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004359
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00004360 for_each_queue(bp, i) {
Eilon Greensteinde832a52009-02-12 08:36:33 +00004361 struct bnx2x_fastpath *fp = &bp->fp[i];
4362 int cl_id = fp->cl_id;
4363 struct tstorm_per_client_stats *tclient =
4364 &stats->tstorm_common.client_statistics[cl_id];
4365 struct tstorm_per_client_stats *old_tclient = &fp->old_tclient;
4366 struct ustorm_per_client_stats *uclient =
4367 &stats->ustorm_common.client_statistics[cl_id];
4368 struct ustorm_per_client_stats *old_uclient = &fp->old_uclient;
4369 struct xstorm_per_client_stats *xclient =
4370 &stats->xstorm_common.client_statistics[cl_id];
4371 struct xstorm_per_client_stats *old_xclient = &fp->old_xclient;
4372 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
4373 u32 diff;
4374
4375 /* are storm stats valid? */
4376 if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
4377 bp->stats_counter) {
4378 DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
4379 " xstorm counter (%d) != stats_counter (%d)\n",
4380 i, xclient->stats_counter, bp->stats_counter);
4381 return -1;
4382 }
4383 if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
4384 bp->stats_counter) {
4385 DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
4386 " tstorm counter (%d) != stats_counter (%d)\n",
4387 i, tclient->stats_counter, bp->stats_counter);
4388 return -2;
4389 }
4390 if ((u16)(le16_to_cpu(uclient->stats_counter) + 1) !=
4391 bp->stats_counter) {
4392 DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
4393 " ustorm counter (%d) != stats_counter (%d)\n",
4394 i, uclient->stats_counter, bp->stats_counter);
4395 return -4;
4396 }
4397
4398 qstats->total_bytes_received_hi =
Eilon Greensteinca003922009-08-12 22:53:28 -07004399 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004400 qstats->total_bytes_received_lo =
Eilon Greensteinca003922009-08-12 22:53:28 -07004401 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
4402
4403 ADD_64(qstats->total_bytes_received_hi,
4404 le32_to_cpu(tclient->rcv_multicast_bytes.hi),
4405 qstats->total_bytes_received_lo,
4406 le32_to_cpu(tclient->rcv_multicast_bytes.lo));
4407
4408 ADD_64(qstats->total_bytes_received_hi,
4409 le32_to_cpu(tclient->rcv_unicast_bytes.hi),
4410 qstats->total_bytes_received_lo,
4411 le32_to_cpu(tclient->rcv_unicast_bytes.lo));
4412
4413 qstats->valid_bytes_received_hi =
4414 qstats->total_bytes_received_hi;
Eilon Greensteinde832a52009-02-12 08:36:33 +00004415 qstats->valid_bytes_received_lo =
Eilon Greensteinca003922009-08-12 22:53:28 -07004416 qstats->total_bytes_received_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004417
Eilon Greensteinde832a52009-02-12 08:36:33 +00004418 qstats->error_bytes_received_hi =
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004419 le32_to_cpu(tclient->rcv_error_bytes.hi);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004420 qstats->error_bytes_received_lo =
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004421 le32_to_cpu(tclient->rcv_error_bytes.lo);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004422
4423 ADD_64(qstats->total_bytes_received_hi,
4424 qstats->error_bytes_received_hi,
4425 qstats->total_bytes_received_lo,
4426 qstats->error_bytes_received_lo);
4427
4428 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
4429 total_unicast_packets_received);
4430 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
4431 total_multicast_packets_received);
4432 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
4433 total_broadcast_packets_received);
4434 UPDATE_EXTEND_TSTAT(packets_too_big_discard,
4435 etherstatsoverrsizepkts);
4436 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
4437
4438 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
4439 total_unicast_packets_received);
4440 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
4441 total_multicast_packets_received);
4442 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
4443 total_broadcast_packets_received);
4444 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
4445 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
4446 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
4447
4448 qstats->total_bytes_transmitted_hi =
Eilon Greensteinca003922009-08-12 22:53:28 -07004449 le32_to_cpu(xclient->unicast_bytes_sent.hi);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004450 qstats->total_bytes_transmitted_lo =
Eilon Greensteinca003922009-08-12 22:53:28 -07004451 le32_to_cpu(xclient->unicast_bytes_sent.lo);
4452
4453 ADD_64(qstats->total_bytes_transmitted_hi,
4454 le32_to_cpu(xclient->multicast_bytes_sent.hi),
4455 qstats->total_bytes_transmitted_lo,
4456 le32_to_cpu(xclient->multicast_bytes_sent.lo));
4457
4458 ADD_64(qstats->total_bytes_transmitted_hi,
4459 le32_to_cpu(xclient->broadcast_bytes_sent.hi),
4460 qstats->total_bytes_transmitted_lo,
4461 le32_to_cpu(xclient->broadcast_bytes_sent.lo));
Eilon Greensteinde832a52009-02-12 08:36:33 +00004462
4463 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
4464 total_unicast_packets_transmitted);
4465 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
4466 total_multicast_packets_transmitted);
4467 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
4468 total_broadcast_packets_transmitted);
4469
4470 old_tclient->checksum_discard = tclient->checksum_discard;
4471 old_tclient->ttl0_discard = tclient->ttl0_discard;
4472
4473 ADD_64(fstats->total_bytes_received_hi,
4474 qstats->total_bytes_received_hi,
4475 fstats->total_bytes_received_lo,
4476 qstats->total_bytes_received_lo);
4477 ADD_64(fstats->total_bytes_transmitted_hi,
4478 qstats->total_bytes_transmitted_hi,
4479 fstats->total_bytes_transmitted_lo,
4480 qstats->total_bytes_transmitted_lo);
4481 ADD_64(fstats->total_unicast_packets_received_hi,
4482 qstats->total_unicast_packets_received_hi,
4483 fstats->total_unicast_packets_received_lo,
4484 qstats->total_unicast_packets_received_lo);
4485 ADD_64(fstats->total_multicast_packets_received_hi,
4486 qstats->total_multicast_packets_received_hi,
4487 fstats->total_multicast_packets_received_lo,
4488 qstats->total_multicast_packets_received_lo);
4489 ADD_64(fstats->total_broadcast_packets_received_hi,
4490 qstats->total_broadcast_packets_received_hi,
4491 fstats->total_broadcast_packets_received_lo,
4492 qstats->total_broadcast_packets_received_lo);
4493 ADD_64(fstats->total_unicast_packets_transmitted_hi,
4494 qstats->total_unicast_packets_transmitted_hi,
4495 fstats->total_unicast_packets_transmitted_lo,
4496 qstats->total_unicast_packets_transmitted_lo);
4497 ADD_64(fstats->total_multicast_packets_transmitted_hi,
4498 qstats->total_multicast_packets_transmitted_hi,
4499 fstats->total_multicast_packets_transmitted_lo,
4500 qstats->total_multicast_packets_transmitted_lo);
4501 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
4502 qstats->total_broadcast_packets_transmitted_hi,
4503 fstats->total_broadcast_packets_transmitted_lo,
4504 qstats->total_broadcast_packets_transmitted_lo);
4505 ADD_64(fstats->valid_bytes_received_hi,
4506 qstats->valid_bytes_received_hi,
4507 fstats->valid_bytes_received_lo,
4508 qstats->valid_bytes_received_lo);
4509
4510 ADD_64(estats->error_bytes_received_hi,
4511 qstats->error_bytes_received_hi,
4512 estats->error_bytes_received_lo,
4513 qstats->error_bytes_received_lo);
4514 ADD_64(estats->etherstatsoverrsizepkts_hi,
4515 qstats->etherstatsoverrsizepkts_hi,
4516 estats->etherstatsoverrsizepkts_lo,
4517 qstats->etherstatsoverrsizepkts_lo);
4518 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
4519 estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
4520 }
4521
4522 ADD_64(fstats->total_bytes_received_hi,
4523 estats->rx_stat_ifhcinbadoctets_hi,
4524 fstats->total_bytes_received_lo,
4525 estats->rx_stat_ifhcinbadoctets_lo);
4526
4527 memcpy(estats, &(fstats->total_bytes_received_hi),
4528 sizeof(struct host_func_stats) - 2*sizeof(u32));
4529
4530 ADD_64(estats->etherstatsoverrsizepkts_hi,
4531 estats->rx_stat_dot3statsframestoolong_hi,
4532 estats->etherstatsoverrsizepkts_lo,
4533 estats->rx_stat_dot3statsframestoolong_lo);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004534 ADD_64(estats->error_bytes_received_hi,
4535 estats->rx_stat_ifhcinbadoctets_hi,
4536 estats->error_bytes_received_lo,
4537 estats->rx_stat_ifhcinbadoctets_lo);
4538
Eilon Greensteinde832a52009-02-12 08:36:33 +00004539 if (bp->port.pmf) {
4540 estats->mac_filter_discard =
4541 le32_to_cpu(tport->mac_filter_discard);
4542 estats->xxoverflow_discard =
4543 le32_to_cpu(tport->xxoverflow_discard);
4544 estats->brb_truncate_discard =
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004545 le32_to_cpu(tport->brb_truncate_discard);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004546 estats->mac_discard = le32_to_cpu(tport->mac_discard);
4547 }
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004548
4549 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
4550
Eilon Greensteinde832a52009-02-12 08:36:33 +00004551 bp->stats_pending = 0;
4552
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004553 return 0;
4554}
4555
4556static void bnx2x_net_stats_update(struct bnx2x *bp)
4557{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004558 struct bnx2x_eth_stats *estats = &bp->eth_stats;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004559 struct net_device_stats *nstats = &bp->dev->stats;
Eilon Greensteinde832a52009-02-12 08:36:33 +00004560 int i;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004561
4562 nstats->rx_packets =
4563 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
4564 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
4565 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
4566
4567 nstats->tx_packets =
4568 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
4569 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
4570 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
4571
Eilon Greensteinde832a52009-02-12 08:36:33 +00004572 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004573
Eliezer Tamir0e39e642008-02-28 11:54:03 -08004574 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004575
Eilon Greensteinde832a52009-02-12 08:36:33 +00004576 nstats->rx_dropped = estats->mac_discard;
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00004577 for_each_queue(bp, i)
Eilon Greensteinde832a52009-02-12 08:36:33 +00004578 nstats->rx_dropped +=
4579 le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
4580
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004581 nstats->tx_dropped = 0;
4582
4583 nstats->multicast =
Eilon Greensteinde832a52009-02-12 08:36:33 +00004584 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004585
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004586 nstats->collisions =
Eilon Greensteinde832a52009-02-12 08:36:33 +00004587 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004588
4589 nstats->rx_length_errors =
Eilon Greensteinde832a52009-02-12 08:36:33 +00004590 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
4591 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
4592 nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
4593 bnx2x_hilo(&estats->brb_truncate_hi);
4594 nstats->rx_crc_errors =
4595 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
4596 nstats->rx_frame_errors =
4597 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
4598 nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004599 nstats->rx_missed_errors = estats->xxoverflow_discard;
4600
4601 nstats->rx_errors = nstats->rx_length_errors +
4602 nstats->rx_over_errors +
4603 nstats->rx_crc_errors +
4604 nstats->rx_frame_errors +
Eliezer Tamir0e39e642008-02-28 11:54:03 -08004605 nstats->rx_fifo_errors +
4606 nstats->rx_missed_errors;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004607
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004608 nstats->tx_aborted_errors =
Eilon Greensteinde832a52009-02-12 08:36:33 +00004609 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
4610 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
4611 nstats->tx_carrier_errors =
4612 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004613 nstats->tx_fifo_errors = 0;
4614 nstats->tx_heartbeat_errors = 0;
4615 nstats->tx_window_errors = 0;
4616
4617 nstats->tx_errors = nstats->tx_aborted_errors +
Eilon Greensteinde832a52009-02-12 08:36:33 +00004618 nstats->tx_carrier_errors +
4619 bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
4620}
4621
4622static void bnx2x_drv_stats_update(struct bnx2x *bp)
4623{
4624 struct bnx2x_eth_stats *estats = &bp->eth_stats;
4625 int i;
4626
4627 estats->driver_xoff = 0;
4628 estats->rx_err_discard_pkt = 0;
4629 estats->rx_skb_alloc_failed = 0;
4630 estats->hw_csum_err = 0;
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00004631 for_each_queue(bp, i) {
Eilon Greensteinde832a52009-02-12 08:36:33 +00004632 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
4633
4634 estats->driver_xoff += qstats->driver_xoff;
4635 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
4636 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
4637 estats->hw_csum_err += qstats->hw_csum_err;
4638 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004639}
4640
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004641static void bnx2x_stats_update(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004642{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004643 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004644
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004645 if (*stats_comp != DMAE_COMP_VAL)
4646 return;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004647
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004648 if (bp->port.pmf)
Eilon Greensteinde832a52009-02-12 08:36:33 +00004649 bnx2x_hw_stats_update(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004650
Eilon Greensteinde832a52009-02-12 08:36:33 +00004651 if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
4652 BNX2X_ERR("storm stats were not updated for 3 times\n");
4653 bnx2x_panic();
4654 return;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004655 }
4656
Eilon Greensteinde832a52009-02-12 08:36:33 +00004657 bnx2x_net_stats_update(bp);
4658 bnx2x_drv_stats_update(bp);
4659
Joe Perches7995c642010-02-17 15:01:52 +00004660 if (netif_msg_timer(bp)) {
Eilon Greensteinca003922009-08-12 22:53:28 -07004661 struct bnx2x_fastpath *fp0_rx = bp->fp;
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00004662 struct bnx2x_fastpath *fp0_tx = bp->fp;
Eilon Greensteinde832a52009-02-12 08:36:33 +00004663 struct tstorm_per_client_stats *old_tclient =
4664 &bp->fp->old_tclient;
4665 struct bnx2x_eth_q_stats *qstats = &bp->fp->eth_q_stats;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004666 struct bnx2x_eth_stats *estats = &bp->eth_stats;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004667 struct net_device_stats *nstats = &bp->dev->stats;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07004668 int i;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004669
Joe Perches7995c642010-02-17 15:01:52 +00004670 netdev_printk(KERN_DEBUG, bp->dev, "\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004671 printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
4672 " tx pkt (%lx)\n",
Eilon Greensteinca003922009-08-12 22:53:28 -07004673 bnx2x_tx_avail(fp0_tx),
4674 le16_to_cpu(*fp0_tx->tx_cons_sb), nstats->tx_packets);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004675 printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
4676 " rx pkt (%lx)\n",
Eilon Greensteinca003922009-08-12 22:53:28 -07004677 (u16)(le16_to_cpu(*fp0_rx->rx_cons_sb) -
4678 fp0_rx->rx_comp_cons),
4679 le16_to_cpu(*fp0_rx->rx_cons_sb), nstats->rx_packets);
Eilon Greensteinde832a52009-02-12 08:36:33 +00004680 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u "
4681 "brb truncate %u\n",
4682 (netif_queue_stopped(bp->dev) ? "Xoff" : "Xon"),
4683 qstats->driver_xoff,
4684 estats->brb_drop_lo, estats->brb_truncate_lo);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004685 printk(KERN_DEBUG "tstats: checksum_discard %u "
Eilon Greensteinde832a52009-02-12 08:36:33 +00004686 "packets_too_big_discard %lu no_buff_discard %lu "
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004687 "mac_discard %u mac_filter_discard %u "
4688 "xxovrflow_discard %u brb_truncate_discard %u "
4689 "ttl0_discard %u\n",
Eilon Greenstein4781bfa2009-02-12 08:38:17 +00004690 le32_to_cpu(old_tclient->checksum_discard),
Eilon Greensteinde832a52009-02-12 08:36:33 +00004691 bnx2x_hilo(&qstats->etherstatsoverrsizepkts_hi),
4692 bnx2x_hilo(&qstats->no_buff_discard_hi),
4693 estats->mac_discard, estats->mac_filter_discard,
4694 estats->xxoverflow_discard, estats->brb_truncate_discard,
Eilon Greenstein4781bfa2009-02-12 08:38:17 +00004695 le32_to_cpu(old_tclient->ttl0_discard));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004696
4697 for_each_queue(bp, i) {
4698 printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
4699 bnx2x_fp(bp, i, tx_pkt),
4700 bnx2x_fp(bp, i, rx_pkt),
4701 bnx2x_fp(bp, i, rx_calls));
4702 }
4703 }
4704
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004705 bnx2x_hw_stats_post(bp);
4706 bnx2x_storm_stats_post(bp);
4707}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004708
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004709static void bnx2x_port_stats_stop(struct bnx2x *bp)
4710{
4711 struct dmae_command *dmae;
4712 u32 opcode;
4713 int loader_idx = PMF_DMAE_C(bp);
4714 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004715
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004716 bp->executer_idx = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004717
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004718 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4719 DMAE_CMD_C_ENABLE |
4720 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004721#ifdef __BIG_ENDIAN
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004722 DMAE_CMD_ENDIANITY_B_DW_SWAP |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004723#else
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004724 DMAE_CMD_ENDIANITY_DW_SWAP |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004725#endif
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004726 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4727 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
4728
4729 if (bp->port.port_stx) {
4730
4731 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4732 if (bp->func_stx)
4733 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
4734 else
4735 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
4736 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
4737 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
4738 dmae->dst_addr_lo = bp->port.port_stx >> 2;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004739 dmae->dst_addr_hi = 0;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004740 dmae->len = sizeof(struct host_port_stats) >> 2;
4741 if (bp->func_stx) {
4742 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4743 dmae->comp_addr_hi = 0;
4744 dmae->comp_val = 1;
4745 } else {
4746 dmae->comp_addr_lo =
4747 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4748 dmae->comp_addr_hi =
4749 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4750 dmae->comp_val = DMAE_COMP_VAL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004751
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004752 *stats_comp = 0;
4753 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004754 }
4755
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004756 if (bp->func_stx) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004757
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004758 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4759 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
4760 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
4761 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
4762 dmae->dst_addr_lo = bp->func_stx >> 2;
4763 dmae->dst_addr_hi = 0;
4764 dmae->len = sizeof(struct host_func_stats) >> 2;
4765 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4766 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4767 dmae->comp_val = DMAE_COMP_VAL;
4768
4769 *stats_comp = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004770 }
4771}
4772
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004773static void bnx2x_stats_stop(struct bnx2x *bp)
4774{
4775 int update = 0;
4776
4777 bnx2x_stats_comp(bp);
4778
4779 if (bp->port.pmf)
4780 update = (bnx2x_hw_stats_update(bp) == 0);
4781
4782 update |= (bnx2x_storm_stats_update(bp) == 0);
4783
4784 if (update) {
4785 bnx2x_net_stats_update(bp);
4786
4787 if (bp->port.pmf)
4788 bnx2x_port_stats_stop(bp);
4789
4790 bnx2x_hw_stats_post(bp);
4791 bnx2x_stats_comp(bp);
4792 }
4793}
4794
4795static void bnx2x_stats_do_nothing(struct bnx2x *bp)
4796{
4797}
4798
4799static const struct {
4800 void (*action)(struct bnx2x *bp);
4801 enum bnx2x_stats_state next_state;
4802} bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
4803/* state event */
4804{
4805/* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
4806/* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
4807/* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
4808/* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
4809},
4810{
4811/* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
4812/* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
4813/* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
4814/* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
4815}
4816};
4817
4818static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
4819{
4820 enum bnx2x_stats_state state = bp->stats_state;
4821
4822 bnx2x_stats_stm[state][event].action(bp);
4823 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
4824
Eilon Greenstein89246652009-08-12 08:23:56 +00004825 /* Make sure the state has been "changed" */
4826 smp_wmb();
4827
Joe Perches7995c642010-02-17 15:01:52 +00004828 if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07004829 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
4830 state, event, bp->stats_state);
4831}
4832
Eilon Greenstein6fe49bb2009-08-12 08:23:17 +00004833static void bnx2x_port_stats_base_init(struct bnx2x *bp)
4834{
4835 struct dmae_command *dmae;
4836 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
4837
4838 /* sanity */
4839 if (!bp->port.pmf || !bp->port.port_stx) {
4840 BNX2X_ERR("BUG!\n");
4841 return;
4842 }
4843
4844 bp->executer_idx = 0;
4845
4846 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
4847 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4848 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4849 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4850#ifdef __BIG_ENDIAN
4851 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4852#else
4853 DMAE_CMD_ENDIANITY_DW_SWAP |
4854#endif
4855 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4856 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
4857 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
4858 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
4859 dmae->dst_addr_lo = bp->port.port_stx >> 2;
4860 dmae->dst_addr_hi = 0;
4861 dmae->len = sizeof(struct host_port_stats) >> 2;
4862 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4863 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4864 dmae->comp_val = DMAE_COMP_VAL;
4865
4866 *stats_comp = 0;
4867 bnx2x_hw_stats_post(bp);
4868 bnx2x_stats_comp(bp);
4869}
4870
4871static void bnx2x_func_stats_base_init(struct bnx2x *bp)
4872{
4873 int vn, vn_max = IS_E1HMF(bp) ? E1HVN_MAX : E1VN_MAX;
4874 int port = BP_PORT(bp);
4875 int func;
4876 u32 func_stx;
4877
4878 /* sanity */
4879 if (!bp->port.pmf || !bp->func_stx) {
4880 BNX2X_ERR("BUG!\n");
4881 return;
4882 }
4883
4884 /* save our func_stx */
4885 func_stx = bp->func_stx;
4886
4887 for (vn = VN_0; vn < vn_max; vn++) {
4888 func = 2*vn + port;
4889
4890 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
4891 bnx2x_func_stats_init(bp);
4892 bnx2x_hw_stats_post(bp);
4893 bnx2x_stats_comp(bp);
4894 }
4895
4896 /* restore our func_stx */
4897 bp->func_stx = func_stx;
4898}
4899
4900static void bnx2x_func_stats_base_update(struct bnx2x *bp)
4901{
4902 struct dmae_command *dmae = &bp->stats_dmae;
4903 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
4904
4905 /* sanity */
4906 if (!bp->func_stx) {
4907 BNX2X_ERR("BUG!\n");
4908 return;
4909 }
4910
4911 bp->executer_idx = 0;
4912 memset(dmae, 0, sizeof(struct dmae_command));
4913
4914 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
4915 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4916 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4917#ifdef __BIG_ENDIAN
4918 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4919#else
4920 DMAE_CMD_ENDIANITY_DW_SWAP |
4921#endif
4922 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4923 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
4924 dmae->src_addr_lo = bp->func_stx >> 2;
4925 dmae->src_addr_hi = 0;
4926 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
4927 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
4928 dmae->len = sizeof(struct host_func_stats) >> 2;
4929 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
4930 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
4931 dmae->comp_val = DMAE_COMP_VAL;
4932
4933 *stats_comp = 0;
4934 bnx2x_hw_stats_post(bp);
4935 bnx2x_stats_comp(bp);
4936}
4937
4938static void bnx2x_stats_init(struct bnx2x *bp)
4939{
4940 int port = BP_PORT(bp);
4941 int func = BP_FUNC(bp);
4942 int i;
4943
4944 bp->stats_pending = 0;
4945 bp->executer_idx = 0;
4946 bp->stats_counter = 0;
4947
4948 /* port and func stats for management */
4949 if (!BP_NOMCP(bp)) {
4950 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
4951 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
4952
4953 } else {
4954 bp->port.port_stx = 0;
4955 bp->func_stx = 0;
4956 }
4957 DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
4958 bp->port.port_stx, bp->func_stx);
4959
4960 /* port stats */
4961 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
4962 bp->port.old_nig_stats.brb_discard =
4963 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
4964 bp->port.old_nig_stats.brb_truncate =
4965 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
4966 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
4967 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
4968 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
4969 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
4970
4971 /* function stats */
4972 for_each_queue(bp, i) {
4973 struct bnx2x_fastpath *fp = &bp->fp[i];
4974
4975 memset(&fp->old_tclient, 0,
4976 sizeof(struct tstorm_per_client_stats));
4977 memset(&fp->old_uclient, 0,
4978 sizeof(struct ustorm_per_client_stats));
4979 memset(&fp->old_xclient, 0,
4980 sizeof(struct xstorm_per_client_stats));
4981 memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
4982 }
4983
4984 memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
4985 memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
4986
4987 bp->stats_state = STATS_STATE_DISABLED;
4988
4989 if (bp->port.pmf) {
4990 if (bp->port.port_stx)
4991 bnx2x_port_stats_base_init(bp);
4992
4993 if (bp->func_stx)
4994 bnx2x_func_stats_base_init(bp);
4995
4996 } else if (bp->func_stx)
4997 bnx2x_func_stats_base_update(bp);
4998}
4999
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005000static void bnx2x_timer(unsigned long data)
5001{
5002 struct bnx2x *bp = (struct bnx2x *) data;
5003
5004 if (!netif_running(bp->dev))
5005 return;
5006
5007 if (atomic_read(&bp->intr_sem) != 0)
Eliezer Tamirf1410642008-02-28 11:51:50 -08005008 goto timer_restart;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005009
5010 if (poll) {
5011 struct bnx2x_fastpath *fp = &bp->fp[0];
5012 int rc;
5013
Eilon Greenstein7961f792009-03-02 07:59:31 +00005014 bnx2x_tx_int(fp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005015 rc = bnx2x_rx_int(fp, 1000);
5016 }
5017
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005018 if (!BP_NOMCP(bp)) {
5019 int func = BP_FUNC(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005020 u32 drv_pulse;
5021 u32 mcp_pulse;
5022
5023 ++bp->fw_drv_pulse_wr_seq;
5024 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5025 /* TBD - add SYSTEM_TIME */
5026 drv_pulse = bp->fw_drv_pulse_wr_seq;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005027 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005028
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005029 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005030 MCP_PULSE_SEQ_MASK);
5031 /* The delta between driver pulse and mcp response
5032 * should be 1 (before mcp response) or 0 (after mcp response)
5033 */
5034 if ((drv_pulse != mcp_pulse) &&
5035 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5036 /* someone lost a heartbeat... */
5037 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5038 drv_pulse, mcp_pulse);
5039 }
5040 }
5041
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07005042 if (bp->state == BNX2X_STATE_OPEN)
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07005043 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005044
Eliezer Tamirf1410642008-02-28 11:51:50 -08005045timer_restart:
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005046 mod_timer(&bp->timer, jiffies + bp->current_interval);
5047}
5048
5049/* end of Statistics */
5050
5051/* nic init */
5052
5053/*
5054 * nic init service functions
5055 */
5056
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005057static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005058{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005059 int port = BP_PORT(bp);
5060
Eilon Greensteinca003922009-08-12 22:53:28 -07005061 /* "CSTORM" */
5062 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
5063 CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
5064 CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
5065 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
5066 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
5067 CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005068}
5069
Eilon Greenstein5c862842008-08-13 15:51:48 -07005070static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
5071 dma_addr_t mapping, int sb_id)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005072{
5073 int port = BP_PORT(bp);
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07005074 int func = BP_FUNC(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005075 int index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005076 u64 section;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005077
5078 /* USTORM */
5079 section = ((u64)mapping) + offsetof(struct host_status_block,
5080 u_status_block);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005081 sb->u_status_block.status_block_id = sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005082
Eilon Greensteinca003922009-08-12 22:53:28 -07005083 REG_WR(bp, BAR_CSTRORM_INTMEM +
5084 CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section));
5085 REG_WR(bp, BAR_CSTRORM_INTMEM +
5086 ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005087 U64_HI(section));
Eilon Greensteinca003922009-08-12 22:53:28 -07005088 REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_USB_FUNC_OFF +
5089 CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005090
5091 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
Eilon Greensteinca003922009-08-12 22:53:28 -07005092 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5093 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005094
5095 /* CSTORM */
5096 section = ((u64)mapping) + offsetof(struct host_status_block,
5097 c_status_block);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005098 sb->c_status_block.status_block_id = sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005099
5100 REG_WR(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005101 CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005102 REG_WR(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005103 ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005104 U64_HI(section));
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005105 REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
Eilon Greensteinca003922009-08-12 22:53:28 -07005106 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005107
5108 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
5109 REG_WR16(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005110 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005111
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005112 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
5113}
5114
5115static void bnx2x_zero_def_sb(struct bnx2x *bp)
5116{
5117 int func = BP_FUNC(bp);
5118
Eilon Greensteinca003922009-08-12 22:53:28 -07005119 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005120 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
5121 sizeof(struct tstorm_def_status_block)/4);
Eilon Greensteinca003922009-08-12 22:53:28 -07005122 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
5123 CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
5124 sizeof(struct cstorm_def_status_block_u)/4);
5125 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
5126 CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
5127 sizeof(struct cstorm_def_status_block_c)/4);
5128 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY +
Eilon Greenstein490c3c92009-03-02 07:59:52 +00005129 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
5130 sizeof(struct xstorm_def_status_block)/4);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005131}
5132
5133static void bnx2x_init_def_sb(struct bnx2x *bp,
5134 struct host_def_status_block *def_sb,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005135 dma_addr_t mapping, int sb_id)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005136{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005137 int port = BP_PORT(bp);
5138 int func = BP_FUNC(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005139 int index, val, reg_offset;
5140 u64 section;
5141
5142 /* ATTN */
5143 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5144 atten_status_block);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005145 def_sb->atten_status_block.status_block_id = sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005146
Eliezer Tamir49d66772008-02-28 11:53:13 -08005147 bp->attn_state = 0;
5148
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005149 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5150 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5151
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005152 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005153 bp->attn_group[index].sig[0] = REG_RD(bp,
5154 reg_offset + 0x10*index);
5155 bp->attn_group[index].sig[1] = REG_RD(bp,
5156 reg_offset + 0x4 + 0x10*index);
5157 bp->attn_group[index].sig[2] = REG_RD(bp,
5158 reg_offset + 0x8 + 0x10*index);
5159 bp->attn_group[index].sig[3] = REG_RD(bp,
5160 reg_offset + 0xc + 0x10*index);
5161 }
5162
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005163 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5164 HC_REG_ATTN_MSG0_ADDR_L);
5165
5166 REG_WR(bp, reg_offset, U64_LO(section));
5167 REG_WR(bp, reg_offset + 4, U64_HI(section));
5168
5169 reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
5170
5171 val = REG_RD(bp, reg_offset);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005172 val |= sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005173 REG_WR(bp, reg_offset, val);
5174
5175 /* USTORM */
5176 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5177 u_def_status_block);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005178 def_sb->u_def_status_block.status_block_id = sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005179
Eilon Greensteinca003922009-08-12 22:53:28 -07005180 REG_WR(bp, BAR_CSTRORM_INTMEM +
5181 CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section));
5182 REG_WR(bp, BAR_CSTRORM_INTMEM +
5183 ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005184 U64_HI(section));
Eilon Greensteinca003922009-08-12 22:53:28 -07005185 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_USB_FUNC_OFF +
5186 CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005187
5188 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
Eilon Greensteinca003922009-08-12 22:53:28 -07005189 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5190 CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005191
5192 /* CSTORM */
5193 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5194 c_def_status_block);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005195 def_sb->c_def_status_block.status_block_id = sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005196
5197 REG_WR(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005198 CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005199 REG_WR(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005200 ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005201 U64_HI(section));
Eilon Greenstein5c862842008-08-13 15:51:48 -07005202 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
Eilon Greensteinca003922009-08-12 22:53:28 -07005203 CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005204
5205 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
5206 REG_WR16(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005207 CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005208
5209 /* TSTORM */
5210 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5211 t_def_status_block);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005212 def_sb->t_def_status_block.status_block_id = sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005213
5214 REG_WR(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005215 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005216 REG_WR(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005217 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005218 U64_HI(section));
Eilon Greenstein5c862842008-08-13 15:51:48 -07005219 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005220 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005221
5222 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
5223 REG_WR16(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005224 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005225
5226 /* XSTORM */
5227 section = ((u64)mapping) + offsetof(struct host_def_status_block,
5228 x_def_status_block);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005229 def_sb->x_def_status_block.status_block_id = sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005230
5231 REG_WR(bp, BAR_XSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005232 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005233 REG_WR(bp, BAR_XSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005234 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005235 U64_HI(section));
Eilon Greenstein5c862842008-08-13 15:51:48 -07005236 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005237 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005238
5239 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
5240 REG_WR16(bp, BAR_XSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005241 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005242
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07005243 bp->stats_pending = 0;
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005244 bp->set_mac_pending = 0;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07005245
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005246 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005247}
5248
5249static void bnx2x_update_coalesce(struct bnx2x *bp)
5250{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005251 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005252 int i;
5253
5254 for_each_queue(bp, i) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005255 int sb_id = bp->fp[i].sb_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005256
5257 /* HC_INDEX_U_ETH_RX_CQ_CONS */
Eilon Greensteinca003922009-08-12 22:53:28 -07005258 REG_WR8(bp, BAR_CSTRORM_INTMEM +
5259 CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
5260 U_SB_ETH_RX_CQ_INDEX),
Eilon Greenstein7d323bf2009-11-09 06:09:35 +00005261 bp->rx_ticks/(4 * BNX2X_BTR));
Eilon Greensteinca003922009-08-12 22:53:28 -07005262 REG_WR16(bp, BAR_CSTRORM_INTMEM +
5263 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
5264 U_SB_ETH_RX_CQ_INDEX),
Eilon Greenstein7d323bf2009-11-09 06:09:35 +00005265 (bp->rx_ticks/(4 * BNX2X_BTR)) ? 0 : 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005266
5267 /* HC_INDEX_C_ETH_TX_CQ_CONS */
5268 REG_WR8(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005269 CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
5270 C_SB_ETH_TX_CQ_INDEX),
Eilon Greenstein7d323bf2009-11-09 06:09:35 +00005271 bp->tx_ticks/(4 * BNX2X_BTR));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005272 REG_WR16(bp, BAR_CSTRORM_INTMEM +
Eilon Greensteinca003922009-08-12 22:53:28 -07005273 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
5274 C_SB_ETH_TX_CQ_INDEX),
Eilon Greenstein7d323bf2009-11-09 06:09:35 +00005275 (bp->tx_ticks/(4 * BNX2X_BTR)) ? 0 : 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005276 }
5277}
5278
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005279static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
5280 struct bnx2x_fastpath *fp, int last)
5281{
5282 int i;
5283
5284 for (i = 0; i < last; i++) {
5285 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
5286 struct sk_buff *skb = rx_buf->skb;
5287
5288 if (skb == NULL) {
5289 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
5290 continue;
5291 }
5292
5293 if (fp->tpa_state[i] == BNX2X_TPA_START)
FUJITA Tomonori1a983142010-04-04 01:51:03 +00005294 dma_unmap_single(&bp->pdev->dev,
5295 dma_unmap_addr(rx_buf, mapping),
5296 bp->rx_buf_size, DMA_FROM_DEVICE);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005297
5298 dev_kfree_skb(skb);
5299 rx_buf->skb = NULL;
5300 }
5301}
5302
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005303static void bnx2x_init_rx_rings(struct bnx2x *bp)
5304{
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005305 int func = BP_FUNC(bp);
Eilon Greenstein32626232008-08-13 15:51:07 -07005306 int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
5307 ETH_MAX_AGGREGATION_QUEUES_E1H;
5308 u16 ring_prod, cqe_ring_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005309 int i, j;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005310
Eilon Greenstein87942b42009-02-12 08:36:49 +00005311 bp->rx_buf_size = bp->dev->mtu + ETH_OVREHEAD + BNX2X_RX_ALIGN;
Eilon Greenstein0f008462009-02-12 08:36:18 +00005312 DP(NETIF_MSG_IFUP,
5313 "mtu %d rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005314
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005315 if (bp->flags & TPA_ENABLE_FLAG) {
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005316
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005317 for_each_queue(bp, j) {
Eilon Greenstein32626232008-08-13 15:51:07 -07005318 struct bnx2x_fastpath *fp = &bp->fp[j];
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005319
Eilon Greenstein32626232008-08-13 15:51:07 -07005320 for (i = 0; i < max_agg_queues; i++) {
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005321 fp->tpa_pool[i].skb =
5322 netdev_alloc_skb(bp->dev, bp->rx_buf_size);
5323 if (!fp->tpa_pool[i].skb) {
5324 BNX2X_ERR("Failed to allocate TPA "
5325 "skb pool for queue[%d] - "
5326 "disabling TPA on this "
5327 "queue!\n", j);
5328 bnx2x_free_tpa_pool(bp, fp, i);
5329 fp->disable_tpa = 1;
5330 break;
5331 }
FUJITA Tomonori1a983142010-04-04 01:51:03 +00005332 dma_unmap_addr_set((struct sw_rx_bd *)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005333 &bp->fp->tpa_pool[i],
5334 mapping, 0);
5335 fp->tpa_state[i] = BNX2X_TPA_STOP;
5336 }
5337 }
5338 }
5339
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005340 for_each_queue(bp, j) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005341 struct bnx2x_fastpath *fp = &bp->fp[j];
5342
5343 fp->rx_bd_cons = 0;
5344 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005345 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005346
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005347 /* "next page" elements initialization */
5348 /* SGE ring */
5349 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
5350 struct eth_rx_sge *sge;
5351
5352 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
5353 sge->addr_hi =
5354 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
5355 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
5356 sge->addr_lo =
5357 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
5358 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
5359 }
5360
5361 bnx2x_init_sge_ring_bit_mask(fp);
5362
5363 /* RX BD ring */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005364 for (i = 1; i <= NUM_RX_RINGS; i++) {
5365 struct eth_rx_bd *rx_bd;
5366
5367 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
5368 rx_bd->addr_hi =
5369 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005370 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005371 rx_bd->addr_lo =
5372 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005373 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005374 }
5375
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005376 /* CQ ring */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005377 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
5378 struct eth_rx_cqe_next_page *nextpg;
5379
5380 nextpg = (struct eth_rx_cqe_next_page *)
5381 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
5382 nextpg->addr_hi =
5383 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005384 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005385 nextpg->addr_lo =
5386 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005387 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005388 }
5389
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005390 /* Allocate SGEs and initialize the ring elements */
5391 for (i = 0, ring_prod = 0;
5392 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005393
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005394 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
5395 BNX2X_ERR("was only able to allocate "
5396 "%d rx sges\n", i);
5397 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
5398 /* Cleanup already allocated elements */
5399 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
Eilon Greenstein32626232008-08-13 15:51:07 -07005400 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005401 fp->disable_tpa = 1;
5402 ring_prod = 0;
5403 break;
5404 }
5405 ring_prod = NEXT_SGE_IDX(ring_prod);
5406 }
5407 fp->rx_sge_prod = ring_prod;
5408
5409 /* Allocate BDs and initialize BD ring */
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005410 fp->rx_comp_cons = 0;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005411 cqe_ring_prod = ring_prod = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005412 for (i = 0; i < bp->rx_ring_size; i++) {
5413 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
5414 BNX2X_ERR("was only able to allocate "
Eilon Greensteinde832a52009-02-12 08:36:33 +00005415 "%d rx skbs on queue[%d]\n", i, j);
5416 fp->eth_q_stats.rx_skb_alloc_failed++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005417 break;
5418 }
5419 ring_prod = NEXT_RX_IDX(ring_prod);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005420 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
Ilpo Järvinen53e5e962008-07-25 21:40:45 -07005421 WARN_ON(ring_prod <= i);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005422 }
5423
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005424 fp->rx_bd_prod = ring_prod;
5425 /* must not have more available CQEs than BDs */
5426 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
5427 cqe_ring_prod);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005428 fp->rx_pkt = fp->rx_calls = 0;
5429
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005430 /* Warning!
5431 * this will generate an interrupt (to the TSTORM)
5432 * must only be done after chip is initialized
5433 */
5434 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
5435 fp->rx_sge_prod);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005436 if (j != 0)
5437 continue;
5438
5439 REG_WR(bp, BAR_USTRORM_INTMEM +
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005440 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005441 U64_LO(fp->rx_comp_mapping));
5442 REG_WR(bp, BAR_USTRORM_INTMEM +
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005443 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005444 U64_HI(fp->rx_comp_mapping));
5445 }
5446}
5447
5448static void bnx2x_init_tx_ring(struct bnx2x *bp)
5449{
5450 int i, j;
5451
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005452 for_each_queue(bp, j) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005453 struct bnx2x_fastpath *fp = &bp->fp[j];
5454
5455 for (i = 1; i <= NUM_TX_RINGS; i++) {
Eilon Greensteinca003922009-08-12 22:53:28 -07005456 struct eth_tx_next_bd *tx_next_bd =
5457 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005458
Eilon Greensteinca003922009-08-12 22:53:28 -07005459 tx_next_bd->addr_hi =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005460 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005461 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
Eilon Greensteinca003922009-08-12 22:53:28 -07005462 tx_next_bd->addr_lo =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005463 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005464 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005465 }
5466
Eilon Greensteinca003922009-08-12 22:53:28 -07005467 fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE;
5468 fp->tx_db.data.zero_fill1 = 0;
5469 fp->tx_db.data.prod = 0;
5470
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005471 fp->tx_pkt_prod = 0;
5472 fp->tx_pkt_cons = 0;
5473 fp->tx_bd_prod = 0;
5474 fp->tx_bd_cons = 0;
5475 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
5476 fp->tx_pkt = 0;
5477 }
5478}
5479
5480static void bnx2x_init_sp_ring(struct bnx2x *bp)
5481{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005482 int func = BP_FUNC(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005483
5484 spin_lock_init(&bp->spq_lock);
5485
5486 bp->spq_left = MAX_SPQ_PENDING;
5487 bp->spq_prod_idx = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005488 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5489 bp->spq_prod_bd = bp->spq;
5490 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5491
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005492 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005493 U64_LO(bp->spq_mapping));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005494 REG_WR(bp,
5495 XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005496 U64_HI(bp->spq_mapping));
5497
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005498 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005499 bp->spq_prod_idx);
5500}
5501
5502static void bnx2x_init_context(struct bnx2x *bp)
5503{
5504 int i;
5505
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005506 /* Rx */
5507 for_each_queue(bp, i) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005508 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
5509 struct bnx2x_fastpath *fp = &bp->fp[i];
Eilon Greensteinde832a52009-02-12 08:36:33 +00005510 u8 cl_id = fp->cl_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005511
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005512 context->ustorm_st_context.common.sb_index_numbers =
5513 BNX2X_RX_SB_INDEX_NUM;
Eilon Greenstein0626b892009-02-12 08:38:14 +00005514 context->ustorm_st_context.common.clientId = cl_id;
Eilon Greensteinca003922009-08-12 22:53:28 -07005515 context->ustorm_st_context.common.status_block_id = fp->sb_id;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005516 context->ustorm_st_context.common.flags =
Eilon Greensteinde832a52009-02-12 08:36:33 +00005517 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
5518 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
5519 context->ustorm_st_context.common.statistics_counter_id =
5520 cl_id;
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005521 context->ustorm_st_context.common.mc_alignment_log_size =
Eilon Greenstein0f008462009-02-12 08:36:18 +00005522 BNX2X_RX_ALIGN_SHIFT;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005523 context->ustorm_st_context.common.bd_buff_size =
Eilon Greenstein437cf2f2008-09-03 14:38:00 -07005524 bp->rx_buf_size;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005525 context->ustorm_st_context.common.bd_page_base_hi =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005526 U64_HI(fp->rx_desc_mapping);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005527 context->ustorm_st_context.common.bd_page_base_lo =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005528 U64_LO(fp->rx_desc_mapping);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005529 if (!fp->disable_tpa) {
5530 context->ustorm_st_context.common.flags |=
Eilon Greensteinca003922009-08-12 22:53:28 -07005531 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005532 context->ustorm_st_context.common.sge_buff_size =
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005533 (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,
5534 (u32)0xffff);
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005535 context->ustorm_st_context.common.sge_page_base_hi =
5536 U64_HI(fp->rx_sge_mapping);
5537 context->ustorm_st_context.common.sge_page_base_lo =
5538 U64_LO(fp->rx_sge_mapping);
Eilon Greensteinca003922009-08-12 22:53:28 -07005539
5540 context->ustorm_st_context.common.max_sges_for_packet =
5541 SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
5542 context->ustorm_st_context.common.max_sges_for_packet =
5543 ((context->ustorm_st_context.common.
5544 max_sges_for_packet + PAGES_PER_SGE - 1) &
5545 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005546 }
5547
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005548 context->ustorm_ag_context.cdu_usage =
5549 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
5550 CDU_REGION_NUMBER_UCM_AG,
5551 ETH_CONNECTION_TYPE);
5552
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005553 context->xstorm_ag_context.cdu_reserved =
5554 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
5555 CDU_REGION_NUMBER_XCM_AG,
5556 ETH_CONNECTION_TYPE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005557 }
Eilon Greensteinca003922009-08-12 22:53:28 -07005558
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005559 /* Tx */
5560 for_each_queue(bp, i) {
Eilon Greensteinca003922009-08-12 22:53:28 -07005561 struct bnx2x_fastpath *fp = &bp->fp[i];
5562 struct eth_context *context =
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005563 bnx2x_sp(bp, context[i].eth);
Eilon Greensteinca003922009-08-12 22:53:28 -07005564
5565 context->cstorm_st_context.sb_index_number =
5566 C_SB_ETH_TX_CQ_INDEX;
5567 context->cstorm_st_context.status_block_id = fp->sb_id;
5568
5569 context->xstorm_st_context.tx_bd_page_base_hi =
5570 U64_HI(fp->tx_desc_mapping);
5571 context->xstorm_st_context.tx_bd_page_base_lo =
5572 U64_LO(fp->tx_desc_mapping);
5573 context->xstorm_st_context.statistics_data = (fp->cl_id |
5574 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
5575 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005576}
5577
5578static void bnx2x_init_ind_table(struct bnx2x *bp)
5579{
Eilon Greenstein26c8fa42009-01-14 21:29:55 -08005580 int func = BP_FUNC(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005581 int i;
5582
Eilon Greenstein555f6c72009-02-12 08:36:11 +00005583 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005584 return;
5585
Eilon Greenstein555f6c72009-02-12 08:36:11 +00005586 DP(NETIF_MSG_IFUP,
5587 "Initializing indirection table multi_mode %d\n", bp->multi_mode);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005588 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005589 REG_WR8(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein26c8fa42009-01-14 21:29:55 -08005590 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005591 bp->fp->cl_id + (i % bp->num_queues));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005592}
5593
Eliezer Tamir49d66772008-02-28 11:53:13 -08005594static void bnx2x_set_client_config(struct bnx2x *bp)
5595{
Eliezer Tamir49d66772008-02-28 11:53:13 -08005596 struct tstorm_eth_client_config tstorm_client = {0};
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005597 int port = BP_PORT(bp);
5598 int i;
Eliezer Tamir49d66772008-02-28 11:53:13 -08005599
Eilon Greensteine7799c52009-01-14 21:30:27 -08005600 tstorm_client.mtu = bp->dev->mtu;
Eliezer Tamir49d66772008-02-28 11:53:13 -08005601 tstorm_client.config_flags =
Eilon Greensteinde832a52009-02-12 08:36:33 +00005602 (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
5603 TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
Eliezer Tamir49d66772008-02-28 11:53:13 -08005604#ifdef BCM_VLAN
Eilon Greenstein0c6671b2009-01-14 21:26:51 -08005605 if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
Eliezer Tamir49d66772008-02-28 11:53:13 -08005606 tstorm_client.config_flags |=
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005607 TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
Eliezer Tamir49d66772008-02-28 11:53:13 -08005608 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
5609 }
5610#endif
Eliezer Tamir49d66772008-02-28 11:53:13 -08005611
5612 for_each_queue(bp, i) {
Eilon Greensteinde832a52009-02-12 08:36:33 +00005613 tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
5614
Eliezer Tamir49d66772008-02-28 11:53:13 -08005615 REG_WR(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005616 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
Eliezer Tamir49d66772008-02-28 11:53:13 -08005617 ((u32 *)&tstorm_client)[0]);
5618 REG_WR(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005619 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
Eliezer Tamir49d66772008-02-28 11:53:13 -08005620 ((u32 *)&tstorm_client)[1]);
5621 }
5622
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005623 DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
5624 ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
Eliezer Tamir49d66772008-02-28 11:53:13 -08005625}
5626
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005627static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5628{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005629 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005630 int mode = bp->rx_mode;
Michael Chan37b091b2009-10-10 13:46:55 +00005631 int mask = bp->rx_mode_cl_mask;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005632 int func = BP_FUNC(bp);
Eilon Greenstein581ce432009-07-29 00:20:04 +00005633 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005634 int i;
Eilon Greenstein581ce432009-07-29 00:20:04 +00005635 /* All but management unicast packets should pass to the host as well */
5636 u32 llh_mask =
5637 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
5638 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
5639 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
5640 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005641
Eilon Greenstein3196a882008-08-13 15:58:49 -07005642 DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005643
5644 switch (mode) {
5645 case BNX2X_RX_MODE_NONE: /* no Rx */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005646 tstorm_mac_filter.ucast_drop_all = mask;
5647 tstorm_mac_filter.mcast_drop_all = mask;
5648 tstorm_mac_filter.bcast_drop_all = mask;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005649 break;
Eilon Greenstein356e2382009-02-12 08:38:32 +00005650
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005651 case BNX2X_RX_MODE_NORMAL:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005652 tstorm_mac_filter.bcast_accept_all = mask;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005653 break;
Eilon Greenstein356e2382009-02-12 08:38:32 +00005654
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005655 case BNX2X_RX_MODE_ALLMULTI:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005656 tstorm_mac_filter.mcast_accept_all = mask;
5657 tstorm_mac_filter.bcast_accept_all = mask;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005658 break;
Eilon Greenstein356e2382009-02-12 08:38:32 +00005659
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005660 case BNX2X_RX_MODE_PROMISC:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005661 tstorm_mac_filter.ucast_accept_all = mask;
5662 tstorm_mac_filter.mcast_accept_all = mask;
5663 tstorm_mac_filter.bcast_accept_all = mask;
Eilon Greenstein581ce432009-07-29 00:20:04 +00005664 /* pass management unicast packets as well */
5665 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005666 break;
Eilon Greenstein356e2382009-02-12 08:38:32 +00005667
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005668 default:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005669 BNX2X_ERR("BAD rx mode (%d)\n", mode);
5670 break;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005671 }
5672
Eilon Greenstein581ce432009-07-29 00:20:04 +00005673 REG_WR(bp,
5674 (port ? NIG_REG_LLH1_BRB1_DRV_MASK : NIG_REG_LLH0_BRB1_DRV_MASK),
5675 llh_mask);
5676
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005677 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
5678 REG_WR(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005679 TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005680 ((u32 *)&tstorm_mac_filter)[i]);
5681
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005682/* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005683 ((u32 *)&tstorm_mac_filter)[i]); */
5684 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005685
Eliezer Tamir49d66772008-02-28 11:53:13 -08005686 if (mode != BNX2X_RX_MODE_NONE)
5687 bnx2x_set_client_config(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005688}
5689
Eilon Greenstein471de712008-08-13 15:49:35 -07005690static void bnx2x_init_internal_common(struct bnx2x *bp)
5691{
5692 int i;
5693
5694 /* Zero this manually as its initialization is
5695 currently missing in the initTool */
5696 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5697 REG_WR(bp, BAR_USTRORM_INTMEM +
5698 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5699}
5700
5701static void bnx2x_init_internal_port(struct bnx2x *bp)
5702{
5703 int port = BP_PORT(bp);
5704
Eilon Greensteinca003922009-08-12 22:53:28 -07005705 REG_WR(bp,
5706 BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BNX2X_BTR);
5707 REG_WR(bp,
5708 BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BNX2X_BTR);
Eilon Greenstein471de712008-08-13 15:49:35 -07005709 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
5710 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
5711}
5712
5713static void bnx2x_init_internal_func(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005714{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005715 struct tstorm_eth_function_common_config tstorm_config = {0};
5716 struct stats_indication_flags stats_flags = {0};
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005717 int port = BP_PORT(bp);
5718 int func = BP_FUNC(bp);
Eilon Greensteinde832a52009-02-12 08:36:33 +00005719 int i, j;
5720 u32 offset;
Eilon Greenstein471de712008-08-13 15:49:35 -07005721 u16 max_agg_size;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005722
5723 if (is_multi(bp)) {
Eilon Greenstein555f6c72009-02-12 08:36:11 +00005724 tstorm_config.config_flags = MULTI_FLAGS(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005725 tstorm_config.rss_result_mask = MULTI_MASK;
5726 }
Eilon Greensteinca003922009-08-12 22:53:28 -07005727
5728 /* Enable TPA if needed */
5729 if (bp->flags & TPA_ENABLE_FLAG)
5730 tstorm_config.config_flags |=
5731 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
5732
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005733 if (IS_E1HMF(bp))
5734 tstorm_config.config_flags |=
5735 TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005736
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005737 tstorm_config.leading_client_id = BP_L_ID(bp);
5738
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005739 REG_WR(bp, BAR_TSTRORM_INTMEM +
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005740 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005741 (*(u32 *)&tstorm_config));
5742
Eliezer Tamirc14423f2008-02-28 11:49:42 -08005743 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
Michael Chan37b091b2009-10-10 13:46:55 +00005744 bp->rx_mode_cl_mask = (1 << BP_L_ID(bp));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005745 bnx2x_set_storm_rx_mode(bp);
5746
Eilon Greensteinde832a52009-02-12 08:36:33 +00005747 for_each_queue(bp, i) {
5748 u8 cl_id = bp->fp[i].cl_id;
5749
5750 /* reset xstorm per client statistics */
5751 offset = BAR_XSTRORM_INTMEM +
5752 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
5753 for (j = 0;
5754 j < sizeof(struct xstorm_per_client_stats) / 4; j++)
5755 REG_WR(bp, offset + j*4, 0);
5756
5757 /* reset tstorm per client statistics */
5758 offset = BAR_TSTRORM_INTMEM +
5759 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
5760 for (j = 0;
5761 j < sizeof(struct tstorm_per_client_stats) / 4; j++)
5762 REG_WR(bp, offset + j*4, 0);
5763
5764 /* reset ustorm per client statistics */
5765 offset = BAR_USTRORM_INTMEM +
5766 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
5767 for (j = 0;
5768 j < sizeof(struct ustorm_per_client_stats) / 4; j++)
5769 REG_WR(bp, offset + j*4, 0);
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005770 }
5771
5772 /* Init statistics related context */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005773 stats_flags.collect_eth = 1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005774
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005775 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005776 ((u32 *)&stats_flags)[0]);
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005777 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005778 ((u32 *)&stats_flags)[1]);
5779
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005780 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005781 ((u32 *)&stats_flags)[0]);
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005782 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005783 ((u32 *)&stats_flags)[1]);
5784
Eilon Greensteinde832a52009-02-12 08:36:33 +00005785 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
5786 ((u32 *)&stats_flags)[0]);
5787 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
5788 ((u32 *)&stats_flags)[1]);
5789
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005790 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005791 ((u32 *)&stats_flags)[0]);
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005792 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005793 ((u32 *)&stats_flags)[1]);
5794
Yitchak Gertner66e855f2008-08-13 15:49:05 -07005795 REG_WR(bp, BAR_XSTRORM_INTMEM +
5796 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
5797 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
5798 REG_WR(bp, BAR_XSTRORM_INTMEM +
5799 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
5800 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
5801
5802 REG_WR(bp, BAR_TSTRORM_INTMEM +
5803 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
5804 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
5805 REG_WR(bp, BAR_TSTRORM_INTMEM +
5806 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
5807 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005808
Eilon Greensteinde832a52009-02-12 08:36:33 +00005809 REG_WR(bp, BAR_USTRORM_INTMEM +
5810 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
5811 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
5812 REG_WR(bp, BAR_USTRORM_INTMEM +
5813 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
5814 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
5815
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005816 if (CHIP_IS_E1H(bp)) {
5817 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
5818 IS_E1HMF(bp));
5819 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
5820 IS_E1HMF(bp));
5821 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
5822 IS_E1HMF(bp));
5823 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
5824 IS_E1HMF(bp));
5825
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005826 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
5827 bp->e1hov);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005828 }
5829
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -08005830 /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
5831 max_agg_size =
5832 min((u32)(min((u32)8, (u32)MAX_SKB_FRAGS) *
5833 SGE_PAGE_SIZE * PAGES_PER_SGE),
5834 (u32)0xffff);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005835 for_each_queue(bp, i) {
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005836 struct bnx2x_fastpath *fp = &bp->fp[i];
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005837
5838 REG_WR(bp, BAR_USTRORM_INTMEM +
Eilon Greenstein0626b892009-02-12 08:38:14 +00005839 USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005840 U64_LO(fp->rx_comp_mapping));
5841 REG_WR(bp, BAR_USTRORM_INTMEM +
Eilon Greenstein0626b892009-02-12 08:38:14 +00005842 USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005843 U64_HI(fp->rx_comp_mapping));
5844
Eilon Greensteinca003922009-08-12 22:53:28 -07005845 /* Next page */
5846 REG_WR(bp, BAR_USTRORM_INTMEM +
5847 USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id),
5848 U64_LO(fp->rx_comp_mapping + BCM_PAGE_SIZE));
5849 REG_WR(bp, BAR_USTRORM_INTMEM +
5850 USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4,
5851 U64_HI(fp->rx_comp_mapping + BCM_PAGE_SIZE));
5852
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005853 REG_WR16(bp, BAR_USTRORM_INTMEM +
Eilon Greenstein0626b892009-02-12 08:38:14 +00005854 USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07005855 max_agg_size);
5856 }
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00005857
Eilon Greenstein1c063282009-02-12 08:36:43 +00005858 /* dropless flow control */
5859 if (CHIP_IS_E1H(bp)) {
5860 struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
5861
5862 rx_pause.bd_thr_low = 250;
5863 rx_pause.cqe_thr_low = 250;
5864 rx_pause.cos = 1;
5865 rx_pause.sge_thr_low = 0;
5866 rx_pause.bd_thr_high = 350;
5867 rx_pause.cqe_thr_high = 350;
5868 rx_pause.sge_thr_high = 0;
5869
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00005870 for_each_queue(bp, i) {
Eilon Greenstein1c063282009-02-12 08:36:43 +00005871 struct bnx2x_fastpath *fp = &bp->fp[i];
5872
5873 if (!fp->disable_tpa) {
5874 rx_pause.sge_thr_low = 150;
5875 rx_pause.sge_thr_high = 250;
5876 }
5877
5878
5879 offset = BAR_USTRORM_INTMEM +
5880 USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
5881 fp->cl_id);
5882 for (j = 0;
5883 j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
5884 j++)
5885 REG_WR(bp, offset + j*4,
5886 ((u32 *)&rx_pause)[j]);
5887 }
5888 }
5889
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00005890 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
5891
5892 /* Init rate shaping and fairness contexts */
5893 if (IS_E1HMF(bp)) {
5894 int vn;
5895
5896 /* During init there is no active link
5897 Until link is up, set link rate to 10Gbps */
5898 bp->link_vars.line_speed = SPEED_10000;
5899 bnx2x_init_port_minmax(bp);
5900
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07005901 if (!BP_NOMCP(bp))
5902 bp->mf_config =
5903 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00005904 bnx2x_calc_vn_weight_sum(bp);
5905
5906 for (vn = VN_0; vn < E1HVN_MAX; vn++)
5907 bnx2x_init_vn_minmax(bp, 2*vn + port);
5908
5909 /* Enable rate shaping and fairness */
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07005910 bp->cmng.flags.cmng_enables |=
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00005911 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07005912
Eilon Greenstein8a1c38d2009-02-12 08:36:40 +00005913 } else {
5914 /* rate shaping and fairness are disabled */
5915 DP(NETIF_MSG_IFUP,
5916 "single function mode minmax will be disabled\n");
5917 }
5918
5919
5920 /* Store it to internal memory */
5921 if (bp->port.pmf)
5922 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
5923 REG_WR(bp, BAR_XSTRORM_INTMEM +
5924 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
5925 ((u32 *)(&bp->cmng))[i]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005926}
5927
Eilon Greenstein471de712008-08-13 15:49:35 -07005928static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5929{
5930 switch (load_code) {
5931 case FW_MSG_CODE_DRV_LOAD_COMMON:
5932 bnx2x_init_internal_common(bp);
5933 /* no break */
5934
5935 case FW_MSG_CODE_DRV_LOAD_PORT:
5936 bnx2x_init_internal_port(bp);
5937 /* no break */
5938
5939 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5940 bnx2x_init_internal_func(bp);
5941 break;
5942
5943 default:
5944 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5945 break;
5946 }
5947}
5948
5949static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005950{
5951 int i;
5952
5953 for_each_queue(bp, i) {
5954 struct bnx2x_fastpath *fp = &bp->fp[i];
5955
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005956 fp->bp = bp;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005957 fp->state = BNX2X_FP_STATE_CLOSED;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005958 fp->index = i;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005959 fp->cl_id = BP_L_ID(bp) + i;
Michael Chan37b091b2009-10-10 13:46:55 +00005960#ifdef BCM_CNIC
5961 fp->sb_id = fp->cl_id + 1;
5962#else
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005963 fp->sb_id = fp->cl_id;
Michael Chan37b091b2009-10-10 13:46:55 +00005964#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07005965 DP(NETIF_MSG_IFUP,
Eilon Greensteinf5372252009-02-12 08:38:30 +00005966 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d sb %d\n",
5967 i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
Eilon Greenstein5c862842008-08-13 15:51:48 -07005968 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
Eilon Greenstein0626b892009-02-12 08:38:14 +00005969 fp->sb_id);
Eilon Greenstein5c862842008-08-13 15:51:48 -07005970 bnx2x_update_fpsb_idx(fp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005971 }
5972
Eilon Greenstein16119782009-03-02 07:59:27 +00005973 /* ensure status block indices were read */
5974 rmb();
5975
5976
Eilon Greenstein5c862842008-08-13 15:51:48 -07005977 bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
5978 DEF_SB_ID);
5979 bnx2x_update_dsb_idx(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005980 bnx2x_update_coalesce(bp);
5981 bnx2x_init_rx_rings(bp);
5982 bnx2x_init_tx_ring(bp);
5983 bnx2x_init_sp_ring(bp);
5984 bnx2x_init_context(bp);
Eilon Greenstein471de712008-08-13 15:49:35 -07005985 bnx2x_init_internal(bp, load_code);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005986 bnx2x_init_ind_table(bp);
Eilon Greenstein0ef00452009-01-14 21:31:08 -08005987 bnx2x_stats_init(bp);
5988
5989 /* At this point, we are ready for interrupts */
5990 atomic_set(&bp->intr_sem, 0);
5991
5992 /* flush all before enabling interrupts */
5993 mb();
5994 mmiowb();
5995
Eliezer Tamir615f8fd2008-02-28 11:54:54 -08005996 bnx2x_int_enable(bp);
Eilon Greensteineb8da202009-07-21 05:47:30 +00005997
5998 /* Check for SPIO5 */
5999 bnx2x_attn_int_deasserted0(bp,
6000 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6001 AEU_INPUTS_ATTN_BITS_SPIO5);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006002}
6003
6004/* end of nic init */
6005
6006/*
6007 * gzip service functions
6008 */
6009
6010static int bnx2x_gunzip_init(struct bnx2x *bp)
6011{
FUJITA Tomonori1a983142010-04-04 01:51:03 +00006012 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6013 &bp->gunzip_mapping, GFP_KERNEL);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006014 if (bp->gunzip_buf == NULL)
6015 goto gunzip_nomem1;
6016
6017 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6018 if (bp->strm == NULL)
6019 goto gunzip_nomem2;
6020
6021 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
6022 GFP_KERNEL);
6023 if (bp->strm->workspace == NULL)
6024 goto gunzip_nomem3;
6025
6026 return 0;
6027
6028gunzip_nomem3:
6029 kfree(bp->strm);
6030 bp->strm = NULL;
6031
6032gunzip_nomem2:
FUJITA Tomonori1a983142010-04-04 01:51:03 +00006033 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6034 bp->gunzip_mapping);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006035 bp->gunzip_buf = NULL;
6036
6037gunzip_nomem1:
Joe Perches7995c642010-02-17 15:01:52 +00006038 netdev_err(bp->dev, "Cannot allocate firmware buffer for un-compression\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006039 return -ENOMEM;
6040}
6041
6042static void bnx2x_gunzip_end(struct bnx2x *bp)
6043{
6044 kfree(bp->strm->workspace);
6045
6046 kfree(bp->strm);
6047 bp->strm = NULL;
6048
6049 if (bp->gunzip_buf) {
FUJITA Tomonori1a983142010-04-04 01:51:03 +00006050 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6051 bp->gunzip_mapping);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006052 bp->gunzip_buf = NULL;
6053 }
6054}
6055
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006056static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006057{
6058 int n, rc;
6059
6060 /* check gzip header */
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006061 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6062 BNX2X_ERR("Bad gzip header\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006063 return -EINVAL;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006064 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006065
6066 n = 10;
6067
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006068#define FNAME 0x8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006069
6070 if (zbuf[3] & FNAME)
6071 while ((zbuf[n++] != 0) && (n < len));
6072
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006073 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006074 bp->strm->avail_in = len - n;
6075 bp->strm->next_out = bp->gunzip_buf;
6076 bp->strm->avail_out = FW_BUF_SIZE;
6077
6078 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6079 if (rc != Z_OK)
6080 return rc;
6081
6082 rc = zlib_inflate(bp->strm, Z_FINISH);
6083 if ((rc != Z_OK) && (rc != Z_STREAM_END))
Joe Perches7995c642010-02-17 15:01:52 +00006084 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6085 bp->strm->msg);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006086
6087 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6088 if (bp->gunzip_outlen & 0x3)
Joe Perches7995c642010-02-17 15:01:52 +00006089 netdev_err(bp->dev, "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6090 bp->gunzip_outlen);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006091 bp->gunzip_outlen >>= 2;
6092
6093 zlib_inflateEnd(bp->strm);
6094
6095 if (rc == Z_STREAM_END)
6096 return 0;
6097
6098 return rc;
6099}
6100
6101/* nic load/unload */
6102
6103/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006104 * General service functions
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006105 */
6106
6107/* send a NIG loopback debug packet */
6108static void bnx2x_lb_pckt(struct bnx2x *bp)
6109{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006110 u32 wb_write[3];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006111
6112 /* Ethernet source and destination addresses */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006113 wb_write[0] = 0x55555555;
6114 wb_write[1] = 0x55555555;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006115 wb_write[2] = 0x20; /* SOP */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006116 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006117
6118 /* NON-IP protocol */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006119 wb_write[0] = 0x09000000;
6120 wb_write[1] = 0x55555555;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006121 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006122 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006123}
6124
6125/* some of the internal memories
6126 * are not directly readable from the driver
6127 * to test them we send debug packets
6128 */
6129static int bnx2x_int_mem_test(struct bnx2x *bp)
6130{
6131 int factor;
6132 int count, i;
6133 u32 val = 0;
6134
Eilon Greensteinad8d3942008-06-23 20:29:02 -07006135 if (CHIP_REV_IS_FPGA(bp))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006136 factor = 120;
Eilon Greensteinad8d3942008-06-23 20:29:02 -07006137 else if (CHIP_REV_IS_EMUL(bp))
6138 factor = 200;
6139 else
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006140 factor = 1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006141
6142 DP(NETIF_MSG_HW, "start part1\n");
6143
6144 /* Disable inputs of parser neighbor blocks */
6145 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6146 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6147 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
Eilon Greenstein3196a882008-08-13 15:58:49 -07006148 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006149
6150 /* Write 0 to parser credits for CFC search request */
6151 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6152
6153 /* send Ethernet packet */
6154 bnx2x_lb_pckt(bp);
6155
6156 /* TODO do i reset NIG statistic? */
6157 /* Wait until NIG register shows 1 packet of size 0x10 */
6158 count = 1000 * factor;
6159 while (count) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006160
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006161 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6162 val = *bnx2x_sp(bp, wb_data[0]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006163 if (val == 0x10)
6164 break;
6165
6166 msleep(10);
6167 count--;
6168 }
6169 if (val != 0x10) {
6170 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6171 return -1;
6172 }
6173
6174 /* Wait until PRS register shows 1 packet */
6175 count = 1000 * factor;
6176 while (count) {
6177 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006178 if (val == 1)
6179 break;
6180
6181 msleep(10);
6182 count--;
6183 }
6184 if (val != 0x1) {
6185 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6186 return -2;
6187 }
6188
6189 /* Reset and init BRB, PRS */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006190 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006191 msleep(50);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006192 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006193 msleep(50);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006194 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
6195 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006196
6197 DP(NETIF_MSG_HW, "part2\n");
6198
6199 /* Disable inputs of parser neighbor blocks */
6200 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6201 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6202 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
Eilon Greenstein3196a882008-08-13 15:58:49 -07006203 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006204
6205 /* Write 0 to parser credits for CFC search request */
6206 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6207
6208 /* send 10 Ethernet packets */
6209 for (i = 0; i < 10; i++)
6210 bnx2x_lb_pckt(bp);
6211
6212 /* Wait until NIG register shows 10 + 1
6213 packets of size 11*0x10 = 0xb0 */
6214 count = 1000 * factor;
6215 while (count) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006216
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006217 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6218 val = *bnx2x_sp(bp, wb_data[0]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006219 if (val == 0xb0)
6220 break;
6221
6222 msleep(10);
6223 count--;
6224 }
6225 if (val != 0xb0) {
6226 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6227 return -3;
6228 }
6229
6230 /* Wait until PRS register shows 2 packets */
6231 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6232 if (val != 2)
6233 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6234
6235 /* Write 1 to parser credits for CFC search request */
6236 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6237
6238 /* Wait until PRS register shows 3 packets */
6239 msleep(10 * factor);
6240 /* Wait until NIG register shows 1 packet of size 0x10 */
6241 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6242 if (val != 3)
6243 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6244
6245 /* clear NIG EOP FIFO */
6246 for (i = 0; i < 11; i++)
6247 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6248 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6249 if (val != 1) {
6250 BNX2X_ERR("clear of NIG failed\n");
6251 return -4;
6252 }
6253
6254 /* Reset and init BRB, PRS, NIG */
6255 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6256 msleep(50);
6257 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6258 msleep(50);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006259 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
6260 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
Michael Chan37b091b2009-10-10 13:46:55 +00006261#ifndef BCM_CNIC
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006262 /* set NIC mode */
6263 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6264#endif
6265
6266 /* Enable inputs of parser neighbor blocks */
6267 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6268 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6269 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
Eilon Greenstein3196a882008-08-13 15:58:49 -07006270 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006271
6272 DP(NETIF_MSG_HW, "done\n");
6273
6274 return 0; /* OK */
6275}
6276
6277static void enable_blocks_attention(struct bnx2x *bp)
6278{
6279 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6280 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6281 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6282 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6283 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6284 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6285 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6286 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6287 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006288/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6289/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006290 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6291 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6292 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006293/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6294/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006295 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6296 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6297 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6298 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006299/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6300/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6301 if (CHIP_REV_IS_FPGA(bp))
6302 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6303 else
6304 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006305 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6306 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6307 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006308/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6309/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006310 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6311 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006312/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6313 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006314}
6315
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00006316static const struct {
6317 u32 addr;
6318 u32 mask;
6319} bnx2x_parity_mask[] = {
6320 {PXP_REG_PXP_PRTY_MASK, 0xffffffff},
6321 {PXP2_REG_PXP2_PRTY_MASK_0, 0xffffffff},
6322 {PXP2_REG_PXP2_PRTY_MASK_1, 0xffffffff},
6323 {HC_REG_HC_PRTY_MASK, 0xffffffff},
6324 {MISC_REG_MISC_PRTY_MASK, 0xffffffff},
6325 {QM_REG_QM_PRTY_MASK, 0x0},
6326 {DORQ_REG_DORQ_PRTY_MASK, 0x0},
6327 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
6328 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
6329 {SRC_REG_SRC_PRTY_MASK, 0x4}, /* bit 2 */
6330 {CDU_REG_CDU_PRTY_MASK, 0x0},
6331 {CFC_REG_CFC_PRTY_MASK, 0x0},
6332 {DBG_REG_DBG_PRTY_MASK, 0x0},
6333 {DMAE_REG_DMAE_PRTY_MASK, 0x0},
6334 {BRB1_REG_BRB1_PRTY_MASK, 0x0},
6335 {PRS_REG_PRS_PRTY_MASK, (1<<6)},/* bit 6 */
6336 {TSDM_REG_TSDM_PRTY_MASK, 0x18},/* bit 3,4 */
6337 {CSDM_REG_CSDM_PRTY_MASK, 0x8}, /* bit 3 */
6338 {USDM_REG_USDM_PRTY_MASK, 0x38},/* bit 3,4,5 */
6339 {XSDM_REG_XSDM_PRTY_MASK, 0x8}, /* bit 3 */
6340 {TSEM_REG_TSEM_PRTY_MASK_0, 0x0},
6341 {TSEM_REG_TSEM_PRTY_MASK_1, 0x0},
6342 {USEM_REG_USEM_PRTY_MASK_0, 0x0},
6343 {USEM_REG_USEM_PRTY_MASK_1, 0x0},
6344 {CSEM_REG_CSEM_PRTY_MASK_0, 0x0},
6345 {CSEM_REG_CSEM_PRTY_MASK_1, 0x0},
6346 {XSEM_REG_XSEM_PRTY_MASK_0, 0x0},
6347 {XSEM_REG_XSEM_PRTY_MASK_1, 0x0}
6348};
6349
6350static void enable_blocks_parity(struct bnx2x *bp)
6351{
6352 int i, mask_arr_len =
6353 sizeof(bnx2x_parity_mask)/(sizeof(bnx2x_parity_mask[0]));
6354
6355 for (i = 0; i < mask_arr_len; i++)
6356 REG_WR(bp, bnx2x_parity_mask[i].addr,
6357 bnx2x_parity_mask[i].mask);
6358}
6359
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006360
Eilon Greenstein81f75bb2009-01-22 03:37:31 +00006361static void bnx2x_reset_common(struct bnx2x *bp)
6362{
6363 /* reset_common */
6364 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6365 0xd3ffff7f);
6366 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
6367}
6368
Eilon Greenstein573f2032009-08-12 08:24:14 +00006369static void bnx2x_init_pxp(struct bnx2x *bp)
6370{
6371 u16 devctl;
6372 int r_order, w_order;
6373
6374 pci_read_config_word(bp->pdev,
6375 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
6376 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6377 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6378 if (bp->mrrs == -1)
6379 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6380 else {
6381 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6382 r_order = bp->mrrs;
6383 }
6384
6385 bnx2x_init_pxp_arb(bp, r_order, w_order);
6386}
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00006387
6388static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6389{
Vladislav Zolotarov2145a922010-04-19 01:13:49 +00006390 int is_required;
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00006391 u32 val;
Vladislav Zolotarov2145a922010-04-19 01:13:49 +00006392 int port;
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00006393
Vladislav Zolotarov2145a922010-04-19 01:13:49 +00006394 if (BP_NOMCP(bp))
6395 return;
6396
6397 is_required = 0;
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00006398 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6399 SHARED_HW_CFG_FAN_FAILURE_MASK;
6400
6401 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6402 is_required = 1;
6403
6404 /*
6405 * The fan failure mechanism is usually related to the PHY type since
6406 * the power consumption of the board is affected by the PHY. Currently,
6407 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6408 */
6409 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6410 for (port = PORT_0; port < PORT_MAX; port++) {
6411 u32 phy_type =
6412 SHMEM_RD(bp, dev_info.port_hw_config[port].
6413 external_phy_config) &
6414 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
6415 is_required |=
6416 ((phy_type ==
6417 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
6418 (phy_type ==
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006419 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6420 (phy_type ==
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00006421 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
6422 }
6423
6424 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6425
6426 if (is_required == 0)
6427 return;
6428
6429 /* Fan failure is indicated by SPIO 5 */
6430 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6431 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6432
6433 /* set to active low mode */
6434 val = REG_RD(bp, MISC_REG_SPIO_INT);
6435 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6436 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6437 REG_WR(bp, MISC_REG_SPIO_INT, val);
6438
6439 /* enable interrupt to signal the IGU */
6440 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6441 val |= (1 << MISC_REGISTERS_SPIO_5);
6442 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6443}
6444
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006445static int bnx2x_init_common(struct bnx2x *bp)
6446{
6447 u32 val, i;
Michael Chan37b091b2009-10-10 13:46:55 +00006448#ifdef BCM_CNIC
6449 u32 wb_write[2];
6450#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006451
6452 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_FUNC(bp));
6453
Eilon Greenstein81f75bb2009-01-22 03:37:31 +00006454 bnx2x_reset_common(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006455 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6456 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
6457
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006458 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006459 if (CHIP_IS_E1H(bp))
6460 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
6461
6462 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
6463 msleep(30);
6464 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
6465
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006466 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006467 if (CHIP_IS_E1(bp)) {
6468 /* enable HW interrupt from PXP on USDM overflow
6469 bit 16 on INT_MASK_0 */
6470 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006471 }
6472
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006473 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006474 bnx2x_init_pxp(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006475
6476#ifdef __BIG_ENDIAN
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006477 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6478 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6479 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6480 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6481 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
Eilon Greenstein8badd272009-02-12 08:36:15 +00006482 /* make sure this value is 0 */
6483 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006484
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006485/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6486 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6487 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6488 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6489 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006490#endif
6491
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006492 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
Michael Chan37b091b2009-10-10 13:46:55 +00006493#ifdef BCM_CNIC
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006494 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
6495 REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
6496 REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006497#endif
6498
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006499 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6500 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006501
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006502 /* let the HW do it's magic ... */
6503 msleep(100);
6504 /* finish PXP init */
6505 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6506 if (val != 1) {
6507 BNX2X_ERR("PXP2 CFG failed\n");
6508 return -EBUSY;
6509 }
6510 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6511 if (val != 1) {
6512 BNX2X_ERR("PXP2 RD_INIT failed\n");
6513 return -EBUSY;
6514 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006515
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006516 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6517 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006518
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006519 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006520
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006521 /* clean the DMAE memory */
6522 bp->dmae_ready = 1;
6523 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006524
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006525 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
6526 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
6527 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
6528 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006529
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006530 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6531 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6532 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6533 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6534
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006535 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
Michael Chan37b091b2009-10-10 13:46:55 +00006536
6537#ifdef BCM_CNIC
6538 wb_write[0] = 0;
6539 wb_write[1] = 0;
6540 for (i = 0; i < 64; i++) {
6541 REG_WR(bp, QM_REG_BASEADDR + i*4, 1024 * 4 * (i%16));
6542 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8, wb_write, 2);
6543
6544 if (CHIP_IS_E1H(bp)) {
6545 REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4, 1024*4*(i%16));
6546 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8,
6547 wb_write, 2);
6548 }
6549 }
6550#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006551 /* soft reset pulse */
6552 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6553 REG_WR(bp, QM_REG_SOFT_RESET, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006554
Michael Chan37b091b2009-10-10 13:46:55 +00006555#ifdef BCM_CNIC
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006556 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006557#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006558
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006559 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006560 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
6561 if (!CHIP_REV_IS_SLOW(bp)) {
6562 /* enable hw interrupt from doorbell Q */
6563 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6564 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006565
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006566 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
6567 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
Eilon Greenstein26c8fa42009-01-14 21:29:55 -08006568 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
Michael Chan37b091b2009-10-10 13:46:55 +00006569#ifndef BCM_CNIC
Eilon Greenstein3196a882008-08-13 15:58:49 -07006570 /* set NIC mode */
6571 REG_WR(bp, PRS_REG_NIC_MODE, 1);
Michael Chan37b091b2009-10-10 13:46:55 +00006572#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006573 if (CHIP_IS_E1H(bp))
6574 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006575
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006576 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
6577 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
6578 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
6579 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006580
Eilon Greensteinca003922009-08-12 22:53:28 -07006581 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
6582 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
6583 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
6584 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006585
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006586 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
6587 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
6588 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
6589 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006590
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006591 /* sync semi rtc */
6592 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6593 0x80000000);
6594 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6595 0x80000000);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006596
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006597 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
6598 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
6599 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006600
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006601 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6602 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
6603 REG_WR(bp, i, 0xc0cac01a);
6604 /* TODO: replace with something meaningful */
6605 }
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006606 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
Michael Chan37b091b2009-10-10 13:46:55 +00006607#ifdef BCM_CNIC
6608 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6609 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6610 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6611 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6612 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6613 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6614 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6615 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6616 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6617 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6618#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006619 REG_WR(bp, SRC_REG_SOFT_RST, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006620
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006621 if (sizeof(union cdu_context) != 1024)
6622 /* we currently assume that a context is 1024 bytes */
Joe Perches7995c642010-02-17 15:01:52 +00006623 pr_alert("please adjust the size of cdu_context(%ld)\n",
6624 (long)sizeof(union cdu_context));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006625
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006626 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006627 val = (4 << 24) + (0 << 12) + 1024;
6628 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006629
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006630 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006631 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08006632 /* enable context validation interrupt from CFC */
6633 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6634
6635 /* set the thresholds to prevent CFC/CDU race */
6636 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006637
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006638 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
6639 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006640
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006641 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006642 /* Reset PCIE errors for debug */
6643 REG_WR(bp, 0x2814, 0xffffffff);
6644 REG_WR(bp, 0x3820, 0xffffffff);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006645
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006646 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006647 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006648 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006649 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006650
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006651 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006652 if (CHIP_IS_E1H(bp)) {
6653 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
6654 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
6655 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006656
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006657 if (CHIP_REV_IS_SLOW(bp))
6658 msleep(200);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006659
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006660 /* finish CFC init */
6661 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6662 if (val != 1) {
6663 BNX2X_ERR("CFC LL_INIT failed\n");
6664 return -EBUSY;
6665 }
6666 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6667 if (val != 1) {
6668 BNX2X_ERR("CFC AC_INIT failed\n");
6669 return -EBUSY;
6670 }
6671 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6672 if (val != 1) {
6673 BNX2X_ERR("CFC CAM_INIT failed\n");
6674 return -EBUSY;
6675 }
6676 REG_WR(bp, CFC_REG_DEBUG0, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006677
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006678 /* read NIG statistic
6679 to see if this is our first up since powerup */
6680 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6681 val = *bnx2x_sp(bp, wb_data[0]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006682
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006683 /* do internal memory self test */
6684 if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
6685 BNX2X_ERR("internal mem self test failed\n");
6686 return -EBUSY;
6687 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006688
Eilon Greenstein35b19ba2009-02-12 08:36:47 +00006689 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
Eilon Greenstein46c6a672009-02-12 08:36:58 +00006690 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6691 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6692 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006693 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
Eilon Greenstein46c6a672009-02-12 08:36:58 +00006694 bp->port.need_hw_lock = 1;
6695 break;
6696
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006697 default:
6698 break;
6699 }
Eliezer Tamirf1410642008-02-28 11:51:50 -08006700
Eilon Greensteinfd4ef402009-07-21 05:47:27 +00006701 bnx2x_setup_fan_failure_detection(bp);
6702
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006703 /* clear PXP2 attentions */
6704 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006705
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006706 enable_blocks_attention(bp);
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00006707 if (CHIP_PARITY_SUPPORTED(bp))
6708 enable_blocks_parity(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006709
Yaniv Rosner6bbca912008-08-13 15:57:28 -07006710 if (!BP_NOMCP(bp)) {
6711 bnx2x_acquire_phy_lock(bp);
6712 bnx2x_common_init_phy(bp, bp->common.shmem_base);
6713 bnx2x_release_phy_lock(bp);
6714 } else
6715 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6716
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006717 return 0;
6718}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006719
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006720static int bnx2x_init_port(struct bnx2x *bp)
6721{
6722 int port = BP_PORT(bp);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006723 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
Eilon Greenstein1c063282009-02-12 08:36:43 +00006724 u32 low, high;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006725 u32 val;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006726
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006727 DP(BNX2X_MSG_MCP, "starting port init port %x\n", port);
6728
6729 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006730
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006731 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006732 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
Eilon Greensteinca003922009-08-12 22:53:28 -07006733
6734 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
6735 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
6736 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006737 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006738
Michael Chan37b091b2009-10-10 13:46:55 +00006739#ifdef BCM_CNIC
6740 REG_WR(bp, QM_REG_CONNNUM_0 + port*4, 1024/16 - 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006741
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006742 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
Michael Chan37b091b2009-10-10 13:46:55 +00006743 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6744 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006745#endif
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006746 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
Eilon Greenstein1c063282009-02-12 08:36:43 +00006747
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006748 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
Eilon Greenstein1c063282009-02-12 08:36:43 +00006749 if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
6750 /* no pause for emulation and FPGA */
6751 low = 0;
6752 high = 513;
6753 } else {
6754 if (IS_E1HMF(bp))
6755 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6756 else if (bp->dev->mtu > 4096) {
6757 if (bp->flags & ONE_PORT_FLAG)
6758 low = 160;
6759 else {
6760 val = bp->dev->mtu;
6761 /* (24*1024 + val*4)/256 */
6762 low = 96 + (val/64) + ((val % 64) ? 1 : 0);
6763 }
6764 } else
6765 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6766 high = low + 56; /* 14*1024/256 */
6767 }
6768 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6769 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6770
6771
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006772 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
Eilon Greensteinca003922009-08-12 22:53:28 -07006773
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006774 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006775 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006776 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006777 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
Eilon Greenstein356e2382009-02-12 08:38:32 +00006778
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006779 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
6780 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
6781 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
6782 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
Eilon Greenstein356e2382009-02-12 08:38:32 +00006783
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006784 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006785 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006786
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006787 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006788
6789 /* configure PBF to work without PAUSE mtu 9000 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006790 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006791
6792 /* update threshold */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006793 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006794 /* update init credit */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006795 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006796
6797 /* probe changes */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006798 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006799 msleep(5);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006800 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006801
Michael Chan37b091b2009-10-10 13:46:55 +00006802#ifdef BCM_CNIC
6803 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006804#endif
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006805 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006806 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006807
6808 if (CHIP_IS_E1(bp)) {
6809 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6810 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6811 }
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006812 bnx2x_init_block(bp, HC_BLOCK, init_stage);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006813
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006814 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006815 /* init aeu_mask_attn_func_0/1:
6816 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6817 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6818 * bits 4-7 are used for "per vn group attention" */
6819 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
6820 (IS_E1HMF(bp) ? 0xF7 : 0x7));
6821
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006822 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006823 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006824 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006825 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006826 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
Eilon Greenstein356e2382009-02-12 08:38:32 +00006827
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006828 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006829
6830 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6831
6832 if (CHIP_IS_E1H(bp)) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006833 /* 0x2 disable e1hov, 0x1 enable */
6834 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6835 (IS_E1HMF(bp) ? 0x1 : 0x2));
6836
Eilon Greenstein1c063282009-02-12 08:36:43 +00006837 {
6838 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6839 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6840 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6841 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006842 }
6843
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006844 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07006845 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006846
Eilon Greenstein35b19ba2009-02-12 08:36:47 +00006847 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
Eilon Greenstein589abe32009-02-12 08:36:55 +00006848 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6849 {
6850 u32 swap_val, swap_override, aeu_gpio_mask, offset;
6851
6852 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6853 MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
6854
6855 /* The GPIO should be swapped if the swap register is
6856 set and active */
6857 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6858 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6859
6860 /* Select function upon port-swap configuration */
6861 if (port == 0) {
6862 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
6863 aeu_gpio_mask = (swap_val && swap_override) ?
6864 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
6865 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
6866 } else {
6867 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
6868 aeu_gpio_mask = (swap_val && swap_override) ?
6869 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
6870 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
6871 }
6872 val = REG_RD(bp, offset);
6873 /* add GPIO3 to group */
6874 val |= aeu_gpio_mask;
6875 REG_WR(bp, offset, val);
6876 }
6877 break;
6878
Eilon Greenstein35b19ba2009-02-12 08:36:47 +00006879 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006880 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
Eliezer Tamirf1410642008-02-28 11:51:50 -08006881 /* add SPIO 5 to group 0 */
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006882 {
6883 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6884 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6885 val = REG_RD(bp, reg_addr);
Eliezer Tamirf1410642008-02-28 11:51:50 -08006886 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006887 REG_WR(bp, reg_addr, val);
6888 }
Eliezer Tamirf1410642008-02-28 11:51:50 -08006889 break;
6890
6891 default:
6892 break;
6893 }
6894
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006895 bnx2x__link_reset(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006896
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006897 return 0;
6898}
6899
6900#define ILT_PER_FUNC (768/2)
6901#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
6902/* the phys address is shifted right 12 bits and has an added
6903 1=valid bit added to the 53rd bit
6904 then since this is a wide register(TM)
6905 we split it into two 32 bit writes
6906 */
6907#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
6908#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
6909#define PXP_ONE_ILT(x) (((x) << 10) | x)
6910#define PXP_ILT_RANGE(f, l) (((l) << 10) | f)
6911
Michael Chan37b091b2009-10-10 13:46:55 +00006912#ifdef BCM_CNIC
6913#define CNIC_ILT_LINES 127
6914#define CNIC_CTX_PER_ILT 16
6915#else
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006916#define CNIC_ILT_LINES 0
Michael Chan37b091b2009-10-10 13:46:55 +00006917#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006918
6919static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6920{
6921 int reg;
6922
6923 if (CHIP_IS_E1H(bp))
6924 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6925 else /* E1 */
6926 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6927
6928 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6929}
6930
6931static int bnx2x_init_func(struct bnx2x *bp)
6932{
6933 int port = BP_PORT(bp);
6934 int func = BP_FUNC(bp);
Eilon Greenstein8badd272009-02-12 08:36:15 +00006935 u32 addr, val;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006936 int i;
6937
6938 DP(BNX2X_MSG_MCP, "starting func init func %x\n", func);
6939
Eilon Greenstein8badd272009-02-12 08:36:15 +00006940 /* set MSI reconfigure capability */
6941 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6942 val = REG_RD(bp, addr);
6943 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6944 REG_WR(bp, addr, val);
6945
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006946 i = FUNC_ILT_BASE(func);
6947
6948 bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
6949 if (CHIP_IS_E1H(bp)) {
6950 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
6951 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
6952 } else /* E1 */
6953 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
6954 PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
6955
Michael Chan37b091b2009-10-10 13:46:55 +00006956#ifdef BCM_CNIC
6957 i += 1 + CNIC_ILT_LINES;
6958 bnx2x_ilt_wr(bp, i, bp->timers_mapping);
6959 if (CHIP_IS_E1(bp))
6960 REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
6961 else {
6962 REG_WR(bp, PXP2_REG_RQ_TM_FIRST_ILT, i);
6963 REG_WR(bp, PXP2_REG_RQ_TM_LAST_ILT, i);
6964 }
6965
6966 i++;
6967 bnx2x_ilt_wr(bp, i, bp->qm_mapping);
6968 if (CHIP_IS_E1(bp))
6969 REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
6970 else {
6971 REG_WR(bp, PXP2_REG_RQ_QM_FIRST_ILT, i);
6972 REG_WR(bp, PXP2_REG_RQ_QM_LAST_ILT, i);
6973 }
6974
6975 i++;
6976 bnx2x_ilt_wr(bp, i, bp->t1_mapping);
6977 if (CHIP_IS_E1(bp))
6978 REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
6979 else {
6980 REG_WR(bp, PXP2_REG_RQ_SRC_FIRST_ILT, i);
6981 REG_WR(bp, PXP2_REG_RQ_SRC_LAST_ILT, i);
6982 }
6983
6984 /* tell the searcher where the T2 table is */
6985 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, 16*1024/64);
6986
6987 bnx2x_wb_wr(bp, SRC_REG_FIRSTFREE0 + port*16,
6988 U64_LO(bp->t2_mapping), U64_HI(bp->t2_mapping));
6989
6990 bnx2x_wb_wr(bp, SRC_REG_LASTFREE0 + port*16,
6991 U64_LO((u64)bp->t2_mapping + 16*1024 - 64),
6992 U64_HI((u64)bp->t2_mapping + 16*1024 - 64));
6993
6994 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, 10);
6995#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07006996
6997 if (CHIP_IS_E1H(bp)) {
Eilon Greenstein573f2032009-08-12 08:24:14 +00006998 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
6999 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
7000 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
7001 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
7002 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
7003 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
7004 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
7005 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
7006 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007007
7008 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7009 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
7010 }
7011
7012 /* HC init per function */
7013 if (CHIP_IS_E1H(bp)) {
7014 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7015
7016 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7017 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7018 }
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -07007019 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007020
Eliezer Tamirc14423f2008-02-28 11:49:42 -08007021 /* Reset PCIE errors for debug */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007022 REG_WR(bp, 0x2114, 0xffffffff);
7023 REG_WR(bp, 0x2120, 0xffffffff);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007024
7025 return 0;
7026}
7027
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007028static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
7029{
7030 int i, rc = 0;
7031
7032 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
7033 BP_FUNC(bp), load_code);
7034
7035 bp->dmae_ready = 0;
7036 mutex_init(&bp->dmae_mutex);
Eilon Greenstein54016b22009-08-12 08:23:48 +00007037 rc = bnx2x_gunzip_init(bp);
7038 if (rc)
7039 return rc;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007040
7041 switch (load_code) {
7042 case FW_MSG_CODE_DRV_LOAD_COMMON:
7043 rc = bnx2x_init_common(bp);
7044 if (rc)
7045 goto init_hw_err;
7046 /* no break */
7047
7048 case FW_MSG_CODE_DRV_LOAD_PORT:
7049 bp->dmae_ready = 1;
7050 rc = bnx2x_init_port(bp);
7051 if (rc)
7052 goto init_hw_err;
7053 /* no break */
7054
7055 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
7056 bp->dmae_ready = 1;
7057 rc = bnx2x_init_func(bp);
7058 if (rc)
7059 goto init_hw_err;
7060 break;
7061
7062 default:
7063 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
7064 break;
7065 }
7066
7067 if (!BP_NOMCP(bp)) {
7068 int func = BP_FUNC(bp);
7069
7070 bp->fw_drv_pulse_wr_seq =
7071 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
7072 DRV_PULSE_SEQ_MASK);
Eilon Greenstein6fe49bb2009-08-12 08:23:17 +00007073 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
7074 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007075
7076 /* this needs to be done before gunzip end */
7077 bnx2x_zero_def_sb(bp);
7078 for_each_queue(bp, i)
7079 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
Michael Chan37b091b2009-10-10 13:46:55 +00007080#ifdef BCM_CNIC
7081 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
7082#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007083
7084init_hw_err:
7085 bnx2x_gunzip_end(bp);
7086
7087 return rc;
7088}
7089
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007090static void bnx2x_free_mem(struct bnx2x *bp)
7091{
7092
7093#define BNX2X_PCI_FREE(x, y, size) \
7094 do { \
7095 if (x) { \
FUJITA Tomonori1a983142010-04-04 01:51:03 +00007096 dma_free_coherent(&bp->pdev->dev, size, x, y); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007097 x = NULL; \
7098 y = 0; \
7099 } \
7100 } while (0)
7101
7102#define BNX2X_FREE(x) \
7103 do { \
7104 if (x) { \
7105 vfree(x); \
7106 x = NULL; \
7107 } \
7108 } while (0)
7109
7110 int i;
7111
7112 /* fastpath */
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007113 /* Common */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007114 for_each_queue(bp, i) {
7115
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007116 /* status blocks */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007117 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
7118 bnx2x_fp(bp, i, status_blk_mapping),
Eilon Greensteinca003922009-08-12 22:53:28 -07007119 sizeof(struct host_status_block));
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007120 }
7121 /* Rx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007122 for_each_queue(bp, i) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007123
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007124 /* fastpath rx rings: rx_buf rx_desc rx_comp */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007125 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
7126 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
7127 bnx2x_fp(bp, i, rx_desc_mapping),
7128 sizeof(struct eth_rx_bd) * NUM_RX_BD);
7129
7130 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
7131 bnx2x_fp(bp, i, rx_comp_mapping),
7132 sizeof(struct eth_fast_path_rx_cqe) *
7133 NUM_RCQ_BD);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007134
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07007135 /* SGE ring */
Eilon Greenstein32626232008-08-13 15:51:07 -07007136 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07007137 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
7138 bnx2x_fp(bp, i, rx_sge_mapping),
7139 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
7140 }
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007141 /* Tx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007142 for_each_queue(bp, i) {
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007143
7144 /* fastpath tx rings: tx_buf tx_desc */
7145 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
7146 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
7147 bnx2x_fp(bp, i, tx_desc_mapping),
Eilon Greensteinca003922009-08-12 22:53:28 -07007148 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007149 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007150 /* end of fastpath */
7151
7152 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007153 sizeof(struct host_def_status_block));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007154
7155 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007156 sizeof(struct bnx2x_slowpath));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007157
Michael Chan37b091b2009-10-10 13:46:55 +00007158#ifdef BCM_CNIC
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007159 BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
7160 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
7161 BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
7162 BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
Michael Chan37b091b2009-10-10 13:46:55 +00007163 BNX2X_PCI_FREE(bp->cnic_sb, bp->cnic_sb_mapping,
7164 sizeof(struct host_status_block));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007165#endif
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07007166 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007167
7168#undef BNX2X_PCI_FREE
7169#undef BNX2X_KFREE
7170}
7171
7172static int bnx2x_alloc_mem(struct bnx2x *bp)
7173{
7174
7175#define BNX2X_PCI_ALLOC(x, y, size) \
7176 do { \
FUJITA Tomonori1a983142010-04-04 01:51:03 +00007177 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007178 if (x == NULL) \
7179 goto alloc_mem_err; \
7180 memset(x, 0, size); \
7181 } while (0)
7182
7183#define BNX2X_ALLOC(x, size) \
7184 do { \
7185 x = vmalloc(size); \
7186 if (x == NULL) \
7187 goto alloc_mem_err; \
7188 memset(x, 0, size); \
7189 } while (0)
7190
7191 int i;
7192
7193 /* fastpath */
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007194 /* Common */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007195 for_each_queue(bp, i) {
7196 bnx2x_fp(bp, i, bp) = bp;
7197
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007198 /* status blocks */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007199 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
7200 &bnx2x_fp(bp, i, status_blk_mapping),
Eilon Greensteinca003922009-08-12 22:53:28 -07007201 sizeof(struct host_status_block));
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007202 }
7203 /* Rx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007204 for_each_queue(bp, i) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007205
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007206 /* fastpath rx rings: rx_buf rx_desc rx_comp */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007207 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
7208 sizeof(struct sw_rx_bd) * NUM_RX_BD);
7209 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
7210 &bnx2x_fp(bp, i, rx_desc_mapping),
7211 sizeof(struct eth_rx_bd) * NUM_RX_BD);
7212
7213 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
7214 &bnx2x_fp(bp, i, rx_comp_mapping),
7215 sizeof(struct eth_fast_path_rx_cqe) *
7216 NUM_RCQ_BD);
7217
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07007218 /* SGE ring */
7219 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
7220 sizeof(struct sw_rx_page) * NUM_RX_SGE);
7221 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
7222 &bnx2x_fp(bp, i, rx_sge_mapping),
7223 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007224 }
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007225 /* Tx */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007226 for_each_queue(bp, i) {
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007227
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007228 /* fastpath tx rings: tx_buf tx_desc */
7229 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
7230 sizeof(struct sw_tx_bd) * NUM_TX_BD);
7231 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
7232 &bnx2x_fp(bp, i, tx_desc_mapping),
Eilon Greensteinca003922009-08-12 22:53:28 -07007233 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007234 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007235 /* end of fastpath */
7236
7237 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7238 sizeof(struct host_def_status_block));
7239
7240 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7241 sizeof(struct bnx2x_slowpath));
7242
Michael Chan37b091b2009-10-10 13:46:55 +00007243#ifdef BCM_CNIC
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007244 BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
7245
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007246 /* allocate searcher T2 table
7247 we allocate 1/4 of alloc num for T2
7248 (which is not entered into the ILT) */
7249 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
7250
Michael Chan37b091b2009-10-10 13:46:55 +00007251 /* Initialize T2 (for 1024 connections) */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007252 for (i = 0; i < 16*1024; i += 64)
Michael Chan37b091b2009-10-10 13:46:55 +00007253 *(u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007254
Michael Chan37b091b2009-10-10 13:46:55 +00007255 /* Timer block array (8*MAX_CONN) phys uncached for now 1024 conns */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007256 BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
7257
7258 /* QM queues (128*MAX_CONN) */
7259 BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
Michael Chan37b091b2009-10-10 13:46:55 +00007260
7261 BNX2X_PCI_ALLOC(bp->cnic_sb, &bp->cnic_sb_mapping,
7262 sizeof(struct host_status_block));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007263#endif
7264
7265 /* Slow path ring */
7266 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7267
7268 return 0;
7269
7270alloc_mem_err:
7271 bnx2x_free_mem(bp);
7272 return -ENOMEM;
7273
7274#undef BNX2X_PCI_ALLOC
7275#undef BNX2X_ALLOC
7276}
7277
7278static void bnx2x_free_tx_skbs(struct bnx2x *bp)
7279{
7280 int i;
7281
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007282 for_each_queue(bp, i) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007283 struct bnx2x_fastpath *fp = &bp->fp[i];
7284
7285 u16 bd_cons = fp->tx_bd_cons;
7286 u16 sw_prod = fp->tx_pkt_prod;
7287 u16 sw_cons = fp->tx_pkt_cons;
7288
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007289 while (sw_cons != sw_prod) {
7290 bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
7291 sw_cons++;
7292 }
7293 }
7294}
7295
7296static void bnx2x_free_rx_skbs(struct bnx2x *bp)
7297{
7298 int i, j;
7299
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007300 for_each_queue(bp, j) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007301 struct bnx2x_fastpath *fp = &bp->fp[j];
7302
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007303 for (i = 0; i < NUM_RX_BD; i++) {
7304 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
7305 struct sk_buff *skb = rx_buf->skb;
7306
7307 if (skb == NULL)
7308 continue;
7309
FUJITA Tomonori1a983142010-04-04 01:51:03 +00007310 dma_unmap_single(&bp->pdev->dev,
7311 dma_unmap_addr(rx_buf, mapping),
7312 bp->rx_buf_size, DMA_FROM_DEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007313
7314 rx_buf->skb = NULL;
7315 dev_kfree_skb(skb);
7316 }
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07007317 if (!fp->disable_tpa)
Eilon Greenstein32626232008-08-13 15:51:07 -07007318 bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
7319 ETH_MAX_AGGREGATION_QUEUES_E1 :
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07007320 ETH_MAX_AGGREGATION_QUEUES_E1H);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007321 }
7322}
7323
7324static void bnx2x_free_skbs(struct bnx2x *bp)
7325{
7326 bnx2x_free_tx_skbs(bp);
7327 bnx2x_free_rx_skbs(bp);
7328}
7329
7330static void bnx2x_free_msix_irqs(struct bnx2x *bp)
7331{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007332 int i, offset = 1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007333
7334 free_irq(bp->msix_table[0].vector, bp->dev);
Eliezer Tamirc14423f2008-02-28 11:49:42 -08007335 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007336 bp->msix_table[0].vector);
7337
Michael Chan37b091b2009-10-10 13:46:55 +00007338#ifdef BCM_CNIC
7339 offset++;
7340#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007341 for_each_queue(bp, i) {
Eliezer Tamirc14423f2008-02-28 11:49:42 -08007342 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq "
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007343 "state %x\n", i, bp->msix_table[i + offset].vector,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007344 bnx2x_fp(bp, i, state));
7345
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007346 free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007347 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007348}
7349
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007350static void bnx2x_free_irq(struct bnx2x *bp, bool disable_only)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007351{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007352 if (bp->flags & USING_MSIX_FLAG) {
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007353 if (!disable_only)
7354 bnx2x_free_msix_irqs(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007355 pci_disable_msix(bp->pdev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007356 bp->flags &= ~USING_MSIX_FLAG;
7357
Eilon Greenstein8badd272009-02-12 08:36:15 +00007358 } else if (bp->flags & USING_MSI_FLAG) {
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007359 if (!disable_only)
7360 free_irq(bp->pdev->irq, bp->dev);
Eilon Greenstein8badd272009-02-12 08:36:15 +00007361 pci_disable_msi(bp->pdev);
7362 bp->flags &= ~USING_MSI_FLAG;
7363
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007364 } else if (!disable_only)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007365 free_irq(bp->pdev->irq, bp->dev);
7366}
7367
7368static int bnx2x_enable_msix(struct bnx2x *bp)
7369{
Eilon Greenstein8badd272009-02-12 08:36:15 +00007370 int i, rc, offset = 1;
7371 int igu_vec = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007372
Eilon Greenstein8badd272009-02-12 08:36:15 +00007373 bp->msix_table[0].entry = igu_vec;
7374 DP(NETIF_MSG_IFUP, "msix_table[0].entry = %d (slowpath)\n", igu_vec);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007375
Michael Chan37b091b2009-10-10 13:46:55 +00007376#ifdef BCM_CNIC
7377 igu_vec = BP_L_ID(bp) + offset;
7378 bp->msix_table[1].entry = igu_vec;
7379 DP(NETIF_MSG_IFUP, "msix_table[1].entry = %d (CNIC)\n", igu_vec);
7380 offset++;
7381#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007382 for_each_queue(bp, i) {
Eilon Greenstein8badd272009-02-12 08:36:15 +00007383 igu_vec = BP_L_ID(bp) + offset + i;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007384 bp->msix_table[i + offset].entry = igu_vec;
7385 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
7386 "(fastpath #%u)\n", i + offset, igu_vec, i);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007387 }
7388
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007389 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007390 BNX2X_NUM_QUEUES(bp) + offset);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007391 if (rc) {
Eilon Greenstein8badd272009-02-12 08:36:15 +00007392 DP(NETIF_MSG_IFUP, "MSI-X is not attainable rc %d\n", rc);
7393 return rc;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007394 }
Eilon Greenstein8badd272009-02-12 08:36:15 +00007395
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007396 bp->flags |= USING_MSIX_FLAG;
7397
7398 return 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007399}
7400
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007401static int bnx2x_req_msix_irqs(struct bnx2x *bp)
7402{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007403 int i, rc, offset = 1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007404
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007405 rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
7406 bp->dev->name, bp->dev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007407 if (rc) {
7408 BNX2X_ERR("request sp irq failed\n");
7409 return -EBUSY;
7410 }
7411
Michael Chan37b091b2009-10-10 13:46:55 +00007412#ifdef BCM_CNIC
7413 offset++;
7414#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007415 for_each_queue(bp, i) {
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007416 struct bnx2x_fastpath *fp = &bp->fp[i];
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007417 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
7418 bp->dev->name, i);
Eilon Greensteinca003922009-08-12 22:53:28 -07007419
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007420 rc = request_irq(bp->msix_table[i + offset].vector,
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007421 bnx2x_msix_fp_int, 0, fp->name, fp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007422 if (rc) {
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007423 BNX2X_ERR("request fp #%d irq failed rc %d\n", i, rc);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007424 bnx2x_free_msix_irqs(bp);
7425 return -EBUSY;
7426 }
7427
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007428 fp->state = BNX2X_FP_STATE_IRQ;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007429 }
7430
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007431 i = BNX2X_NUM_QUEUES(bp);
Joe Perches7995c642010-02-17 15:01:52 +00007432 netdev_info(bp->dev, "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n",
7433 bp->msix_table[0].vector,
7434 0, bp->msix_table[offset].vector,
7435 i - 1, bp->msix_table[offset + i - 1].vector);
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007436
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007437 return 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007438}
7439
Eilon Greenstein8badd272009-02-12 08:36:15 +00007440static int bnx2x_enable_msi(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007441{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007442 int rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007443
Eilon Greenstein8badd272009-02-12 08:36:15 +00007444 rc = pci_enable_msi(bp->pdev);
7445 if (rc) {
7446 DP(NETIF_MSG_IFUP, "MSI is not attainable\n");
7447 return -1;
7448 }
7449 bp->flags |= USING_MSI_FLAG;
7450
7451 return 0;
7452}
7453
7454static int bnx2x_req_irq(struct bnx2x *bp)
7455{
7456 unsigned long flags;
7457 int rc;
7458
7459 if (bp->flags & USING_MSI_FLAG)
7460 flags = 0;
7461 else
7462 flags = IRQF_SHARED;
7463
7464 rc = request_irq(bp->pdev->irq, bnx2x_interrupt, flags,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007465 bp->dev->name, bp->dev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007466 if (!rc)
7467 bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
7468
7469 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007470}
7471
Yitchak Gertner65abd742008-08-25 15:26:24 -07007472static void bnx2x_napi_enable(struct bnx2x *bp)
7473{
7474 int i;
7475
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007476 for_each_queue(bp, i)
Yitchak Gertner65abd742008-08-25 15:26:24 -07007477 napi_enable(&bnx2x_fp(bp, i, napi));
7478}
7479
7480static void bnx2x_napi_disable(struct bnx2x *bp)
7481{
7482 int i;
7483
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007484 for_each_queue(bp, i)
Yitchak Gertner65abd742008-08-25 15:26:24 -07007485 napi_disable(&bnx2x_fp(bp, i, napi));
7486}
7487
7488static void bnx2x_netif_start(struct bnx2x *bp)
7489{
Eilon Greensteine1510702009-07-21 05:47:41 +00007490 int intr_sem;
7491
7492 intr_sem = atomic_dec_and_test(&bp->intr_sem);
7493 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
7494
7495 if (intr_sem) {
Yitchak Gertner65abd742008-08-25 15:26:24 -07007496 if (netif_running(bp->dev)) {
Yitchak Gertner65abd742008-08-25 15:26:24 -07007497 bnx2x_napi_enable(bp);
7498 bnx2x_int_enable(bp);
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007499 if (bp->state == BNX2X_STATE_OPEN)
7500 netif_tx_wake_all_queues(bp->dev);
Yitchak Gertner65abd742008-08-25 15:26:24 -07007501 }
7502 }
7503}
7504
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -07007505static void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
Yitchak Gertner65abd742008-08-25 15:26:24 -07007506{
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -07007507 bnx2x_int_disable_sync(bp, disable_hw);
Eilon Greensteine94d8af2009-01-22 03:37:36 +00007508 bnx2x_napi_disable(bp);
Eilon Greenstein762d5f62009-03-02 07:59:56 +00007509 netif_tx_disable(bp->dev);
Yitchak Gertner65abd742008-08-25 15:26:24 -07007510}
7511
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007512/*
7513 * Init service functions
7514 */
7515
Michael Chane665bfd2009-10-10 13:46:54 +00007516/**
7517 * Sets a MAC in a CAM for a few L2 Clients for E1 chip
7518 *
7519 * @param bp driver descriptor
7520 * @param set set or clear an entry (1 or 0)
7521 * @param mac pointer to a buffer containing a MAC
7522 * @param cl_bit_vec bit vector of clients to register a MAC for
7523 * @param cam_offset offset in a CAM to use
7524 * @param with_bcast set broadcast MAC as well
7525 */
7526static void bnx2x_set_mac_addr_e1_gen(struct bnx2x *bp, int set, u8 *mac,
7527 u32 cl_bit_vec, u8 cam_offset,
7528 u8 with_bcast)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007529{
7530 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007531 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007532
7533 /* CAM allocation
7534 * unicasts 0-31:port0 32-63:port1
7535 * multicast 64-127:port0 128-191:port1
7536 */
Michael Chane665bfd2009-10-10 13:46:54 +00007537 config->hdr.length = 1 + (with_bcast ? 1 : 0);
7538 config->hdr.offset = cam_offset;
7539 config->hdr.client_id = 0xff;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007540 config->hdr.reserved1 = 0;
7541
7542 /* primary MAC */
7543 config->config_table[0].cam_entry.msb_mac_addr =
Michael Chane665bfd2009-10-10 13:46:54 +00007544 swab16(*(u16 *)&mac[0]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007545 config->config_table[0].cam_entry.middle_mac_addr =
Michael Chane665bfd2009-10-10 13:46:54 +00007546 swab16(*(u16 *)&mac[2]);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007547 config->config_table[0].cam_entry.lsb_mac_addr =
Michael Chane665bfd2009-10-10 13:46:54 +00007548 swab16(*(u16 *)&mac[4]);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007549 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
Yitchak Gertner3101c2b2008-08-13 15:52:28 -07007550 if (set)
7551 config->config_table[0].target_table_entry.flags = 0;
7552 else
7553 CAM_INVALIDATE(config->config_table[0]);
Eilon Greensteinca003922009-08-12 22:53:28 -07007554 config->config_table[0].target_table_entry.clients_bit_vector =
Michael Chane665bfd2009-10-10 13:46:54 +00007555 cpu_to_le32(cl_bit_vec);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007556 config->config_table[0].target_table_entry.vlan_id = 0;
7557
Yitchak Gertner3101c2b2008-08-13 15:52:28 -07007558 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
7559 (set ? "setting" : "clearing"),
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007560 config->config_table[0].cam_entry.msb_mac_addr,
7561 config->config_table[0].cam_entry.middle_mac_addr,
7562 config->config_table[0].cam_entry.lsb_mac_addr);
7563
7564 /* broadcast */
Michael Chane665bfd2009-10-10 13:46:54 +00007565 if (with_bcast) {
7566 config->config_table[1].cam_entry.msb_mac_addr =
7567 cpu_to_le16(0xffff);
7568 config->config_table[1].cam_entry.middle_mac_addr =
7569 cpu_to_le16(0xffff);
7570 config->config_table[1].cam_entry.lsb_mac_addr =
7571 cpu_to_le16(0xffff);
7572 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
7573 if (set)
7574 config->config_table[1].target_table_entry.flags =
7575 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
7576 else
7577 CAM_INVALIDATE(config->config_table[1]);
7578 config->config_table[1].target_table_entry.clients_bit_vector =
7579 cpu_to_le32(cl_bit_vec);
7580 config->config_table[1].target_table_entry.vlan_id = 0;
7581 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007582
7583 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
7584 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
7585 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
7586}
7587
Michael Chane665bfd2009-10-10 13:46:54 +00007588/**
7589 * Sets a MAC in a CAM for a few L2 Clients for E1H chip
7590 *
7591 * @param bp driver descriptor
7592 * @param set set or clear an entry (1 or 0)
7593 * @param mac pointer to a buffer containing a MAC
7594 * @param cl_bit_vec bit vector of clients to register a MAC for
7595 * @param cam_offset offset in a CAM to use
7596 */
7597static void bnx2x_set_mac_addr_e1h_gen(struct bnx2x *bp, int set, u8 *mac,
7598 u32 cl_bit_vec, u8 cam_offset)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007599{
7600 struct mac_configuration_cmd_e1h *config =
7601 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
7602
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08007603 config->hdr.length = 1;
Michael Chane665bfd2009-10-10 13:46:54 +00007604 config->hdr.offset = cam_offset;
7605 config->hdr.client_id = 0xff;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007606 config->hdr.reserved1 = 0;
7607
7608 /* primary MAC */
7609 config->config_table[0].msb_mac_addr =
Michael Chane665bfd2009-10-10 13:46:54 +00007610 swab16(*(u16 *)&mac[0]);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007611 config->config_table[0].middle_mac_addr =
Michael Chane665bfd2009-10-10 13:46:54 +00007612 swab16(*(u16 *)&mac[2]);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007613 config->config_table[0].lsb_mac_addr =
Michael Chane665bfd2009-10-10 13:46:54 +00007614 swab16(*(u16 *)&mac[4]);
Eilon Greensteinca003922009-08-12 22:53:28 -07007615 config->config_table[0].clients_bit_vector =
Michael Chane665bfd2009-10-10 13:46:54 +00007616 cpu_to_le32(cl_bit_vec);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007617 config->config_table[0].vlan_id = 0;
7618 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
Yitchak Gertner3101c2b2008-08-13 15:52:28 -07007619 if (set)
7620 config->config_table[0].flags = BP_PORT(bp);
7621 else
7622 config->config_table[0].flags =
7623 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007624
Michael Chane665bfd2009-10-10 13:46:54 +00007625 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID mask %d\n",
Yitchak Gertner3101c2b2008-08-13 15:52:28 -07007626 (set ? "setting" : "clearing"),
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007627 config->config_table[0].msb_mac_addr,
7628 config->config_table[0].middle_mac_addr,
Michael Chane665bfd2009-10-10 13:46:54 +00007629 config->config_table[0].lsb_mac_addr, bp->e1hov, cl_bit_vec);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007630
7631 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
7632 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
7633 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
7634}
7635
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007636static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
7637 int *state_p, int poll)
7638{
7639 /* can take a while if any port is running */
Eilon Greenstein8b3a0f02009-02-12 08:37:23 +00007640 int cnt = 5000;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007641
Eliezer Tamirc14423f2008-02-28 11:49:42 -08007642 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
7643 poll ? "polling" : "waiting", state, idx);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007644
7645 might_sleep();
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007646 while (cnt--) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007647 if (poll) {
7648 bnx2x_rx_int(bp->fp, 10);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007649 /* if index is different from 0
7650 * the reply for some commands will
Yitchak Gertner3101c2b2008-08-13 15:52:28 -07007651 * be on the non default queue
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007652 */
7653 if (idx)
7654 bnx2x_rx_int(&bp->fp[idx], 10);
7655 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007656
Yitchak Gertner3101c2b2008-08-13 15:52:28 -07007657 mb(); /* state is changed by bnx2x_sp_event() */
Eilon Greenstein8b3a0f02009-02-12 08:37:23 +00007658 if (*state_p == state) {
7659#ifdef BNX2X_STOP_ON_ERROR
7660 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
7661#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007662 return 0;
Eilon Greenstein8b3a0f02009-02-12 08:37:23 +00007663 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007664
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007665 msleep(1);
Eilon Greensteine3553b22009-08-12 08:23:31 +00007666
7667 if (bp->panic)
7668 return -EIO;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007669 }
7670
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007671 /* timeout! */
Eliezer Tamir49d66772008-02-28 11:53:13 -08007672 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
7673 poll ? "polling" : "waiting", state, idx);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007674#ifdef BNX2X_STOP_ON_ERROR
7675 bnx2x_panic();
7676#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007677
Eliezer Tamir49d66772008-02-28 11:53:13 -08007678 return -EBUSY;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007679}
7680
Michael Chane665bfd2009-10-10 13:46:54 +00007681static void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set)
7682{
7683 bp->set_mac_pending++;
7684 smp_wmb();
7685
7686 bnx2x_set_mac_addr_e1h_gen(bp, set, bp->dev->dev_addr,
7687 (1 << bp->fp->cl_id), BP_FUNC(bp));
7688
7689 /* Wait for a completion */
7690 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
7691}
7692
7693static void bnx2x_set_eth_mac_addr_e1(struct bnx2x *bp, int set)
7694{
7695 bp->set_mac_pending++;
7696 smp_wmb();
7697
7698 bnx2x_set_mac_addr_e1_gen(bp, set, bp->dev->dev_addr,
7699 (1 << bp->fp->cl_id), (BP_PORT(bp) ? 32 : 0),
7700 1);
7701
7702 /* Wait for a completion */
7703 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
7704}
7705
Michael Chan993ac7b2009-10-10 13:46:56 +00007706#ifdef BCM_CNIC
7707/**
7708 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
7709 * MAC(s). This function will wait until the ramdord completion
7710 * returns.
7711 *
7712 * @param bp driver handle
7713 * @param set set or clear the CAM entry
7714 *
7715 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
7716 */
7717static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
7718{
7719 u32 cl_bit_vec = (1 << BCM_ISCSI_ETH_CL_ID);
7720
7721 bp->set_mac_pending++;
7722 smp_wmb();
7723
7724 /* Send a SET_MAC ramrod */
7725 if (CHIP_IS_E1(bp))
7726 bnx2x_set_mac_addr_e1_gen(bp, set, bp->iscsi_mac,
7727 cl_bit_vec, (BP_PORT(bp) ? 32 : 0) + 2,
7728 1);
7729 else
7730 /* CAM allocation for E1H
7731 * unicasts: by func number
7732 * multicast: 20+FUNC*20, 20 each
7733 */
7734 bnx2x_set_mac_addr_e1h_gen(bp, set, bp->iscsi_mac,
7735 cl_bit_vec, E1H_FUNC_MAX + BP_FUNC(bp));
7736
7737 /* Wait for a completion when setting */
7738 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
7739
7740 return 0;
7741}
7742#endif
7743
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007744static int bnx2x_setup_leading(struct bnx2x *bp)
7745{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007746 int rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007747
Eliezer Tamirc14423f2008-02-28 11:49:42 -08007748 /* reset IGU state */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007749 bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007750
7751 /* SETUP ramrod */
7752 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
7753
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007754 /* Wait for completion */
7755 rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007756
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007757 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007758}
7759
7760static int bnx2x_setup_multi(struct bnx2x *bp, int index)
7761{
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007762 struct bnx2x_fastpath *fp = &bp->fp[index];
7763
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007764 /* reset IGU state */
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007765 bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007766
Eliezer Tamir228241e2008-02-28 11:56:57 -08007767 /* SETUP ramrod */
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007768 fp->state = BNX2X_FP_STATE_OPENING;
7769 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0,
7770 fp->cl_id, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007771
7772 /* Wait for completion */
7773 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
Eilon Greenstein555f6c72009-02-12 08:36:11 +00007774 &(fp->state), 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007775}
7776
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007777static int bnx2x_poll(struct napi_struct *napi, int budget);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007778
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007779static void bnx2x_set_num_queues_msix(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007780{
Eilon Greensteinca003922009-08-12 22:53:28 -07007781
7782 switch (bp->multi_mode) {
7783 case ETH_RSS_MODE_DISABLED:
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007784 bp->num_queues = 1;
Eilon Greensteinca003922009-08-12 22:53:28 -07007785 break;
7786
7787 case ETH_RSS_MODE_REGULAR:
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007788 if (num_queues)
7789 bp->num_queues = min_t(u32, num_queues,
7790 BNX2X_MAX_QUEUES(bp));
Eilon Greensteinca003922009-08-12 22:53:28 -07007791 else
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007792 bp->num_queues = min_t(u32, num_online_cpus(),
7793 BNX2X_MAX_QUEUES(bp));
Eilon Greensteinca003922009-08-12 22:53:28 -07007794 break;
7795
7796
7797 default:
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007798 bp->num_queues = 1;
Eilon Greensteinca003922009-08-12 22:53:28 -07007799 break;
7800 }
Eilon Greensteinca003922009-08-12 22:53:28 -07007801}
7802
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007803static int bnx2x_set_num_queues(struct bnx2x *bp)
Eilon Greensteinca003922009-08-12 22:53:28 -07007804{
7805 int rc = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007806
Eilon Greenstein8badd272009-02-12 08:36:15 +00007807 switch (int_mode) {
7808 case INT_MODE_INTx:
7809 case INT_MODE_MSI:
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007810 bp->num_queues = 1;
Eilon Greensteinca003922009-08-12 22:53:28 -07007811 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
Eilon Greenstein8badd272009-02-12 08:36:15 +00007812 break;
7813
7814 case INT_MODE_MSIX:
7815 default:
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007816 /* Set number of queues according to bp->multi_mode value */
7817 bnx2x_set_num_queues_msix(bp);
Eilon Greensteinca003922009-08-12 22:53:28 -07007818
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007819 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7820 bp->num_queues);
Eilon Greensteinca003922009-08-12 22:53:28 -07007821
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007822 /* if we can't use MSI-X we only need one fp,
7823 * so try to enable MSI-X with the requested number of fp's
7824 * and fallback to MSI or legacy INTx with one fp
7825 */
Eilon Greensteinca003922009-08-12 22:53:28 -07007826 rc = bnx2x_enable_msix(bp);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007827 if (rc)
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007828 /* failed to enable MSI-X */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007829 bp->num_queues = 1;
Eilon Greenstein8badd272009-02-12 08:36:15 +00007830 break;
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007831 }
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007832 bp->dev->real_num_tx_queues = bp->num_queues;
Eilon Greensteinca003922009-08-12 22:53:28 -07007833 return rc;
Eilon Greenstein8badd272009-02-12 08:36:15 +00007834}
7835
Michael Chan993ac7b2009-10-10 13:46:56 +00007836#ifdef BCM_CNIC
7837static int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
7838static void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
7839#endif
Eilon Greenstein8badd272009-02-12 08:36:15 +00007840
7841/* must be called with rtnl_lock */
7842static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
7843{
7844 u32 load_code;
Eilon Greensteinca003922009-08-12 22:53:28 -07007845 int i, rc;
7846
Eilon Greenstein8badd272009-02-12 08:36:15 +00007847#ifdef BNX2X_STOP_ON_ERROR
Eilon Greenstein8badd272009-02-12 08:36:15 +00007848 if (unlikely(bp->panic))
7849 return -EPERM;
7850#endif
7851
7852 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
7853
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007854 rc = bnx2x_set_num_queues(bp);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007855
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007856 if (bnx2x_alloc_mem(bp)) {
7857 bnx2x_free_irq(bp, true);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007858 return -ENOMEM;
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007859 }
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007860
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007861 for_each_queue(bp, i)
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007862 bnx2x_fp(bp, i, disable_tpa) =
7863 ((bp->flags & TPA_ENABLE_FLAG) == 0);
7864
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007865 for_each_queue(bp, i)
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007866 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
7867 bnx2x_poll, 128);
7868
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007869 bnx2x_napi_enable(bp);
7870
7871 if (bp->flags & USING_MSIX_FLAG) {
7872 rc = bnx2x_req_msix_irqs(bp);
7873 if (rc) {
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007874 bnx2x_free_irq(bp, true);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007875 goto load_error1;
7876 }
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007877 } else {
Eilon Greensteinca003922009-08-12 22:53:28 -07007878 /* Fall to INTx if failed to enable MSI-X due to lack of
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00007879 memory (in bnx2x_set_num_queues()) */
Eilon Greenstein8badd272009-02-12 08:36:15 +00007880 if ((rc != -ENOMEM) && (int_mode != INT_MODE_INTx))
7881 bnx2x_enable_msi(bp);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007882 bnx2x_ack_int(bp);
7883 rc = bnx2x_req_irq(bp);
7884 if (rc) {
7885 BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00007886 bnx2x_free_irq(bp, true);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007887 goto load_error1;
7888 }
Eilon Greenstein8badd272009-02-12 08:36:15 +00007889 if (bp->flags & USING_MSI_FLAG) {
7890 bp->dev->irq = bp->pdev->irq;
Joe Perches7995c642010-02-17 15:01:52 +00007891 netdev_info(bp->dev, "using MSI IRQ %d\n",
7892 bp->pdev->irq);
Eilon Greenstein8badd272009-02-12 08:36:15 +00007893 }
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007894 }
7895
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007896 /* Send LOAD_REQUEST command to MCP
7897 Returns the type of LOAD command:
7898 if it is the first port to be initialized
7899 common blocks should be initialized, otherwise - not
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007900 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007901 if (!BP_NOMCP(bp)) {
Eliezer Tamir228241e2008-02-28 11:56:57 -08007902 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
7903 if (!load_code) {
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07007904 BNX2X_ERR("MCP response failure, aborting\n");
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007905 rc = -EBUSY;
7906 goto load_error2;
Eliezer Tamir228241e2008-02-28 11:56:57 -08007907 }
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007908 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) {
7909 rc = -EBUSY; /* other port in diagnostic mode */
7910 goto load_error2;
7911 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007912
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007913 } else {
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07007914 int port = BP_PORT(bp);
7915
Eilon Greensteinf5372252009-02-12 08:38:30 +00007916 DP(NETIF_MSG_IFUP, "NO MCP - load counts %d, %d, %d\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007917 load_count[0], load_count[1], load_count[2]);
7918 load_count[0]++;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07007919 load_count[1 + port]++;
Eilon Greensteinf5372252009-02-12 08:38:30 +00007920 DP(NETIF_MSG_IFUP, "NO MCP - new load counts %d, %d, %d\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007921 load_count[0], load_count[1], load_count[2]);
7922 if (load_count[0] == 1)
7923 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07007924 else if (load_count[1 + port] == 1)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007925 load_code = FW_MSG_CODE_DRV_LOAD_PORT;
7926 else
7927 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007928 }
7929
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007930 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
7931 (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
7932 bp->port.pmf = 1;
7933 else
7934 bp->port.pmf = 0;
7935 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
7936
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007937 /* Initialize HW */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007938 rc = bnx2x_init_hw(bp, load_code);
7939 if (rc) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007940 BNX2X_ERR("HW init failed, aborting\n");
Vladislav Zolotarovf1e1a192010-02-17 02:03:33 +00007941 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
7942 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
7943 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007944 goto load_error2;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007945 }
7946
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007947 /* Setup NIC internals and enable interrupts */
Eilon Greenstein471de712008-08-13 15:49:35 -07007948 bnx2x_nic_init(bp, load_code);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007949
Eilon Greenstein2691d512009-08-12 08:22:08 +00007950 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) &&
7951 (bp->common.shmem2_base))
7952 SHMEM2_WR(bp, dcc_support,
7953 (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
7954 SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
7955
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007956 /* Send LOAD_DONE command to MCP */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007957 if (!BP_NOMCP(bp)) {
Eliezer Tamir228241e2008-02-28 11:56:57 -08007958 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
7959 if (!load_code) {
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07007960 BNX2X_ERR("MCP response failure, aborting\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007961 rc = -EBUSY;
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007962 goto load_error3;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007963 }
7964 }
7965
7966 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
7967
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007968 rc = bnx2x_setup_leading(bp);
7969 if (rc) {
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07007970 BNX2X_ERR("Setup leading failed!\n");
Eilon Greensteine3553b22009-08-12 08:23:31 +00007971#ifndef BNX2X_STOP_ON_ERROR
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007972 goto load_error3;
Eilon Greensteine3553b22009-08-12 08:23:31 +00007973#else
7974 bp->panic = 1;
7975 return -EBUSY;
7976#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007977 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007978
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007979 if (CHIP_IS_E1H(bp))
7980 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
Eilon Greensteinf5372252009-02-12 08:38:30 +00007981 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07007982 bp->flags |= MF_FUNC_DIS;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007983 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007984
Eilon Greensteinca003922009-08-12 22:53:28 -07007985 if (bp->state == BNX2X_STATE_OPEN) {
Michael Chan37b091b2009-10-10 13:46:55 +00007986#ifdef BCM_CNIC
7987 /* Enable Timer scan */
7988 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + BP_PORT(bp)*4, 1);
7989#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007990 for_each_nondefault_queue(bp, i) {
7991 rc = bnx2x_setup_multi(bp, i);
7992 if (rc)
Michael Chan37b091b2009-10-10 13:46:55 +00007993#ifdef BCM_CNIC
7994 goto load_error4;
7995#else
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00007996 goto load_error3;
Michael Chan37b091b2009-10-10 13:46:55 +00007997#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07007998 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007999
Eilon Greensteinca003922009-08-12 22:53:28 -07008000 if (CHIP_IS_E1(bp))
Michael Chane665bfd2009-10-10 13:46:54 +00008001 bnx2x_set_eth_mac_addr_e1(bp, 1);
Eilon Greensteinca003922009-08-12 22:53:28 -07008002 else
Michael Chane665bfd2009-10-10 13:46:54 +00008003 bnx2x_set_eth_mac_addr_e1h(bp, 1);
Michael Chan993ac7b2009-10-10 13:46:56 +00008004#ifdef BCM_CNIC
8005 /* Set iSCSI L2 MAC */
8006 mutex_lock(&bp->cnic_mutex);
8007 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) {
8008 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
8009 bp->cnic_flags |= BNX2X_CNIC_FLAG_MAC_SET;
Michael Chan4a6e47a2009-12-25 17:13:07 -08008010 bnx2x_init_sb(bp, bp->cnic_sb, bp->cnic_sb_mapping,
8011 CNIC_SB_ID(bp));
Michael Chan993ac7b2009-10-10 13:46:56 +00008012 }
8013 mutex_unlock(&bp->cnic_mutex);
8014#endif
Eilon Greensteinca003922009-08-12 22:53:28 -07008015 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008016
8017 if (bp->port.pmf)
Eilon Greensteinb5bf9062009-02-12 08:38:08 +00008018 bnx2x_initial_phy_init(bp, load_mode);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008019
8020 /* Start fast path */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008021 switch (load_mode) {
8022 case LOAD_NORMAL:
Eilon Greensteinca003922009-08-12 22:53:28 -07008023 if (bp->state == BNX2X_STATE_OPEN) {
8024 /* Tx queue should be only reenabled */
8025 netif_tx_wake_all_queues(bp->dev);
8026 }
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00008027 /* Initialize the receive filter. */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008028 bnx2x_set_rx_mode(bp->dev);
8029 break;
8030
8031 case LOAD_OPEN:
Eilon Greenstein555f6c72009-02-12 08:36:11 +00008032 netif_tx_start_all_queues(bp->dev);
Eilon Greensteinca003922009-08-12 22:53:28 -07008033 if (bp->state != BNX2X_STATE_OPEN)
8034 netif_tx_disable(bp->dev);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00008035 /* Initialize the receive filter. */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008036 bnx2x_set_rx_mode(bp->dev);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008037 break;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008038
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008039 case LOAD_DIAG:
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00008040 /* Initialize the receive filter. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008041 bnx2x_set_rx_mode(bp->dev);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008042 bp->state = BNX2X_STATE_DIAG;
8043 break;
8044
8045 default:
8046 break;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008047 }
8048
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008049 if (!bp->port.pmf)
8050 bnx2x__link_status_update(bp);
8051
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008052 /* start the timer */
8053 mod_timer(&bp->timer, jiffies + bp->current_interval);
8054
Michael Chan993ac7b2009-10-10 13:46:56 +00008055#ifdef BCM_CNIC
8056 bnx2x_setup_cnic_irq_info(bp);
8057 if (bp->state == BNX2X_STATE_OPEN)
8058 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
8059#endif
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008060 bnx2x_inc_load_cnt(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008061
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008062 return 0;
8063
Michael Chan37b091b2009-10-10 13:46:55 +00008064#ifdef BCM_CNIC
8065load_error4:
8066 /* Disable Timer scan */
8067 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + BP_PORT(bp)*4, 0);
8068#endif
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00008069load_error3:
8070 bnx2x_int_disable_sync(bp, 1);
8071 if (!BP_NOMCP(bp)) {
8072 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
8073 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
8074 }
8075 bp->port.pmf = 0;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07008076 /* Free SKBs, SGEs, TPA pool and driver internals */
8077 bnx2x_free_skbs(bp);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00008078 for_each_queue(bp, i)
Eilon Greenstein3196a882008-08-13 15:58:49 -07008079 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00008080load_error2:
Yitchak Gertnerd1014632008-08-25 15:25:45 -07008081 /* Release IRQs */
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +00008082 bnx2x_free_irq(bp, false);
Eilon Greenstein2dfe0e12009-01-22 03:37:44 +00008083load_error1:
8084 bnx2x_napi_disable(bp);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00008085 for_each_queue(bp, i)
Eilon Greenstein7cde1c82009-01-22 06:01:25 +00008086 netif_napi_del(&bnx2x_fp(bp, i, napi));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008087 bnx2x_free_mem(bp);
8088
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008089 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008090}
8091
8092static int bnx2x_stop_multi(struct bnx2x *bp, int index)
8093{
Eilon Greenstein555f6c72009-02-12 08:36:11 +00008094 struct bnx2x_fastpath *fp = &bp->fp[index];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008095 int rc;
8096
Eliezer Tamirc14423f2008-02-28 11:49:42 -08008097 /* halt the connection */
Eilon Greenstein555f6c72009-02-12 08:36:11 +00008098 fp->state = BNX2X_FP_STATE_HALTING;
8099 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008100
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008101 /* Wait for completion */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008102 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
Eilon Greenstein555f6c72009-02-12 08:36:11 +00008103 &(fp->state), 1);
Eliezer Tamirc14423f2008-02-28 11:49:42 -08008104 if (rc) /* timeout */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008105 return rc;
8106
8107 /* delete cfc entry */
8108 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
8109
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008110 /* Wait for completion */
8111 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
Eilon Greenstein555f6c72009-02-12 08:36:11 +00008112 &(fp->state), 1);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008113 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008114}
8115
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008116static int bnx2x_stop_leading(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008117{
Eilon Greenstein4781bfa2009-02-12 08:38:17 +00008118 __le16 dsb_sp_prod_idx;
Eliezer Tamirc14423f2008-02-28 11:49:42 -08008119 /* if the other port is handling traffic,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008120 this can take a lot of time */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008121 int cnt = 500;
8122 int rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008123
8124 might_sleep();
8125
8126 /* Send HALT ramrod */
8127 bp->fp[0].state = BNX2X_FP_STATE_HALTING;
Eilon Greenstein0626b892009-02-12 08:38:14 +00008128 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, bp->fp->cl_id, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008129
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008130 /* Wait for completion */
8131 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
8132 &(bp->fp[0].state), 1);
8133 if (rc) /* timeout */
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008134 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008135
Eliezer Tamir49d66772008-02-28 11:53:13 -08008136 dsb_sp_prod_idx = *bp->dsb_sp_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008137
Eliezer Tamir228241e2008-02-28 11:56:57 -08008138 /* Send PORT_DELETE ramrod */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008139 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
8140
Eliezer Tamir49d66772008-02-28 11:53:13 -08008141 /* Wait for completion to arrive on default status block
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008142 we are going to reset the chip anyway
8143 so there is not much to do if this times out
8144 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008145 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008146 if (!cnt) {
8147 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
8148 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
8149 *bp->dsb_sp_prod, dsb_sp_prod_idx);
8150#ifdef BNX2X_STOP_ON_ERROR
8151 bnx2x_panic();
8152#endif
Eilon Greenstein36e552a2009-02-12 08:37:21 +00008153 rc = -EBUSY;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008154 break;
8155 }
8156 cnt--;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008157 msleep(1);
Eilon Greenstein5650d9d2009-01-22 06:01:29 +00008158 rmb(); /* Refresh the dsb_sp_prod */
Eliezer Tamir49d66772008-02-28 11:53:13 -08008159 }
8160 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
8161 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008162
8163 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008164}
8165
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008166static void bnx2x_reset_func(struct bnx2x *bp)
8167{
8168 int port = BP_PORT(bp);
8169 int func = BP_FUNC(bp);
8170 int base, i;
Eliezer Tamir49d66772008-02-28 11:53:13 -08008171
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008172 /* Configure IGU */
8173 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8174 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8175
Michael Chan37b091b2009-10-10 13:46:55 +00008176#ifdef BCM_CNIC
8177 /* Disable Timer scan */
8178 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8179 /*
8180 * Wait for at least 10ms and up to 2 second for the timers scan to
8181 * complete
8182 */
8183 for (i = 0; i < 200; i++) {
8184 msleep(10);
8185 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8186 break;
8187 }
8188#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008189 /* Clear ILT */
8190 base = FUNC_ILT_BASE(func);
8191 for (i = base; i < base + ILT_PER_FUNC; i++)
8192 bnx2x_ilt_wr(bp, i, 0);
8193}
8194
8195static void bnx2x_reset_port(struct bnx2x *bp)
8196{
8197 int port = BP_PORT(bp);
8198 u32 val;
8199
8200 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8201
8202 /* Do not rcv packets to BRB */
8203 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8204 /* Do not direct rcv packets that are not for MCP to the BRB */
8205 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8206 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8207
8208 /* Configure AEU */
8209 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8210
8211 msleep(100);
8212 /* Check for BRB port occupancy */
8213 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8214 if (val)
8215 DP(NETIF_MSG_IFDOWN,
Eilon Greenstein33471622008-08-13 15:59:08 -07008216 "BRB1 is not empty %d blocks are occupied\n", val);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008217
8218 /* TODO: Close Doorbell port? */
8219}
8220
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008221static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
8222{
8223 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
8224 BP_FUNC(bp), reset_code);
8225
8226 switch (reset_code) {
8227 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
8228 bnx2x_reset_port(bp);
8229 bnx2x_reset_func(bp);
8230 bnx2x_reset_common(bp);
8231 break;
8232
8233 case FW_MSG_CODE_DRV_UNLOAD_PORT:
8234 bnx2x_reset_port(bp);
8235 bnx2x_reset_func(bp);
8236 break;
8237
8238 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
8239 bnx2x_reset_func(bp);
8240 break;
8241
8242 default:
8243 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
8244 break;
8245 }
8246}
8247
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008248static void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008249{
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008250 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008251 u32 reset_code = 0;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008252 int i, cnt, rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008253
Eilon Greenstein555f6c72009-02-12 08:36:11 +00008254 /* Wait until tx fastpath tasks complete */
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00008255 for_each_queue(bp, i) {
Eliezer Tamir228241e2008-02-28 11:56:57 -08008256 struct bnx2x_fastpath *fp = &bp->fp[i];
8257
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008258 cnt = 1000;
Vladislav Zolotarove8b5fc52009-01-26 12:36:42 -08008259 while (bnx2x_has_tx_work_unload(fp)) {
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008260
Eilon Greenstein7961f792009-03-02 07:59:31 +00008261 bnx2x_tx_int(fp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008262 if (!cnt) {
8263 BNX2X_ERR("timeout waiting for queue[%d]\n",
8264 i);
8265#ifdef BNX2X_STOP_ON_ERROR
8266 bnx2x_panic();
8267 return -EBUSY;
8268#else
8269 break;
8270#endif
8271 }
8272 cnt--;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008273 msleep(1);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008274 }
Eliezer Tamir228241e2008-02-28 11:56:57 -08008275 }
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008276 /* Give HW time to discard old tx messages */
8277 msleep(1);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008278
Yitchak Gertner65abd742008-08-25 15:26:24 -07008279 if (CHIP_IS_E1(bp)) {
8280 struct mac_configuration_cmd *config =
8281 bnx2x_sp(bp, mcast_config);
8282
Michael Chane665bfd2009-10-10 13:46:54 +00008283 bnx2x_set_eth_mac_addr_e1(bp, 0);
Yitchak Gertner65abd742008-08-25 15:26:24 -07008284
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08008285 for (i = 0; i < config->hdr.length; i++)
Yitchak Gertner65abd742008-08-25 15:26:24 -07008286 CAM_INVALIDATE(config->config_table[i]);
8287
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08008288 config->hdr.length = i;
Yitchak Gertner65abd742008-08-25 15:26:24 -07008289 if (CHIP_REV_IS_SLOW(bp))
8290 config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
8291 else
8292 config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
Eilon Greenstein0626b892009-02-12 08:38:14 +00008293 config->hdr.client_id = bp->fp->cl_id;
Yitchak Gertner65abd742008-08-25 15:26:24 -07008294 config->hdr.reserved1 = 0;
8295
Michael Chane665bfd2009-10-10 13:46:54 +00008296 bp->set_mac_pending++;
8297 smp_wmb();
8298
Yitchak Gertner65abd742008-08-25 15:26:24 -07008299 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
8300 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
8301 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
8302
8303 } else { /* E1H */
8304 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8305
Michael Chane665bfd2009-10-10 13:46:54 +00008306 bnx2x_set_eth_mac_addr_e1h(bp, 0);
Yitchak Gertner65abd742008-08-25 15:26:24 -07008307
8308 for (i = 0; i < MC_HASH_SIZE; i++)
8309 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
Eilon Greenstein7d0446c2009-07-29 00:20:10 +00008310
8311 REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
Yitchak Gertner65abd742008-08-25 15:26:24 -07008312 }
Michael Chan993ac7b2009-10-10 13:46:56 +00008313#ifdef BCM_CNIC
8314 /* Clear iSCSI L2 MAC */
8315 mutex_lock(&bp->cnic_mutex);
8316 if (bp->cnic_flags & BNX2X_CNIC_FLAG_MAC_SET) {
8317 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
8318 bp->cnic_flags &= ~BNX2X_CNIC_FLAG_MAC_SET;
8319 }
8320 mutex_unlock(&bp->cnic_mutex);
8321#endif
Yitchak Gertner65abd742008-08-25 15:26:24 -07008322
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008323 if (unload_mode == UNLOAD_NORMAL)
8324 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
Eliezer Tamir228241e2008-02-28 11:56:57 -08008325
Eilon Greenstein7d0446c2009-07-29 00:20:10 +00008326 else if (bp->flags & NO_WOL_FLAG)
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008327 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008328
Eilon Greenstein7d0446c2009-07-29 00:20:10 +00008329 else if (bp->wol) {
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008330 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008331 u8 *mac_addr = bp->dev->dev_addr;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008332 u32 val;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008333 /* The mac address is written to entries 1-4 to
8334 preserve entry 0 which is used by the PMF */
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008335 u8 entry = (BP_E1HVN(bp) + 1)*8;
8336
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008337 val = (mac_addr[0] << 8) | mac_addr[1];
Eilon Greenstein3196a882008-08-13 15:58:49 -07008338 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008339
8340 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8341 (mac_addr[4] << 8) | mac_addr[5];
Eilon Greenstein3196a882008-08-13 15:58:49 -07008342 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008343
8344 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
Eliezer Tamir228241e2008-02-28 11:56:57 -08008345
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008346 } else
8347 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8348
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008349 /* Close multi and leading connections
8350 Completions for ramrods are collected in a synchronous way */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008351 for_each_nondefault_queue(bp, i)
8352 if (bnx2x_stop_multi(bp, i))
Eliezer Tamir228241e2008-02-28 11:56:57 -08008353 goto unload_error;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008354
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008355 rc = bnx2x_stop_leading(bp);
8356 if (rc) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008357 BNX2X_ERR("Stop leading failed!\n");
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008358#ifdef BNX2X_STOP_ON_ERROR
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008359 return -EBUSY;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008360#else
8361 goto unload_error;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008362#endif
Eliezer Tamir228241e2008-02-28 11:56:57 -08008363 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008364
Eliezer Tamir228241e2008-02-28 11:56:57 -08008365unload_error:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008366 if (!BP_NOMCP(bp))
Eliezer Tamir228241e2008-02-28 11:56:57 -08008367 reset_code = bnx2x_fw_command(bp, reset_code);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008368 else {
Eilon Greensteinf5372252009-02-12 08:38:30 +00008369 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts %d, %d, %d\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008370 load_count[0], load_count[1], load_count[2]);
8371 load_count[0]--;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008372 load_count[1 + port]--;
Eilon Greensteinf5372252009-02-12 08:38:30 +00008373 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts %d, %d, %d\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008374 load_count[0], load_count[1], load_count[2]);
8375 if (load_count[0] == 0)
8376 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07008377 else if (load_count[1 + port] == 0)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008378 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8379 else
8380 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8381 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008382
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008383 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
8384 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
8385 bnx2x__link_reset(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008386
8387 /* Reset the chip */
Eliezer Tamir228241e2008-02-28 11:56:57 -08008388 bnx2x_reset_chip(bp, reset_code);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008389
8390 /* Report UNLOAD_DONE to MCP */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008391 if (!BP_NOMCP(bp))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008392 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
Eilon Greenstein356e2382009-02-12 08:38:32 +00008393
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008394}
8395
8396static inline void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8397{
8398 u32 val;
8399
8400 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
8401
8402 if (CHIP_IS_E1(bp)) {
8403 int port = BP_PORT(bp);
8404 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8405 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8406
8407 val = REG_RD(bp, addr);
8408 val &= ~(0x300);
8409 REG_WR(bp, addr, val);
8410 } else if (CHIP_IS_E1H(bp)) {
8411 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8412 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8413 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8414 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8415 }
8416}
8417
8418/* must be called with rtnl_lock */
8419static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
8420{
8421 int i;
8422
8423 if (bp->state == BNX2X_STATE_CLOSED) {
8424 /* Interface has been removed - nothing to recover */
8425 bp->recovery_state = BNX2X_RECOVERY_DONE;
8426 bp->is_leader = 0;
8427 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
8428 smp_wmb();
8429
8430 return -EINVAL;
8431 }
8432
8433#ifdef BCM_CNIC
8434 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
8435#endif
8436 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
8437
8438 /* Set "drop all" */
8439 bp->rx_mode = BNX2X_RX_MODE_NONE;
8440 bnx2x_set_storm_rx_mode(bp);
8441
8442 /* Disable HW interrupts, NAPI and Tx */
8443 bnx2x_netif_stop(bp, 1);
8444
8445 del_timer_sync(&bp->timer);
8446 SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb,
8447 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
8448 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8449
8450 /* Release IRQs */
8451 bnx2x_free_irq(bp, false);
8452
8453 /* Cleanup the chip if needed */
8454 if (unload_mode != UNLOAD_RECOVERY)
8455 bnx2x_chip_cleanup(bp, unload_mode);
8456
Eilon Greenstein9a035442008-11-03 16:45:55 -08008457 bp->port.pmf = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008458
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07008459 /* Free SKBs, SGEs, TPA pool and driver internals */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008460 bnx2x_free_skbs(bp);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00008461 for_each_queue(bp, i)
Eilon Greenstein3196a882008-08-13 15:58:49 -07008462 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +00008463 for_each_queue(bp, i)
Eilon Greenstein7cde1c82009-01-22 06:01:25 +00008464 netif_napi_del(&bnx2x_fp(bp, i, napi));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008465 bnx2x_free_mem(bp);
8466
8467 bp->state = BNX2X_STATE_CLOSED;
Eliezer Tamir228241e2008-02-28 11:56:57 -08008468
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008469 netif_carrier_off(bp->dev);
8470
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008471 /* The last driver must disable a "close the gate" if there is no
8472 * parity attention or "process kill" pending.
8473 */
8474 if ((!bnx2x_dec_load_cnt(bp)) && (!bnx2x_chk_parity_attn(bp)) &&
8475 bnx2x_reset_is_done(bp))
8476 bnx2x_disable_close_the_gate(bp);
8477
8478 /* Reset MCP mail box sequence if there is on going recovery */
8479 if (unload_mode == UNLOAD_RECOVERY)
8480 bp->fw_seq = 0;
8481
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008482 return 0;
8483}
8484
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008485/* Close gates #2, #3 and #4: */
8486static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8487{
8488 u32 val, addr;
8489
8490 /* Gates #2 and #4a are closed/opened for "not E1" only */
8491 if (!CHIP_IS_E1(bp)) {
8492 /* #4 */
8493 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
8494 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
8495 close ? (val | 0x1) : (val & (~(u32)1)));
8496 /* #2 */
8497 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
8498 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
8499 close ? (val | 0x1) : (val & (~(u32)1)));
8500 }
8501
8502 /* #3 */
8503 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
8504 val = REG_RD(bp, addr);
8505 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
8506
8507 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
8508 close ? "closing" : "opening");
8509 mmiowb();
8510}
8511
8512#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8513
8514static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8515{
8516 /* Do some magic... */
8517 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8518 *magic_val = val & SHARED_MF_CLP_MAGIC;
8519 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8520}
8521
8522/* Restore the value of the `magic' bit.
8523 *
8524 * @param pdev Device handle.
8525 * @param magic_val Old value of the `magic' bit.
8526 */
8527static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8528{
8529 /* Restore the `magic' bit value... */
8530 /* u32 val = SHMEM_RD(bp, mf_cfg.shared_mf_config.clp_mb);
8531 SHMEM_WR(bp, mf_cfg.shared_mf_config.clp_mb,
8532 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); */
8533 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8534 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8535 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8536}
8537
8538/* Prepares for MCP reset: takes care of CLP configurations.
8539 *
8540 * @param bp
8541 * @param magic_val Old value of 'magic' bit.
8542 */
8543static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8544{
8545 u32 shmem;
8546 u32 validity_offset;
8547
8548 DP(NETIF_MSG_HW, "Starting\n");
8549
8550 /* Set `magic' bit in order to save MF config */
8551 if (!CHIP_IS_E1(bp))
8552 bnx2x_clp_reset_prep(bp, magic_val);
8553
8554 /* Get shmem offset */
8555 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8556 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8557
8558 /* Clear validity map flags */
8559 if (shmem > 0)
8560 REG_WR(bp, shmem + validity_offset, 0);
8561}
8562
8563#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8564#define MCP_ONE_TIMEOUT 100 /* 100 ms */
8565
8566/* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
8567 * depending on the HW type.
8568 *
8569 * @param bp
8570 */
8571static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
8572{
8573 /* special handling for emulation and FPGA,
8574 wait 10 times longer */
8575 if (CHIP_REV_IS_SLOW(bp))
8576 msleep(MCP_ONE_TIMEOUT*10);
8577 else
8578 msleep(MCP_ONE_TIMEOUT);
8579}
8580
8581static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8582{
8583 u32 shmem, cnt, validity_offset, val;
8584 int rc = 0;
8585
8586 msleep(100);
8587
8588 /* Get shmem offset */
8589 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8590 if (shmem == 0) {
8591 BNX2X_ERR("Shmem 0 return failure\n");
8592 rc = -ENOTTY;
8593 goto exit_lbl;
8594 }
8595
8596 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8597
8598 /* Wait for MCP to come up */
8599 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
8600 /* TBD: its best to check validity map of last port.
8601 * currently checks on port 0.
8602 */
8603 val = REG_RD(bp, shmem + validity_offset);
8604 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
8605 shmem + validity_offset, val);
8606
8607 /* check that shared memory is valid. */
8608 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
8609 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
8610 break;
8611
8612 bnx2x_mcp_wait_one(bp);
8613 }
8614
8615 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
8616
8617 /* Check that shared memory is valid. This indicates that MCP is up. */
8618 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8619 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8620 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
8621 rc = -ENOTTY;
8622 goto exit_lbl;
8623 }
8624
8625exit_lbl:
8626 /* Restore the `magic' bit value */
8627 if (!CHIP_IS_E1(bp))
8628 bnx2x_clp_reset_done(bp, magic_val);
8629
8630 return rc;
8631}
8632
8633static void bnx2x_pxp_prep(struct bnx2x *bp)
8634{
8635 if (!CHIP_IS_E1(bp)) {
8636 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8637 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8638 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
8639 mmiowb();
8640 }
8641}
8642
8643/*
8644 * Reset the whole chip except for:
8645 * - PCIE core
8646 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8647 * one reset bit)
8648 * - IGU
8649 * - MISC (including AEU)
8650 * - GRC
8651 * - RBCN, RBCP
8652 */
8653static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
8654{
8655 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8656
8657 not_reset_mask1 =
8658 MISC_REGISTERS_RESET_REG_1_RST_HC |
8659 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8660 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8661
8662 not_reset_mask2 =
8663 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
8664 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8665 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8666 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8667 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8668 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8669 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8670 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
8671
8672 reset_mask1 = 0xffffffff;
8673
8674 if (CHIP_IS_E1(bp))
8675 reset_mask2 = 0xffff;
8676 else
8677 reset_mask2 = 0x1ffff;
8678
8679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8680 reset_mask1 & (~not_reset_mask1));
8681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8682 reset_mask2 & (~not_reset_mask2));
8683
8684 barrier();
8685 mmiowb();
8686
8687 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8688 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
8689 mmiowb();
8690}
8691
8692static int bnx2x_process_kill(struct bnx2x *bp)
8693{
8694 int cnt = 1000;
8695 u32 val = 0;
8696 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8697
8698
8699 /* Empty the Tetris buffer, wait for 1s */
8700 do {
8701 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8702 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8703 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8704 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8705 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8706 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8707 ((port_is_idle_0 & 0x1) == 0x1) &&
8708 ((port_is_idle_1 & 0x1) == 0x1) &&
8709 (pgl_exp_rom2 == 0xffffffff))
8710 break;
8711 msleep(1);
8712 } while (cnt-- > 0);
8713
8714 if (cnt <= 0) {
8715 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8716 " are still"
8717 " outstanding read requests after 1s!\n");
8718 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8719 " port_is_idle_0=0x%08x,"
8720 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8721 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8722 pgl_exp_rom2);
8723 return -EAGAIN;
8724 }
8725
8726 barrier();
8727
8728 /* Close gates #2, #3 and #4 */
8729 bnx2x_set_234_gates(bp, true);
8730
8731 /* TBD: Indicate that "process kill" is in progress to MCP */
8732
8733 /* Clear "unprepared" bit */
8734 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8735 barrier();
8736
8737 /* Make sure all is written to the chip before the reset */
8738 mmiowb();
8739
8740 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8741 * PSWHST, GRC and PSWRD Tetris buffer.
8742 */
8743 msleep(1);
8744
8745 /* Prepare to chip reset: */
8746 /* MCP */
8747 bnx2x_reset_mcp_prep(bp, &val);
8748
8749 /* PXP */
8750 bnx2x_pxp_prep(bp);
8751 barrier();
8752
8753 /* reset the chip */
8754 bnx2x_process_kill_chip_reset(bp);
8755 barrier();
8756
8757 /* Recover after reset: */
8758 /* MCP */
8759 if (bnx2x_reset_mcp_comp(bp, val))
8760 return -EAGAIN;
8761
8762 /* PXP */
8763 bnx2x_pxp_prep(bp);
8764
8765 /* Open the gates #2, #3 and #4 */
8766 bnx2x_set_234_gates(bp, false);
8767
8768 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8769 * reset state, re-enable attentions. */
8770
8771 return 0;
8772}
8773
8774static int bnx2x_leader_reset(struct bnx2x *bp)
8775{
8776 int rc = 0;
8777 /* Try to recover after the failure */
8778 if (bnx2x_process_kill(bp)) {
8779 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
8780 bp->dev->name);
8781 rc = -EAGAIN;
8782 goto exit_leader_reset;
8783 }
8784
8785 /* Clear "reset is in progress" bit and update the driver state */
8786 bnx2x_set_reset_done(bp);
8787 bp->recovery_state = BNX2X_RECOVERY_DONE;
8788
8789exit_leader_reset:
8790 bp->is_leader = 0;
8791 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
8792 smp_wmb();
8793 return rc;
8794}
8795
8796static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
8797
8798/* Assumption: runs under rtnl lock. This together with the fact
8799 * that it's called only from bnx2x_reset_task() ensure that it
8800 * will never be called when netif_running(bp->dev) is false.
8801 */
8802static void bnx2x_parity_recover(struct bnx2x *bp)
8803{
8804 DP(NETIF_MSG_HW, "Handling parity\n");
8805 while (1) {
8806 switch (bp->recovery_state) {
8807 case BNX2X_RECOVERY_INIT:
8808 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8809 /* Try to get a LEADER_LOCK HW lock */
8810 if (bnx2x_trylock_hw_lock(bp,
8811 HW_LOCK_RESOURCE_RESERVED_08))
8812 bp->is_leader = 1;
8813
8814 /* Stop the driver */
8815 /* If interface has been removed - break */
8816 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8817 return;
8818
8819 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8820 /* Ensure "is_leader" and "recovery_state"
8821 * update values are seen on other CPUs
8822 */
8823 smp_wmb();
8824 break;
8825
8826 case BNX2X_RECOVERY_WAIT:
8827 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8828 if (bp->is_leader) {
8829 u32 load_counter = bnx2x_get_load_cnt(bp);
8830 if (load_counter) {
8831 /* Wait until all other functions get
8832 * down.
8833 */
8834 schedule_delayed_work(&bp->reset_task,
8835 HZ/10);
8836 return;
8837 } else {
8838 /* If all other functions got down -
8839 * try to bring the chip back to
8840 * normal. In any case it's an exit
8841 * point for a leader.
8842 */
8843 if (bnx2x_leader_reset(bp) ||
8844 bnx2x_nic_load(bp, LOAD_NORMAL)) {
8845 printk(KERN_ERR"%s: Recovery "
8846 "has failed. Power cycle is "
8847 "needed.\n", bp->dev->name);
8848 /* Disconnect this device */
8849 netif_device_detach(bp->dev);
8850 /* Block ifup for all function
8851 * of this ASIC until
8852 * "process kill" or power
8853 * cycle.
8854 */
8855 bnx2x_set_reset_in_progress(bp);
8856 /* Shut down the power */
8857 bnx2x_set_power_state(bp,
8858 PCI_D3hot);
8859 return;
8860 }
8861
8862 return;
8863 }
8864 } else { /* non-leader */
8865 if (!bnx2x_reset_is_done(bp)) {
8866 /* Try to get a LEADER_LOCK HW lock as
8867 * long as a former leader may have
8868 * been unloaded by the user or
8869 * released a leadership by another
8870 * reason.
8871 */
8872 if (bnx2x_trylock_hw_lock(bp,
8873 HW_LOCK_RESOURCE_RESERVED_08)) {
8874 /* I'm a leader now! Restart a
8875 * switch case.
8876 */
8877 bp->is_leader = 1;
8878 break;
8879 }
8880
8881 schedule_delayed_work(&bp->reset_task,
8882 HZ/10);
8883 return;
8884
8885 } else { /* A leader has completed
8886 * the "process kill". It's an exit
8887 * point for a non-leader.
8888 */
8889 bnx2x_nic_load(bp, LOAD_NORMAL);
8890 bp->recovery_state =
8891 BNX2X_RECOVERY_DONE;
8892 smp_wmb();
8893 return;
8894 }
8895 }
8896 default:
8897 return;
8898 }
8899 }
8900}
8901
8902/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8903 * scheduled on a general queue in order to prevent a dead lock.
8904 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008905static void bnx2x_reset_task(struct work_struct *work)
8906{
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008907 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008908
8909#ifdef BNX2X_STOP_ON_ERROR
8910 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
8911 " so reset not done to allow debug dump,\n"
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008912 KERN_ERR " you will need to reboot when done\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008913 return;
8914#endif
8915
8916 rtnl_lock();
8917
8918 if (!netif_running(bp->dev))
8919 goto reset_task_exit;
8920
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00008921 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
8922 bnx2x_parity_recover(bp);
8923 else {
8924 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8925 bnx2x_nic_load(bp, LOAD_NORMAL);
8926 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008927
8928reset_task_exit:
8929 rtnl_unlock();
8930}
8931
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008932/* end of nic load/unload */
8933
8934/* ethtool_ops */
8935
8936/*
8937 * Init service functions
8938 */
8939
Eilon Greensteinf1ef27e2009-02-12 08:36:23 +00008940static inline u32 bnx2x_get_pretend_reg(struct bnx2x *bp, int func)
8941{
8942 switch (func) {
8943 case 0: return PXP2_REG_PGL_PRETEND_FUNC_F0;
8944 case 1: return PXP2_REG_PGL_PRETEND_FUNC_F1;
8945 case 2: return PXP2_REG_PGL_PRETEND_FUNC_F2;
8946 case 3: return PXP2_REG_PGL_PRETEND_FUNC_F3;
8947 case 4: return PXP2_REG_PGL_PRETEND_FUNC_F4;
8948 case 5: return PXP2_REG_PGL_PRETEND_FUNC_F5;
8949 case 6: return PXP2_REG_PGL_PRETEND_FUNC_F6;
8950 case 7: return PXP2_REG_PGL_PRETEND_FUNC_F7;
8951 default:
8952 BNX2X_ERR("Unsupported function index: %d\n", func);
8953 return (u32)(-1);
8954 }
8955}
8956
8957static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func)
8958{
8959 u32 reg = bnx2x_get_pretend_reg(bp, orig_func), new_val;
8960
8961 /* Flush all outstanding writes */
8962 mmiowb();
8963
8964 /* Pretend to be function 0 */
8965 REG_WR(bp, reg, 0);
8966 /* Flush the GRC transaction (in the chip) */
8967 new_val = REG_RD(bp, reg);
8968 if (new_val != 0) {
8969 BNX2X_ERR("Hmmm... Pretend register wasn't updated: (0,%d)!\n",
8970 new_val);
8971 BUG();
8972 }
8973
8974 /* From now we are in the "like-E1" mode */
8975 bnx2x_int_disable(bp);
8976
8977 /* Flush all outstanding writes */
8978 mmiowb();
8979
8980 /* Restore the original funtion settings */
8981 REG_WR(bp, reg, orig_func);
8982 new_val = REG_RD(bp, reg);
8983 if (new_val != orig_func) {
8984 BNX2X_ERR("Hmmm... Pretend register wasn't updated: (%d,%d)!\n",
8985 orig_func, new_val);
8986 BUG();
8987 }
8988}
8989
8990static inline void bnx2x_undi_int_disable(struct bnx2x *bp, int func)
8991{
8992 if (CHIP_IS_E1H(bp))
8993 bnx2x_undi_int_disable_e1h(bp, func);
8994 else
8995 bnx2x_int_disable(bp);
8996}
8997
Eilon Greenstein34f80b02008-06-23 20:33:01 -07008998static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02008999{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009000 u32 val;
9001
9002 /* Check if there is any driver already loaded */
9003 val = REG_RD(bp, MISC_REG_UNPREPARED);
9004 if (val == 0x1) {
9005 /* Check if it is the UNDI driver
9006 * UNDI driver initializes CID offset for normal bell to 0x7
9007 */
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07009008 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009009 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9010 if (val == 0x7) {
9011 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009012 /* save our func */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009013 int func = BP_FUNC(bp);
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009014 u32 swap_en;
9015 u32 swap_val;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009016
Eilon Greensteinb4661732009-01-14 06:43:56 +00009017 /* clear the UNDI indication */
9018 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9019
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009020 BNX2X_DEV_INFO("UNDI is active! reset device\n");
9021
9022 /* try unload UNDI on port 0 */
9023 bp->func = 0;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009024 bp->fw_seq =
9025 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
9026 DRV_MSG_SEQ_NUMBER_MASK);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009027 reset_code = bnx2x_fw_command(bp, reset_code);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009028
9029 /* if UNDI is loaded on the other port */
9030 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9031
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009032 /* send "DONE" for previous unload */
9033 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
9034
9035 /* unload UNDI on port 1 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009036 bp->func = 1;
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009037 bp->fw_seq =
9038 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
9039 DRV_MSG_SEQ_NUMBER_MASK);
9040 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009041
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009042 bnx2x_fw_command(bp, reset_code);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009043 }
9044
Eilon Greensteinb4661732009-01-14 06:43:56 +00009045 /* now it's safe to release the lock */
9046 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
9047
Eilon Greensteinf1ef27e2009-02-12 08:36:23 +00009048 bnx2x_undi_int_disable(bp, func);
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009049
9050 /* close input traffic and wait for it */
9051 /* Do not rcv packets to BRB */
9052 REG_WR(bp,
9053 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
9054 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
9055 /* Do not direct rcv packets that are not for MCP to
9056 * the BRB */
9057 REG_WR(bp,
9058 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
9059 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9060 /* clear AEU */
9061 REG_WR(bp,
9062 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9063 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
9064 msleep(10);
9065
9066 /* save NIG port swap info */
9067 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9068 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009069 /* reset device */
9070 REG_WR(bp,
9071 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009072 0xd3ffffff);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009073 REG_WR(bp,
9074 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9075 0x1403);
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009076 /* take the NIG out of reset and restore swap values */
9077 REG_WR(bp,
9078 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
9079 MISC_REGISTERS_RESET_REG_1_RST_NIG);
9080 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
9081 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
9082
9083 /* send unload done to the MCP */
9084 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
9085
9086 /* restore our func and fw_seq */
9087 bp->func = func;
9088 bp->fw_seq =
9089 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
9090 DRV_MSG_SEQ_NUMBER_MASK);
Eilon Greensteinb4661732009-01-14 06:43:56 +00009091
9092 } else
9093 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009094 }
9095}
9096
9097static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9098{
9099 u32 val, val2, val3, val4, id;
Eilon Greenstein72ce58c2008-08-13 15:52:46 -07009100 u16 pmc;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009101
9102 /* Get the chip revision id and number. */
9103 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9104 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9105 id = ((val & 0xffff) << 16);
9106 val = REG_RD(bp, MISC_REG_CHIP_REV);
9107 id |= ((val & 0xf) << 12);
9108 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9109 id |= ((val & 0xff) << 4);
Eilon Greenstein5a40e082009-01-14 06:44:04 +00009110 val = REG_RD(bp, MISC_REG_BOND_ID);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009111 id |= (val & 0xf);
9112 bp->common.chip_id = id;
9113 bp->link_params.chip_id = bp->common.chip_id;
9114 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9115
Eilon Greenstein1c063282009-02-12 08:36:43 +00009116 val = (REG_RD(bp, 0x2874) & 0x55);
9117 if ((bp->common.chip_id & 0x1) ||
9118 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9119 bp->flags |= ONE_PORT_FLAG;
9120 BNX2X_DEV_INFO("single port device\n");
9121 }
9122
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009123 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9124 bp->common.flash_size = (NVRAM_1MB_SIZE <<
9125 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9126 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9127 bp->common.flash_size, bp->common.flash_size);
9128
9129 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
Eilon Greenstein2691d512009-08-12 08:22:08 +00009130 bp->common.shmem2_base = REG_RD(bp, MISC_REG_GENERIC_CR_0);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009131 bp->link_params.shmem_base = bp->common.shmem_base;
Eilon Greenstein2691d512009-08-12 08:22:08 +00009132 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9133 bp->common.shmem_base, bp->common.shmem2_base);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009134
9135 if (!bp->common.shmem_base ||
9136 (bp->common.shmem_base < 0xA0000) ||
9137 (bp->common.shmem_base >= 0xC0000)) {
9138 BNX2X_DEV_INFO("MCP not active\n");
9139 bp->flags |= NO_MCP_FLAG;
9140 return;
9141 }
9142
9143 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9144 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9145 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9146 BNX2X_ERR("BAD MCP validity signature\n");
9147
9148 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
Eilon Greenstein35b19ba2009-02-12 08:36:47 +00009149 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009150
9151 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9152 SHARED_HW_CFG_LED_MODE_MASK) >>
9153 SHARED_HW_CFG_LED_MODE_SHIFT);
9154
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00009155 bp->link_params.feature_config_flags = 0;
9156 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9157 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9158 bp->link_params.feature_config_flags |=
9159 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9160 else
9161 bp->link_params.feature_config_flags &=
9162 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9163
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009164 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9165 bp->common.bc_ver = val;
9166 BNX2X_DEV_INFO("bc_ver %X\n", val);
9167 if (val < BNX2X_BC_VER) {
9168 /* for now only warn
9169 * later we might need to enforce this */
9170 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
9171 " please upgrade BC\n", BNX2X_BC_VER, val);
9172 }
Eilon Greenstein4d295db2009-07-21 05:47:47 +00009173 bp->link_params.feature_config_flags |=
9174 (val >= REQ_BC_VER_4_VRFY_OPT_MDL) ?
9175 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
Eilon Greenstein72ce58c2008-08-13 15:52:46 -07009176
9177 if (BP_E1HVN(bp) == 0) {
9178 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9179 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9180 } else {
9181 /* no WOL capability for E1HVN != 0 */
9182 bp->flags |= NO_WOL_FLAG;
9183 }
9184 BNX2X_DEV_INFO("%sWoL capable\n",
Eilon Greensteinf5372252009-02-12 08:38:30 +00009185 (bp->flags & NO_WOL_FLAG) ? "not " : "");
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009186
9187 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9188 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9189 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9190 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9191
Joe Perches7995c642010-02-17 15:01:52 +00009192 pr_info("part number %X-%X-%X-%X\n", val, val2, val3, val4);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009193}
9194
9195static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9196 u32 switch_cfg)
9197{
9198 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009199 u32 ext_phy_type;
9200
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009201 switch (switch_cfg) {
9202 case SWITCH_CFG_1G:
9203 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
9204
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009205 ext_phy_type =
9206 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009207 switch (ext_phy_type) {
9208 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
9209 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
9210 ext_phy_type);
9211
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009212 bp->port.supported |= (SUPPORTED_10baseT_Half |
9213 SUPPORTED_10baseT_Full |
9214 SUPPORTED_100baseT_Half |
9215 SUPPORTED_100baseT_Full |
9216 SUPPORTED_1000baseT_Full |
9217 SUPPORTED_2500baseX_Full |
9218 SUPPORTED_TP |
9219 SUPPORTED_FIBRE |
9220 SUPPORTED_Autoneg |
9221 SUPPORTED_Pause |
9222 SUPPORTED_Asym_Pause);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009223 break;
9224
9225 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
9226 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
9227 ext_phy_type);
9228
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009229 bp->port.supported |= (SUPPORTED_10baseT_Half |
9230 SUPPORTED_10baseT_Full |
9231 SUPPORTED_100baseT_Half |
9232 SUPPORTED_100baseT_Full |
9233 SUPPORTED_1000baseT_Full |
9234 SUPPORTED_TP |
9235 SUPPORTED_FIBRE |
9236 SUPPORTED_Autoneg |
9237 SUPPORTED_Pause |
9238 SUPPORTED_Asym_Pause);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009239 break;
9240
9241 default:
9242 BNX2X_ERR("NVRAM config error. "
9243 "BAD SerDes ext_phy_config 0x%x\n",
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009244 bp->link_params.ext_phy_config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009245 return;
9246 }
9247
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009248 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
9249 port*0x10);
9250 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009251 break;
9252
9253 case SWITCH_CFG_10G:
9254 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
9255
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009256 ext_phy_type =
9257 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009258 switch (ext_phy_type) {
9259 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9260 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
9261 ext_phy_type);
9262
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009263 bp->port.supported |= (SUPPORTED_10baseT_Half |
9264 SUPPORTED_10baseT_Full |
9265 SUPPORTED_100baseT_Half |
9266 SUPPORTED_100baseT_Full |
9267 SUPPORTED_1000baseT_Full |
9268 SUPPORTED_2500baseX_Full |
9269 SUPPORTED_10000baseT_Full |
9270 SUPPORTED_TP |
9271 SUPPORTED_FIBRE |
9272 SUPPORTED_Autoneg |
9273 SUPPORTED_Pause |
9274 SUPPORTED_Asym_Pause);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009275 break;
9276
Eliezer Tamirf1410642008-02-28 11:51:50 -08009277 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
9278 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
9279 ext_phy_type);
9280
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009281 bp->port.supported |= (SUPPORTED_10000baseT_Full |
9282 SUPPORTED_1000baseT_Full |
9283 SUPPORTED_FIBRE |
9284 SUPPORTED_Autoneg |
9285 SUPPORTED_Pause |
9286 SUPPORTED_Asym_Pause);
Eliezer Tamirf1410642008-02-28 11:51:50 -08009287 break;
9288
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009289 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
9290 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
9291 ext_phy_type);
9292
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009293 bp->port.supported |= (SUPPORTED_10000baseT_Full |
9294 SUPPORTED_2500baseX_Full |
9295 SUPPORTED_1000baseT_Full |
9296 SUPPORTED_FIBRE |
9297 SUPPORTED_Autoneg |
9298 SUPPORTED_Pause |
9299 SUPPORTED_Asym_Pause);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009300 break;
9301
Eilon Greenstein589abe32009-02-12 08:36:55 +00009302 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
9303 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
9304 ext_phy_type);
9305
9306 bp->port.supported |= (SUPPORTED_10000baseT_Full |
9307 SUPPORTED_FIBRE |
9308 SUPPORTED_Pause |
9309 SUPPORTED_Asym_Pause);
9310 break;
9311
9312 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
9313 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
9314 ext_phy_type);
9315
9316 bp->port.supported |= (SUPPORTED_10000baseT_Full |
9317 SUPPORTED_1000baseT_Full |
9318 SUPPORTED_FIBRE |
9319 SUPPORTED_Pause |
9320 SUPPORTED_Asym_Pause);
9321 break;
9322
9323 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
9324 BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
9325 ext_phy_type);
9326
9327 bp->port.supported |= (SUPPORTED_10000baseT_Full |
9328 SUPPORTED_1000baseT_Full |
9329 SUPPORTED_Autoneg |
9330 SUPPORTED_FIBRE |
9331 SUPPORTED_Pause |
9332 SUPPORTED_Asym_Pause);
9333 break;
9334
Eilon Greenstein4d295db2009-07-21 05:47:47 +00009335 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9336 BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n",
9337 ext_phy_type);
9338
9339 bp->port.supported |= (SUPPORTED_10000baseT_Full |
9340 SUPPORTED_1000baseT_Full |
9341 SUPPORTED_Autoneg |
9342 SUPPORTED_FIBRE |
9343 SUPPORTED_Pause |
9344 SUPPORTED_Asym_Pause);
9345 break;
9346
Eliezer Tamirf1410642008-02-28 11:51:50 -08009347 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
9348 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
9349 ext_phy_type);
9350
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009351 bp->port.supported |= (SUPPORTED_10000baseT_Full |
9352 SUPPORTED_TP |
9353 SUPPORTED_Autoneg |
9354 SUPPORTED_Pause |
9355 SUPPORTED_Asym_Pause);
Eliezer Tamirf1410642008-02-28 11:51:50 -08009356 break;
9357
Eilon Greenstein28577182009-02-12 08:37:00 +00009358 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
9359 BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n",
9360 ext_phy_type);
9361
9362 bp->port.supported |= (SUPPORTED_10baseT_Half |
9363 SUPPORTED_10baseT_Full |
9364 SUPPORTED_100baseT_Half |
9365 SUPPORTED_100baseT_Full |
9366 SUPPORTED_1000baseT_Full |
9367 SUPPORTED_10000baseT_Full |
9368 SUPPORTED_TP |
9369 SUPPORTED_Autoneg |
9370 SUPPORTED_Pause |
9371 SUPPORTED_Asym_Pause);
9372 break;
9373
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009374 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
9375 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
9376 bp->link_params.ext_phy_config);
9377 break;
9378
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009379 default:
9380 BNX2X_ERR("NVRAM config error. "
9381 "BAD XGXS ext_phy_config 0x%x\n",
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009382 bp->link_params.ext_phy_config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009383 return;
9384 }
9385
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009386 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
9387 port*0x18);
9388 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009389
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009390 break;
9391
9392 default:
9393 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009394 bp->port.link_config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009395 return;
9396 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009397 bp->link_params.phy_addr = bp->port.phy_addr;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009398
9399 /* mask what we support according to speed_cap_mask */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009400 if (!(bp->link_params.speed_cap_mask &
9401 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009402 bp->port.supported &= ~SUPPORTED_10baseT_Half;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009403
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009404 if (!(bp->link_params.speed_cap_mask &
9405 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009406 bp->port.supported &= ~SUPPORTED_10baseT_Full;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009407
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009408 if (!(bp->link_params.speed_cap_mask &
9409 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009410 bp->port.supported &= ~SUPPORTED_100baseT_Half;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009411
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009412 if (!(bp->link_params.speed_cap_mask &
9413 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009414 bp->port.supported &= ~SUPPORTED_100baseT_Full;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009415
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009416 if (!(bp->link_params.speed_cap_mask &
9417 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009418 bp->port.supported &= ~(SUPPORTED_1000baseT_Half |
9419 SUPPORTED_1000baseT_Full);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009420
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009421 if (!(bp->link_params.speed_cap_mask &
9422 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009423 bp->port.supported &= ~SUPPORTED_2500baseX_Full;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009424
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009425 if (!(bp->link_params.speed_cap_mask &
9426 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009427 bp->port.supported &= ~SUPPORTED_10000baseT_Full;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009428
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009429 BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009430}
9431
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009432static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009433{
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009434 bp->link_params.req_duplex = DUPLEX_FULL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009435
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009436 switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009437 case PORT_FEATURE_LINK_SPEED_AUTO:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009438 if (bp->port.supported & SUPPORTED_Autoneg) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009439 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009440 bp->port.advertising = bp->port.supported;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009441 } else {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009442 u32 ext_phy_type =
9443 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
9444
9445 if ((ext_phy_type ==
9446 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
9447 (ext_phy_type ==
9448 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009449 /* force 10G, no AN */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009450 bp->link_params.req_line_speed = SPEED_10000;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009451 bp->port.advertising =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009452 (ADVERTISED_10000baseT_Full |
9453 ADVERTISED_FIBRE);
9454 break;
9455 }
9456 BNX2X_ERR("NVRAM config error. "
9457 "Invalid link_config 0x%x"
9458 " Autoneg not supported\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009459 bp->port.link_config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009460 return;
9461 }
9462 break;
9463
9464 case PORT_FEATURE_LINK_SPEED_10M_FULL:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009465 if (bp->port.supported & SUPPORTED_10baseT_Full) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009466 bp->link_params.req_line_speed = SPEED_10;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009467 bp->port.advertising = (ADVERTISED_10baseT_Full |
9468 ADVERTISED_TP);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009469 } else {
9470 BNX2X_ERR("NVRAM config error. "
9471 "Invalid link_config 0x%x"
9472 " speed_cap_mask 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009473 bp->port.link_config,
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009474 bp->link_params.speed_cap_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009475 return;
9476 }
9477 break;
9478
9479 case PORT_FEATURE_LINK_SPEED_10M_HALF:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009480 if (bp->port.supported & SUPPORTED_10baseT_Half) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009481 bp->link_params.req_line_speed = SPEED_10;
9482 bp->link_params.req_duplex = DUPLEX_HALF;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009483 bp->port.advertising = (ADVERTISED_10baseT_Half |
9484 ADVERTISED_TP);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009485 } else {
9486 BNX2X_ERR("NVRAM config error. "
9487 "Invalid link_config 0x%x"
9488 " speed_cap_mask 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009489 bp->port.link_config,
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009490 bp->link_params.speed_cap_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009491 return;
9492 }
9493 break;
9494
9495 case PORT_FEATURE_LINK_SPEED_100M_FULL:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009496 if (bp->port.supported & SUPPORTED_100baseT_Full) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009497 bp->link_params.req_line_speed = SPEED_100;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009498 bp->port.advertising = (ADVERTISED_100baseT_Full |
9499 ADVERTISED_TP);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009500 } else {
9501 BNX2X_ERR("NVRAM config error. "
9502 "Invalid link_config 0x%x"
9503 " speed_cap_mask 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009504 bp->port.link_config,
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009505 bp->link_params.speed_cap_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009506 return;
9507 }
9508 break;
9509
9510 case PORT_FEATURE_LINK_SPEED_100M_HALF:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009511 if (bp->port.supported & SUPPORTED_100baseT_Half) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009512 bp->link_params.req_line_speed = SPEED_100;
9513 bp->link_params.req_duplex = DUPLEX_HALF;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009514 bp->port.advertising = (ADVERTISED_100baseT_Half |
9515 ADVERTISED_TP);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009516 } else {
9517 BNX2X_ERR("NVRAM config error. "
9518 "Invalid link_config 0x%x"
9519 " speed_cap_mask 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009520 bp->port.link_config,
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009521 bp->link_params.speed_cap_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009522 return;
9523 }
9524 break;
9525
9526 case PORT_FEATURE_LINK_SPEED_1G:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009527 if (bp->port.supported & SUPPORTED_1000baseT_Full) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009528 bp->link_params.req_line_speed = SPEED_1000;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009529 bp->port.advertising = (ADVERTISED_1000baseT_Full |
9530 ADVERTISED_TP);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009531 } else {
9532 BNX2X_ERR("NVRAM config error. "
9533 "Invalid link_config 0x%x"
9534 " speed_cap_mask 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009535 bp->port.link_config,
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009536 bp->link_params.speed_cap_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009537 return;
9538 }
9539 break;
9540
9541 case PORT_FEATURE_LINK_SPEED_2_5G:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009542 if (bp->port.supported & SUPPORTED_2500baseX_Full) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009543 bp->link_params.req_line_speed = SPEED_2500;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009544 bp->port.advertising = (ADVERTISED_2500baseX_Full |
9545 ADVERTISED_TP);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009546 } else {
9547 BNX2X_ERR("NVRAM config error. "
9548 "Invalid link_config 0x%x"
9549 " speed_cap_mask 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009550 bp->port.link_config,
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009551 bp->link_params.speed_cap_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009552 return;
9553 }
9554 break;
9555
9556 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9557 case PORT_FEATURE_LINK_SPEED_10G_KX4:
9558 case PORT_FEATURE_LINK_SPEED_10G_KR:
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009559 if (bp->port.supported & SUPPORTED_10000baseT_Full) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009560 bp->link_params.req_line_speed = SPEED_10000;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009561 bp->port.advertising = (ADVERTISED_10000baseT_Full |
9562 ADVERTISED_FIBRE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009563 } else {
9564 BNX2X_ERR("NVRAM config error. "
9565 "Invalid link_config 0x%x"
9566 " speed_cap_mask 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009567 bp->port.link_config,
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009568 bp->link_params.speed_cap_mask);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009569 return;
9570 }
9571 break;
9572
9573 default:
9574 BNX2X_ERR("NVRAM config error. "
9575 "BAD link speed link_config 0x%x\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009576 bp->port.link_config);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009577 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009578 bp->port.advertising = bp->port.supported;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009579 break;
9580 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009581
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009582 bp->link_params.req_flow_ctrl = (bp->port.link_config &
9583 PORT_FEATURE_FLOW_CONTROL_MASK);
David S. Millerc0700f92008-12-16 23:53:20 -08009584 if ((bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
Randy Dunlap4ab84d42008-08-07 20:33:19 -07009585 !(bp->port.supported & SUPPORTED_Autoneg))
David S. Millerc0700f92008-12-16 23:53:20 -08009586 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009587
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009588 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
Eliezer Tamirf1410642008-02-28 11:51:50 -08009589 " advertising 0x%x\n",
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009590 bp->link_params.req_line_speed,
9591 bp->link_params.req_duplex,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009592 bp->link_params.req_flow_ctrl, bp->port.advertising);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009593}
9594
Michael Chane665bfd2009-10-10 13:46:54 +00009595static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9596{
9597 mac_hi = cpu_to_be16(mac_hi);
9598 mac_lo = cpu_to_be32(mac_lo);
9599 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9600 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9601}
9602
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009603static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009604{
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009605 int port = BP_PORT(bp);
9606 u32 val, val2;
Eilon Greenstein589abe32009-02-12 08:36:55 +00009607 u32 config;
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00009608 u16 i;
Eilon Greenstein01cd4522009-08-12 08:23:08 +00009609 u32 ext_phy_type;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009610
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009611 bp->link_params.bp = bp;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009612 bp->link_params.port = port;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009613
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009614 bp->link_params.lane_config =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009615 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009616 bp->link_params.ext_phy_config =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009617 SHMEM_RD(bp,
9618 dev_info.port_hw_config[port].external_phy_config);
Eilon Greenstein4d295db2009-07-21 05:47:47 +00009619 /* BCM8727_NOC => BCM8727 no over current */
9620 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
9621 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
9622 bp->link_params.ext_phy_config &=
9623 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
9624 bp->link_params.ext_phy_config |=
9625 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
9626 bp->link_params.feature_config_flags |=
9627 FEATURE_CONFIG_BCM8727_NOC;
9628 }
9629
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009630 bp->link_params.speed_cap_mask =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009631 SHMEM_RD(bp,
9632 dev_info.port_hw_config[port].speed_capability_mask);
9633
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009634 bp->port.link_config =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009635 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9636
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00009637 /* Get the 4 lanes xgxs config rx and tx */
9638 for (i = 0; i < 2; i++) {
9639 val = SHMEM_RD(bp,
9640 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
9641 bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
9642 bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
9643
9644 val = SHMEM_RD(bp,
9645 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
9646 bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
9647 bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
9648 }
9649
Eilon Greenstein3ce2c3f2009-02-12 08:37:52 +00009650 /* If the device is capable of WoL, set the default state according
9651 * to the HW
9652 */
Eilon Greenstein4d295db2009-07-21 05:47:47 +00009653 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
Eilon Greenstein3ce2c3f2009-02-12 08:37:52 +00009654 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9655 (config & PORT_FEATURE_WOL_ENABLED));
9656
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00009657 BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x"
9658 " speed_cap_mask 0x%08x link_config 0x%08x\n",
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009659 bp->link_params.lane_config,
9660 bp->link_params.ext_phy_config,
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009661 bp->link_params.speed_cap_mask, bp->port.link_config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009662
Eilon Greenstein4d295db2009-07-21 05:47:47 +00009663 bp->link_params.switch_cfg |= (bp->port.link_config &
9664 PORT_FEATURE_CONNECTED_SWITCH_MASK);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009665 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009666
9667 bnx2x_link_settings_requested(bp);
9668
Eilon Greenstein01cd4522009-08-12 08:23:08 +00009669 /*
9670 * If connected directly, work with the internal PHY, otherwise, work
9671 * with the external PHY
9672 */
9673 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
9674 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9675 bp->mdio.prtad = bp->link_params.phy_addr;
9676
9677 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9678 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9679 bp->mdio.prtad =
Eilon Greenstein659bc5c2009-08-12 08:24:02 +00009680 XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config);
Eilon Greenstein01cd4522009-08-12 08:23:08 +00009681
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009682 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9683 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
Michael Chane665bfd2009-10-10 13:46:54 +00009684 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009685 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9686 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
Michael Chan37b091b2009-10-10 13:46:55 +00009687
9688#ifdef BCM_CNIC
9689 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].iscsi_mac_upper);
9690 val = SHMEM_RD(bp, dev_info.port_hw_config[port].iscsi_mac_lower);
9691 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
9692#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009693}
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009694
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009695static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9696{
9697 int func = BP_FUNC(bp);
9698 u32 val, val2;
9699 int rc = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009700
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009701 bnx2x_get_common_hwinfo(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009702
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009703 bp->e1hov = 0;
9704 bp->e1hmf = 0;
Vladislav Zolotarov2145a922010-04-19 01:13:49 +00009705 if (CHIP_IS_E1H(bp) && !BP_NOMCP(bp)) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009706 bp->mf_config =
9707 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009708
Eilon Greenstein2691d512009-08-12 08:22:08 +00009709 val = (SHMEM_RD(bp, mf_cfg.func_mf_config[FUNC_0].e1hov_tag) &
Eilon Greenstein3196a882008-08-13 15:58:49 -07009710 FUNC_MF_CFG_E1HOV_TAG_MASK);
Eilon Greenstein2691d512009-08-12 08:22:08 +00009711 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009712 bp->e1hmf = 1;
Eilon Greenstein2691d512009-08-12 08:22:08 +00009713 BNX2X_DEV_INFO("%s function mode\n",
9714 IS_E1HMF(bp) ? "multi" : "single");
9715
9716 if (IS_E1HMF(bp)) {
9717 val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].
9718 e1hov_tag) &
9719 FUNC_MF_CFG_E1HOV_TAG_MASK);
9720 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9721 bp->e1hov = val;
9722 BNX2X_DEV_INFO("E1HOV for func %d is %d "
9723 "(0x%04x)\n",
9724 func, bp->e1hov, bp->e1hov);
9725 } else {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009726 BNX2X_ERR("!!! No valid E1HOV for func %d,"
9727 " aborting\n", func);
9728 rc = -EPERM;
9729 }
Eilon Greenstein2691d512009-08-12 08:22:08 +00009730 } else {
9731 if (BP_E1HVN(bp)) {
9732 BNX2X_ERR("!!! VN %d in single function mode,"
9733 " aborting\n", BP_E1HVN(bp));
9734 rc = -EPERM;
9735 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009736 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009737 }
9738
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009739 if (!BP_NOMCP(bp)) {
9740 bnx2x_get_port_hwinfo(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009741
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009742 bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) &
9743 DRV_MSG_SEQ_NUMBER_MASK);
9744 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9745 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009746
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009747 if (IS_E1HMF(bp)) {
9748 val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper);
9749 val = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_lower);
9750 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9751 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
9752 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
9753 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
9754 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
9755 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
9756 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
9757 bp->dev->dev_addr[5] = (u8)(val & 0xff);
9758 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
9759 ETH_ALEN);
9760 memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
9761 ETH_ALEN);
9762 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009763
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009764 return rc;
9765 }
9766
9767 if (BP_NOMCP(bp)) {
9768 /* only supposed to happen on emulation/FPGA */
Eilon Greenstein33471622008-08-13 15:59:08 -07009769 BNX2X_ERR("warning random MAC workaround active\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009770 random_ether_addr(bp->dev->dev_addr);
9771 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9772 }
9773
9774 return rc;
9775}
9776
Vladislav Zolotarov34f24c72010-04-19 01:13:23 +00009777static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9778{
9779 int cnt, i, block_end, rodi;
9780 char vpd_data[BNX2X_VPD_LEN+1];
9781 char str_id_reg[VENDOR_ID_LEN+1];
9782 char str_id_cap[VENDOR_ID_LEN+1];
9783 u8 len;
9784
9785 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9786 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9787
9788 if (cnt < BNX2X_VPD_LEN)
9789 goto out_not_found;
9790
9791 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9792 PCI_VPD_LRDT_RO_DATA);
9793 if (i < 0)
9794 goto out_not_found;
9795
9796
9797 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9798 pci_vpd_lrdt_size(&vpd_data[i]);
9799
9800 i += PCI_VPD_LRDT_TAG_SIZE;
9801
9802 if (block_end > BNX2X_VPD_LEN)
9803 goto out_not_found;
9804
9805 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9806 PCI_VPD_RO_KEYWORD_MFR_ID);
9807 if (rodi < 0)
9808 goto out_not_found;
9809
9810 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9811
9812 if (len != VENDOR_ID_LEN)
9813 goto out_not_found;
9814
9815 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9816
9817 /* vendor specific info */
9818 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9819 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9820 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9821 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9822
9823 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9824 PCI_VPD_RO_KEYWORD_VENDOR0);
9825 if (rodi >= 0) {
9826 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9827
9828 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9829
9830 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9831 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9832 bp->fw_ver[len] = ' ';
9833 }
9834 }
9835 return;
9836 }
9837out_not_found:
9838 return;
9839}
9840
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009841static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9842{
9843 int func = BP_FUNC(bp);
Eilon Greenstein87942b42009-02-12 08:36:49 +00009844 int timer_interval;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009845 int rc;
9846
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009847 /* Disable interrupt handling until HW is initialized */
9848 atomic_set(&bp->intr_sem, 1);
Eilon Greensteine1510702009-07-21 05:47:41 +00009849 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07009850
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009851 mutex_init(&bp->port.phy_mutex);
Eilon Greensteinc4ff7cb2009-10-15 00:18:27 -07009852 mutex_init(&bp->fw_mb_mutex);
Michael Chan993ac7b2009-10-10 13:46:56 +00009853#ifdef BCM_CNIC
9854 mutex_init(&bp->cnic_mutex);
9855#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009856
Eilon Greenstein1cf167f2009-01-14 21:22:18 -08009857 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00009858 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009859
9860 rc = bnx2x_get_hwinfo(bp);
9861
Vladislav Zolotarov34f24c72010-04-19 01:13:23 +00009862 bnx2x_read_fwinfo(bp);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009863 /* need to reset chip if undi was active */
9864 if (!BP_NOMCP(bp))
9865 bnx2x_undi_unload(bp);
9866
9867 if (CHIP_REV_IS_FPGA(bp))
Joe Perches7995c642010-02-17 15:01:52 +00009868 pr_err("FPGA detected\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009869
9870 if (BP_NOMCP(bp) && (func == 0))
Joe Perches7995c642010-02-17 15:01:52 +00009871 pr_err("MCP disabled, must load devices in order!\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009872
Eilon Greenstein555f6c72009-02-12 08:36:11 +00009873 /* Set multi queue mode */
Eilon Greenstein8badd272009-02-12 08:36:15 +00009874 if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
9875 ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
Joe Perches7995c642010-02-17 15:01:52 +00009876 pr_err("Multi disabled since int_mode requested is not MSI-X\n");
Eilon Greenstein555f6c72009-02-12 08:36:11 +00009877 multi_mode = ETH_RSS_MODE_DISABLED;
9878 }
9879 bp->multi_mode = multi_mode;
9880
9881
Dmitry Kravkov4fd89b72010-04-01 19:45:34 -07009882 bp->dev->features |= NETIF_F_GRO;
9883
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07009884 /* Set TPA flags */
9885 if (disable_tpa) {
9886 bp->flags &= ~TPA_ENABLE_FLAG;
9887 bp->dev->features &= ~NETIF_F_LRO;
9888 } else {
9889 bp->flags |= TPA_ENABLE_FLAG;
9890 bp->dev->features |= NETIF_F_LRO;
9891 }
9892
Eilon Greensteina18f5122009-08-12 08:23:26 +00009893 if (CHIP_IS_E1(bp))
9894 bp->dropless_fc = 0;
9895 else
9896 bp->dropless_fc = dropless_fc;
9897
Eilon Greenstein8d5726c2009-02-12 08:37:19 +00009898 bp->mrrs = mrrs;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07009899
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009900 bp->tx_ring_size = MAX_TX_AVAIL;
9901 bp->rx_ring_size = MAX_RX_AVAIL;
9902
9903 bp->rx_csum = 1;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009904
Eilon Greenstein7d323bf2009-11-09 06:09:35 +00009905 /* make sure that the numbers are in the right granularity */
9906 bp->tx_ticks = (50 / (4 * BNX2X_BTR)) * (4 * BNX2X_BTR);
9907 bp->rx_ticks = (25 / (4 * BNX2X_BTR)) * (4 * BNX2X_BTR);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009908
Eilon Greenstein87942b42009-02-12 08:36:49 +00009909 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9910 bp->current_interval = (poll ? poll : timer_interval);
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009911
9912 init_timer(&bp->timer);
9913 bp->timer.expires = jiffies + bp->current_interval;
9914 bp->timer.data = (unsigned long) bp;
9915 bp->timer.function = bnx2x_timer;
9916
9917 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009918}
9919
9920/*
9921 * ethtool service functions
9922 */
9923
9924/* All ethtool functions called with rtnl_lock */
9925
9926static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9927{
9928 struct bnx2x *bp = netdev_priv(dev);
9929
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009930 cmd->supported = bp->port.supported;
9931 cmd->advertising = bp->port.advertising;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009932
Eilon Greensteinf34d28e2009-10-15 00:18:08 -07009933 if ((bp->state == BNX2X_STATE_OPEN) &&
9934 !(bp->flags & MF_FUNC_DIS) &&
9935 (bp->link_vars.link_up)) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009936 cmd->speed = bp->link_vars.line_speed;
9937 cmd->duplex = bp->link_vars.duplex;
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07009938 if (IS_E1HMF(bp)) {
9939 u16 vn_max_rate;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009940
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07009941 vn_max_rate =
9942 ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009943 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
Eilon Greensteinb015e3d2009-10-15 00:17:20 -07009944 if (vn_max_rate < cmd->speed)
9945 cmd->speed = vn_max_rate;
9946 }
9947 } else {
9948 cmd->speed = -1;
9949 cmd->duplex = -1;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07009950 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009951
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009952 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
9953 u32 ext_phy_type =
9954 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
Eliezer Tamirf1410642008-02-28 11:51:50 -08009955
9956 switch (ext_phy_type) {
9957 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
Eliezer Tamirf1410642008-02-28 11:51:50 -08009958 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
Eilon Greenstein589abe32009-02-12 08:36:55 +00009960 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
9961 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
9962 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
Eilon Greenstein4d295db2009-07-21 05:47:47 +00009963 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
Eliezer Tamirf1410642008-02-28 11:51:50 -08009964 cmd->port = PORT_FIBRE;
9965 break;
9966
9967 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
Eilon Greenstein28577182009-02-12 08:37:00 +00009968 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
Eliezer Tamirf1410642008-02-28 11:51:50 -08009969 cmd->port = PORT_TP;
9970 break;
9971
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009972 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
9973 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
9974 bp->link_params.ext_phy_config);
9975 break;
9976
Eliezer Tamirf1410642008-02-28 11:51:50 -08009977 default:
9978 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009979 bp->link_params.ext_phy_config);
9980 break;
Eliezer Tamirf1410642008-02-28 11:51:50 -08009981 }
9982 } else
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009983 cmd->port = PORT_TP;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009984
Eilon Greenstein01cd4522009-08-12 08:23:08 +00009985 cmd->phy_address = bp->mdio.prtad;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009986 cmd->transceiver = XCVR_INTERNAL;
9987
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07009988 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009989 cmd->autoneg = AUTONEG_ENABLE;
Eliezer Tamirf1410642008-02-28 11:51:50 -08009990 else
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009991 cmd->autoneg = AUTONEG_DISABLE;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02009992
9993 cmd->maxtxpkt = 0;
9994 cmd->maxrxpkt = 0;
9995
9996 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
9997 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
9998 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
9999 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
10000 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
10001 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
10002 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
10003
10004 return 0;
10005}
10006
10007static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10008{
10009 struct bnx2x *bp = netdev_priv(dev);
10010 u32 advertising;
10011
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010012 if (IS_E1HMF(bp))
10013 return 0;
10014
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010015 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
10016 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
10017 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
10018 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
10019 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
10020 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
10021 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
10022
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010023 if (cmd->autoneg == AUTONEG_ENABLE) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010024 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
10025 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010026 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010027 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010028
10029 /* advertise the requested speed and duplex if supported */
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010030 cmd->advertising &= bp->port.supported;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010031
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010032 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
10033 bp->link_params.req_duplex = DUPLEX_FULL;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010034 bp->port.advertising |= (ADVERTISED_Autoneg |
10035 cmd->advertising);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010036
10037 } else { /* forced speed */
10038 /* advertise the requested speed and duplex if supported */
10039 switch (cmd->speed) {
10040 case SPEED_10:
10041 if (cmd->duplex == DUPLEX_FULL) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010042 if (!(bp->port.supported &
Eliezer Tamirf1410642008-02-28 11:51:50 -080010043 SUPPORTED_10baseT_Full)) {
10044 DP(NETIF_MSG_LINK,
10045 "10M full not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010046 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010047 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010048
10049 advertising = (ADVERTISED_10baseT_Full |
10050 ADVERTISED_TP);
10051 } else {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010052 if (!(bp->port.supported &
Eliezer Tamirf1410642008-02-28 11:51:50 -080010053 SUPPORTED_10baseT_Half)) {
10054 DP(NETIF_MSG_LINK,
10055 "10M half not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010056 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010057 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010058
10059 advertising = (ADVERTISED_10baseT_Half |
10060 ADVERTISED_TP);
10061 }
10062 break;
10063
10064 case SPEED_100:
10065 if (cmd->duplex == DUPLEX_FULL) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010066 if (!(bp->port.supported &
Eliezer Tamirf1410642008-02-28 11:51:50 -080010067 SUPPORTED_100baseT_Full)) {
10068 DP(NETIF_MSG_LINK,
10069 "100M full not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010070 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010071 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010072
10073 advertising = (ADVERTISED_100baseT_Full |
10074 ADVERTISED_TP);
10075 } else {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010076 if (!(bp->port.supported &
Eliezer Tamirf1410642008-02-28 11:51:50 -080010077 SUPPORTED_100baseT_Half)) {
10078 DP(NETIF_MSG_LINK,
10079 "100M half not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010080 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010081 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010082
10083 advertising = (ADVERTISED_100baseT_Half |
10084 ADVERTISED_TP);
10085 }
10086 break;
10087
10088 case SPEED_1000:
Eliezer Tamirf1410642008-02-28 11:51:50 -080010089 if (cmd->duplex != DUPLEX_FULL) {
10090 DP(NETIF_MSG_LINK, "1G half not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010091 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010092 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010093
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010094 if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
Eliezer Tamirf1410642008-02-28 11:51:50 -080010095 DP(NETIF_MSG_LINK, "1G full not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010096 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010097 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010098
10099 advertising = (ADVERTISED_1000baseT_Full |
10100 ADVERTISED_TP);
10101 break;
10102
10103 case SPEED_2500:
Eliezer Tamirf1410642008-02-28 11:51:50 -080010104 if (cmd->duplex != DUPLEX_FULL) {
10105 DP(NETIF_MSG_LINK,
10106 "2.5G half not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010107 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010108 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010109
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010110 if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
Eliezer Tamirf1410642008-02-28 11:51:50 -080010111 DP(NETIF_MSG_LINK,
10112 "2.5G full not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010113 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010114 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010115
Eliezer Tamirf1410642008-02-28 11:51:50 -080010116 advertising = (ADVERTISED_2500baseX_Full |
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010117 ADVERTISED_TP);
10118 break;
10119
10120 case SPEED_10000:
Eliezer Tamirf1410642008-02-28 11:51:50 -080010121 if (cmd->duplex != DUPLEX_FULL) {
10122 DP(NETIF_MSG_LINK, "10G half not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010123 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010124 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010125
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010126 if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
Eliezer Tamirf1410642008-02-28 11:51:50 -080010127 DP(NETIF_MSG_LINK, "10G full not supported\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010128 return -EINVAL;
Eliezer Tamirf1410642008-02-28 11:51:50 -080010129 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010130
10131 advertising = (ADVERTISED_10000baseT_Full |
10132 ADVERTISED_FIBRE);
10133 break;
10134
10135 default:
Eliezer Tamirf1410642008-02-28 11:51:50 -080010136 DP(NETIF_MSG_LINK, "Unsupported speed\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010137 return -EINVAL;
10138 }
10139
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010140 bp->link_params.req_line_speed = cmd->speed;
10141 bp->link_params.req_duplex = cmd->duplex;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010142 bp->port.advertising = advertising;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010143 }
10144
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010145 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010146 DP_LEVEL " req_duplex %d advertising 0x%x\n",
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010147 bp->link_params.req_line_speed, bp->link_params.req_duplex,
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010148 bp->port.advertising);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010149
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010150 if (netif_running(dev)) {
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070010151 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010152 bnx2x_link_set(bp);
10153 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010154
10155 return 0;
10156}
10157
Eilon Greenstein0a64ea52009-03-02 08:01:12 +000010158#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
10159#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
10160
10161static int bnx2x_get_regs_len(struct net_device *dev)
10162{
Eilon Greenstein0a64ea52009-03-02 08:01:12 +000010163 struct bnx2x *bp = netdev_priv(dev);
Eilon Greenstein0d28e492009-08-12 08:23:40 +000010164 int regdump_len = 0;
Eilon Greenstein0a64ea52009-03-02 08:01:12 +000010165 int i;
10166
Eilon Greenstein0a64ea52009-03-02 08:01:12 +000010167 if (CHIP_IS_E1(bp)) {
10168 for (i = 0; i < REGS_COUNT; i++)
10169 if (IS_E1_ONLINE(reg_addrs[i].info))
10170 regdump_len += reg_addrs[i].size;
10171
10172 for (i = 0; i < WREGS_COUNT_E1; i++)
10173 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
10174 regdump_len += wreg_addrs_e1[i].size *
10175 (1 + wreg_addrs_e1[i].read_regs_count);
10176
10177 } else { /* E1H */
10178 for (i = 0; i < REGS_COUNT; i++)
10179 if (IS_E1H_ONLINE(reg_addrs[i].info))
10180 regdump_len += reg_addrs[i].size;
10181
10182 for (i = 0; i < WREGS_COUNT_E1H; i++)
10183 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
10184 regdump_len += wreg_addrs_e1h[i].size *
10185 (1 + wreg_addrs_e1h[i].read_regs_count);
10186 }
10187 regdump_len *= 4;
10188 regdump_len += sizeof(struct dump_hdr);
10189
10190 return regdump_len;
10191}
10192
10193static void bnx2x_get_regs(struct net_device *dev,
10194 struct ethtool_regs *regs, void *_p)
10195{
10196 u32 *p = _p, i, j;
10197 struct bnx2x *bp = netdev_priv(dev);
10198 struct dump_hdr dump_hdr = {0};
10199
10200 regs->version = 0;
10201 memset(p, 0, regs->len);
10202
10203 if (!netif_running(bp->dev))
10204 return;
10205
10206 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
10207 dump_hdr.dump_sign = dump_sign_all;
10208 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
10209 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
10210 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
10211 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
10212 dump_hdr.info = CHIP_IS_E1(bp) ? RI_E1_ONLINE : RI_E1H_ONLINE;
10213
10214 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
10215 p += dump_hdr.hdr_size + 1;
10216
10217 if (CHIP_IS_E1(bp)) {
10218 for (i = 0; i < REGS_COUNT; i++)
10219 if (IS_E1_ONLINE(reg_addrs[i].info))
10220 for (j = 0; j < reg_addrs[i].size; j++)
10221 *p++ = REG_RD(bp,
10222 reg_addrs[i].addr + j*4);
10223
10224 } else { /* E1H */
10225 for (i = 0; i < REGS_COUNT; i++)
10226 if (IS_E1H_ONLINE(reg_addrs[i].info))
10227 for (j = 0; j < reg_addrs[i].size; j++)
10228 *p++ = REG_RD(bp,
10229 reg_addrs[i].addr + j*4);
10230 }
10231}
10232
Eilon Greenstein0d28e492009-08-12 08:23:40 +000010233#define PHY_FW_VER_LEN 10
10234
10235static void bnx2x_get_drvinfo(struct net_device *dev,
10236 struct ethtool_drvinfo *info)
10237{
10238 struct bnx2x *bp = netdev_priv(dev);
10239 u8 phy_fw_ver[PHY_FW_VER_LEN];
10240
10241 strcpy(info->driver, DRV_MODULE_NAME);
10242 strcpy(info->version, DRV_MODULE_VERSION);
10243
10244 phy_fw_ver[0] = '\0';
10245 if (bp->port.pmf) {
10246 bnx2x_acquire_phy_lock(bp);
10247 bnx2x_get_ext_phy_fw_version(&bp->link_params,
10248 (bp->state != BNX2X_STATE_CLOSED),
10249 phy_fw_ver, PHY_FW_VER_LEN);
10250 bnx2x_release_phy_lock(bp);
10251 }
10252
Vladislav Zolotarov34f24c72010-04-19 01:13:23 +000010253 strncpy(info->fw_version, bp->fw_ver, 32);
10254 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
10255 "bc %d.%d.%d%s%s",
Eilon Greenstein0d28e492009-08-12 08:23:40 +000010256 (bp->common.bc_ver & 0xff0000) >> 16,
10257 (bp->common.bc_ver & 0xff00) >> 8,
10258 (bp->common.bc_ver & 0xff),
Vladislav Zolotarov34f24c72010-04-19 01:13:23 +000010259 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
Eilon Greenstein0d28e492009-08-12 08:23:40 +000010260 strcpy(info->bus_info, pci_name(bp->pdev));
10261 info->n_stats = BNX2X_NUM_STATS;
10262 info->testinfo_len = BNX2X_NUM_TESTS;
10263 info->eedump_len = bp->common.flash_size;
10264 info->regdump_len = bnx2x_get_regs_len(dev);
10265}
10266
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010267static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10268{
10269 struct bnx2x *bp = netdev_priv(dev);
10270
10271 if (bp->flags & NO_WOL_FLAG) {
10272 wol->supported = 0;
10273 wol->wolopts = 0;
10274 } else {
10275 wol->supported = WAKE_MAGIC;
10276 if (bp->wol)
10277 wol->wolopts = WAKE_MAGIC;
10278 else
10279 wol->wolopts = 0;
10280 }
10281 memset(&wol->sopass, 0, sizeof(wol->sopass));
10282}
10283
10284static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10285{
10286 struct bnx2x *bp = netdev_priv(dev);
10287
10288 if (wol->wolopts & ~WAKE_MAGIC)
10289 return -EINVAL;
10290
10291 if (wol->wolopts & WAKE_MAGIC) {
10292 if (bp->flags & NO_WOL_FLAG)
10293 return -EINVAL;
10294
10295 bp->wol = 1;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010296 } else
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010297 bp->wol = 0;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010298
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010299 return 0;
10300}
10301
10302static u32 bnx2x_get_msglevel(struct net_device *dev)
10303{
10304 struct bnx2x *bp = netdev_priv(dev);
10305
Joe Perches7995c642010-02-17 15:01:52 +000010306 return bp->msg_enable;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010307}
10308
10309static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
10310{
10311 struct bnx2x *bp = netdev_priv(dev);
10312
10313 if (capable(CAP_NET_ADMIN))
Joe Perches7995c642010-02-17 15:01:52 +000010314 bp->msg_enable = level;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010315}
10316
10317static int bnx2x_nway_reset(struct net_device *dev)
10318{
10319 struct bnx2x *bp = netdev_priv(dev);
10320
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010321 if (!bp->port.pmf)
10322 return 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010323
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010324 if (netif_running(dev)) {
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070010325 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010326 bnx2x_link_set(bp);
10327 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010328
10329 return 0;
10330}
10331
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000010332static u32 bnx2x_get_link(struct net_device *dev)
Naohiro Ooiwa01e53292009-06-30 12:44:19 -070010333{
10334 struct bnx2x *bp = netdev_priv(dev);
10335
Eilon Greensteinf34d28e2009-10-15 00:18:08 -070010336 if (bp->flags & MF_FUNC_DIS)
10337 return 0;
10338
Naohiro Ooiwa01e53292009-06-30 12:44:19 -070010339 return bp->link_vars.link_up;
10340}
10341
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010342static int bnx2x_get_eeprom_len(struct net_device *dev)
10343{
10344 struct bnx2x *bp = netdev_priv(dev);
10345
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010346 return bp->common.flash_size;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010347}
10348
10349static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
10350{
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010351 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010352 int count, i;
10353 u32 val = 0;
10354
10355 /* adjust timeout for emulation/FPGA */
10356 count = NVRAM_TIMEOUT_COUNT;
10357 if (CHIP_REV_IS_SLOW(bp))
10358 count *= 100;
10359
10360 /* request access to nvram interface */
10361 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10362 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
10363
10364 for (i = 0; i < count*10; i++) {
10365 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
10366 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
10367 break;
10368
10369 udelay(5);
10370 }
10371
10372 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010373 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010374 return -EBUSY;
10375 }
10376
10377 return 0;
10378}
10379
10380static int bnx2x_release_nvram_lock(struct bnx2x *bp)
10381{
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010382 int port = BP_PORT(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010383 int count, i;
10384 u32 val = 0;
10385
10386 /* adjust timeout for emulation/FPGA */
10387 count = NVRAM_TIMEOUT_COUNT;
10388 if (CHIP_REV_IS_SLOW(bp))
10389 count *= 100;
10390
10391 /* relinquish nvram interface */
10392 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10393 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
10394
10395 for (i = 0; i < count*10; i++) {
10396 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
10397 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
10398 break;
10399
10400 udelay(5);
10401 }
10402
10403 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010404 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010405 return -EBUSY;
10406 }
10407
10408 return 0;
10409}
10410
10411static void bnx2x_enable_nvram_access(struct bnx2x *bp)
10412{
10413 u32 val;
10414
10415 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
10416
10417 /* enable both bits, even on read */
10418 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
10419 (val | MCPR_NVM_ACCESS_ENABLE_EN |
10420 MCPR_NVM_ACCESS_ENABLE_WR_EN));
10421}
10422
10423static void bnx2x_disable_nvram_access(struct bnx2x *bp)
10424{
10425 u32 val;
10426
10427 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
10428
10429 /* disable both bits, even after read */
10430 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
10431 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
10432 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
10433}
10434
Eilon Greenstein4781bfa2009-02-12 08:38:17 +000010435static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010436 u32 cmd_flags)
10437{
Eliezer Tamirf1410642008-02-28 11:51:50 -080010438 int count, i, rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010439 u32 val;
10440
10441 /* build the command word */
10442 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
10443
10444 /* need to clear DONE bit separately */
10445 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
10446
10447 /* address of the NVRAM to read from */
10448 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
10449 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
10450
10451 /* issue a read command */
10452 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
10453
10454 /* adjust timeout for emulation/FPGA */
10455 count = NVRAM_TIMEOUT_COUNT;
10456 if (CHIP_REV_IS_SLOW(bp))
10457 count *= 100;
10458
10459 /* wait for completion */
10460 *ret_val = 0;
10461 rc = -EBUSY;
10462 for (i = 0; i < count; i++) {
10463 udelay(5);
10464 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
10465
10466 if (val & MCPR_NVM_COMMAND_DONE) {
10467 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010468 /* we read nvram data in cpu order
10469 * but ethtool sees it as an array of bytes
10470 * converting to big-endian will do the work */
Eilon Greenstein4781bfa2009-02-12 08:38:17 +000010471 *ret_val = cpu_to_be32(val);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010472 rc = 0;
10473 break;
10474 }
10475 }
10476
10477 return rc;
10478}
10479
10480static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
10481 int buf_size)
10482{
10483 int rc;
10484 u32 cmd_flags;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +000010485 __be32 val;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010486
10487 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010488 DP(BNX2X_MSG_NVM,
Eliezer Tamirc14423f2008-02-28 11:49:42 -080010489 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010490 offset, buf_size);
10491 return -EINVAL;
10492 }
10493
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010494 if (offset + buf_size > bp->common.flash_size) {
10495 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010496 " buf_size (0x%x) > flash_size (0x%x)\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010497 offset, buf_size, bp->common.flash_size);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010498 return -EINVAL;
10499 }
10500
10501 /* request access to nvram interface */
10502 rc = bnx2x_acquire_nvram_lock(bp);
10503 if (rc)
10504 return rc;
10505
10506 /* enable access to nvram interface */
10507 bnx2x_enable_nvram_access(bp);
10508
10509 /* read the first word(s) */
10510 cmd_flags = MCPR_NVM_COMMAND_FIRST;
10511 while ((buf_size > sizeof(u32)) && (rc == 0)) {
10512 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
10513 memcpy(ret_buf, &val, 4);
10514
10515 /* advance to the next dword */
10516 offset += sizeof(u32);
10517 ret_buf += sizeof(u32);
10518 buf_size -= sizeof(u32);
10519 cmd_flags = 0;
10520 }
10521
10522 if (rc == 0) {
10523 cmd_flags |= MCPR_NVM_COMMAND_LAST;
10524 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
10525 memcpy(ret_buf, &val, 4);
10526 }
10527
10528 /* disable access to nvram interface */
10529 bnx2x_disable_nvram_access(bp);
10530 bnx2x_release_nvram_lock(bp);
10531
10532 return rc;
10533}
10534
10535static int bnx2x_get_eeprom(struct net_device *dev,
10536 struct ethtool_eeprom *eeprom, u8 *eebuf)
10537{
10538 struct bnx2x *bp = netdev_priv(dev);
10539 int rc;
10540
Eilon Greenstein2add3ac2009-01-14 06:44:07 +000010541 if (!netif_running(dev))
10542 return -EAGAIN;
10543
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010544 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010545 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
10546 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
10547 eeprom->len, eeprom->len);
10548
10549 /* parameters already validated in ethtool_get_eeprom */
10550
10551 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
10552
10553 return rc;
10554}
10555
10556static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
10557 u32 cmd_flags)
10558{
Eliezer Tamirf1410642008-02-28 11:51:50 -080010559 int count, i, rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010560
10561 /* build the command word */
10562 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
10563
10564 /* need to clear DONE bit separately */
10565 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
10566
10567 /* write the data */
10568 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
10569
10570 /* address of the NVRAM to write to */
10571 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
10572 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
10573
10574 /* issue the write command */
10575 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
10576
10577 /* adjust timeout for emulation/FPGA */
10578 count = NVRAM_TIMEOUT_COUNT;
10579 if (CHIP_REV_IS_SLOW(bp))
10580 count *= 100;
10581
10582 /* wait for completion */
10583 rc = -EBUSY;
10584 for (i = 0; i < count; i++) {
10585 udelay(5);
10586 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
10587 if (val & MCPR_NVM_COMMAND_DONE) {
10588 rc = 0;
10589 break;
10590 }
10591 }
10592
10593 return rc;
10594}
10595
Eliezer Tamirf1410642008-02-28 11:51:50 -080010596#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010597
10598static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
10599 int buf_size)
10600{
10601 int rc;
10602 u32 cmd_flags;
10603 u32 align_offset;
Eilon Greenstein4781bfa2009-02-12 08:38:17 +000010604 __be32 val;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010605
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010606 if (offset + buf_size > bp->common.flash_size) {
10607 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010608 " buf_size (0x%x) > flash_size (0x%x)\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010609 offset, buf_size, bp->common.flash_size);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010610 return -EINVAL;
10611 }
10612
10613 /* request access to nvram interface */
10614 rc = bnx2x_acquire_nvram_lock(bp);
10615 if (rc)
10616 return rc;
10617
10618 /* enable access to nvram interface */
10619 bnx2x_enable_nvram_access(bp);
10620
10621 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
10622 align_offset = (offset & ~0x03);
10623 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
10624
10625 if (rc == 0) {
10626 val &= ~(0xff << BYTE_OFFSET(offset));
10627 val |= (*data_buf << BYTE_OFFSET(offset));
10628
10629 /* nvram data is returned as an array of bytes
10630 * convert it back to cpu order */
10631 val = be32_to_cpu(val);
10632
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010633 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
10634 cmd_flags);
10635 }
10636
10637 /* disable access to nvram interface */
10638 bnx2x_disable_nvram_access(bp);
10639 bnx2x_release_nvram_lock(bp);
10640
10641 return rc;
10642}
10643
10644static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
10645 int buf_size)
10646{
10647 int rc;
10648 u32 cmd_flags;
10649 u32 val;
10650 u32 written_so_far;
10651
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010652 if (buf_size == 1) /* ethtool */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010653 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010654
10655 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010656 DP(BNX2X_MSG_NVM,
Eliezer Tamirc14423f2008-02-28 11:49:42 -080010657 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010658 offset, buf_size);
10659 return -EINVAL;
10660 }
10661
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010662 if (offset + buf_size > bp->common.flash_size) {
10663 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010664 " buf_size (0x%x) > flash_size (0x%x)\n",
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010665 offset, buf_size, bp->common.flash_size);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010666 return -EINVAL;
10667 }
10668
10669 /* request access to nvram interface */
10670 rc = bnx2x_acquire_nvram_lock(bp);
10671 if (rc)
10672 return rc;
10673
10674 /* enable access to nvram interface */
10675 bnx2x_enable_nvram_access(bp);
10676
10677 written_so_far = 0;
10678 cmd_flags = MCPR_NVM_COMMAND_FIRST;
10679 while ((written_so_far < buf_size) && (rc == 0)) {
10680 if (written_so_far == (buf_size - sizeof(u32)))
10681 cmd_flags |= MCPR_NVM_COMMAND_LAST;
10682 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
10683 cmd_flags |= MCPR_NVM_COMMAND_LAST;
10684 else if ((offset % NVRAM_PAGE_SIZE) == 0)
10685 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
10686
10687 memcpy(&val, data_buf, 4);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010688
10689 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
10690
10691 /* advance to the next dword */
10692 offset += sizeof(u32);
10693 data_buf += sizeof(u32);
10694 written_so_far += sizeof(u32);
10695 cmd_flags = 0;
10696 }
10697
10698 /* disable access to nvram interface */
10699 bnx2x_disable_nvram_access(bp);
10700 bnx2x_release_nvram_lock(bp);
10701
10702 return rc;
10703}
10704
10705static int bnx2x_set_eeprom(struct net_device *dev,
10706 struct ethtool_eeprom *eeprom, u8 *eebuf)
10707{
10708 struct bnx2x *bp = netdev_priv(dev);
Eilon Greensteinf57a6022009-08-12 08:23:11 +000010709 int port = BP_PORT(bp);
10710 int rc = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010711
Eilon Greenstein9f4c9582009-01-08 11:21:43 -080010712 if (!netif_running(dev))
10713 return -EAGAIN;
10714
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010715 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010716 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
10717 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
10718 eeprom->len, eeprom->len);
10719
10720 /* parameters already validated in ethtool_set_eeprom */
10721
Eilon Greensteinf57a6022009-08-12 08:23:11 +000010722 /* PHY eeprom can be accessed only by the PMF */
10723 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
10724 !bp->port.pmf)
10725 return -EINVAL;
10726
10727 if (eeprom->magic == 0x50485950) {
10728 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
10729 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10730
10731 bnx2x_acquire_phy_lock(bp);
10732 rc |= bnx2x_link_reset(&bp->link_params,
10733 &bp->link_vars, 0);
10734 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
10735 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
10736 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
10737 MISC_REGISTERS_GPIO_HIGH, port);
10738 bnx2x_release_phy_lock(bp);
10739 bnx2x_link_report(bp);
10740
10741 } else if (eeprom->magic == 0x50485952) {
10742 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
Eilon Greensteinf34d28e2009-10-15 00:18:08 -070010743 if (bp->state == BNX2X_STATE_OPEN) {
Eilon Greensteinf57a6022009-08-12 08:23:11 +000010744 bnx2x_acquire_phy_lock(bp);
10745 rc |= bnx2x_link_reset(&bp->link_params,
10746 &bp->link_vars, 1);
10747
10748 rc |= bnx2x_phy_init(&bp->link_params,
10749 &bp->link_vars);
10750 bnx2x_release_phy_lock(bp);
10751 bnx2x_calc_fc_adv(bp);
10752 }
10753 } else if (eeprom->magic == 0x53985943) {
10754 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
10755 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
10756 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
10757 u8 ext_phy_addr =
Eilon Greenstein659bc5c2009-08-12 08:24:02 +000010758 XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config);
Eilon Greensteinf57a6022009-08-12 08:23:11 +000010759
10760 /* DSP Remove Download Mode */
10761 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
10762 MISC_REGISTERS_GPIO_LOW, port);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010763
Yitchak Gertner4a37fb62008-08-13 15:50:23 -070010764 bnx2x_acquire_phy_lock(bp);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010765
Eilon Greensteinf57a6022009-08-12 08:23:11 +000010766 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
10767
10768 /* wait 0.5 sec to allow it to run */
10769 msleep(500);
10770 bnx2x_ext_phy_hw_reset(bp, port);
10771 msleep(500);
10772 bnx2x_release_phy_lock(bp);
10773 }
10774 } else
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010775 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010776
10777 return rc;
10778}
10779
10780static int bnx2x_get_coalesce(struct net_device *dev,
10781 struct ethtool_coalesce *coal)
10782{
10783 struct bnx2x *bp = netdev_priv(dev);
10784
10785 memset(coal, 0, sizeof(struct ethtool_coalesce));
10786
10787 coal->rx_coalesce_usecs = bp->rx_ticks;
10788 coal->tx_coalesce_usecs = bp->tx_ticks;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010789
10790 return 0;
10791}
10792
Eilon Greensteinca003922009-08-12 22:53:28 -070010793#define BNX2X_MAX_COALES_TOUT (0xf0*12) /* Maximal coalescing timeout in us */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010794static int bnx2x_set_coalesce(struct net_device *dev,
10795 struct ethtool_coalesce *coal)
10796{
10797 struct bnx2x *bp = netdev_priv(dev);
10798
10799 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
Eilon Greensteinca003922009-08-12 22:53:28 -070010800 if (bp->rx_ticks > BNX2X_MAX_COALES_TOUT)
10801 bp->rx_ticks = BNX2X_MAX_COALES_TOUT;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010802
10803 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
Eilon Greensteinca003922009-08-12 22:53:28 -070010804 if (bp->tx_ticks > BNX2X_MAX_COALES_TOUT)
10805 bp->tx_ticks = BNX2X_MAX_COALES_TOUT;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010806
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010807 if (netif_running(dev))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010808 bnx2x_update_coalesce(bp);
10809
10810 return 0;
10811}
10812
10813static void bnx2x_get_ringparam(struct net_device *dev,
10814 struct ethtool_ringparam *ering)
10815{
10816 struct bnx2x *bp = netdev_priv(dev);
10817
10818 ering->rx_max_pending = MAX_RX_AVAIL;
10819 ering->rx_mini_max_pending = 0;
10820 ering->rx_jumbo_max_pending = 0;
10821
10822 ering->rx_pending = bp->rx_ring_size;
10823 ering->rx_mini_pending = 0;
10824 ering->rx_jumbo_pending = 0;
10825
10826 ering->tx_max_pending = MAX_TX_AVAIL;
10827 ering->tx_pending = bp->tx_ring_size;
10828}
10829
10830static int bnx2x_set_ringparam(struct net_device *dev,
10831 struct ethtool_ringparam *ering)
10832{
10833 struct bnx2x *bp = netdev_priv(dev);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010834 int rc = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010835
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000010836 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10837 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
10838 return -EAGAIN;
10839 }
10840
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010841 if ((ering->rx_pending > MAX_RX_AVAIL) ||
10842 (ering->tx_pending > MAX_TX_AVAIL) ||
10843 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
10844 return -EINVAL;
10845
10846 bp->rx_ring_size = ering->rx_pending;
10847 bp->tx_ring_size = ering->tx_pending;
10848
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010849 if (netif_running(dev)) {
10850 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
10851 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010852 }
10853
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010854 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010855}
10856
10857static void bnx2x_get_pauseparam(struct net_device *dev,
10858 struct ethtool_pauseparam *epause)
10859{
10860 struct bnx2x *bp = netdev_priv(dev);
10861
Eilon Greenstein356e2382009-02-12 08:38:32 +000010862 epause->autoneg = (bp->link_params.req_flow_ctrl ==
10863 BNX2X_FLOW_CTRL_AUTO) &&
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010864 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
10865
David S. Millerc0700f92008-12-16 23:53:20 -080010866 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
10867 BNX2X_FLOW_CTRL_RX);
10868 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
10869 BNX2X_FLOW_CTRL_TX);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010870
10871 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
10872 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
10873 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
10874}
10875
10876static int bnx2x_set_pauseparam(struct net_device *dev,
10877 struct ethtool_pauseparam *epause)
10878{
10879 struct bnx2x *bp = netdev_priv(dev);
10880
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010881 if (IS_E1HMF(bp))
10882 return 0;
10883
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010884 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
10885 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
10886 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
10887
David S. Millerc0700f92008-12-16 23:53:20 -080010888 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010889
10890 if (epause->rx_pause)
David S. Millerc0700f92008-12-16 23:53:20 -080010891 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_RX;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010892
10893 if (epause->tx_pause)
David S. Millerc0700f92008-12-16 23:53:20 -080010894 bp->link_params.req_flow_ctrl |= BNX2X_FLOW_CTRL_TX;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010895
David S. Millerc0700f92008-12-16 23:53:20 -080010896 if (bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
10897 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010898
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010899 if (epause->autoneg) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010900 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
Eilon Greenstein3196a882008-08-13 15:58:49 -070010901 DP(NETIF_MSG_LINK, "autoneg not supported\n");
Eliezer Tamirf1410642008-02-28 11:51:50 -080010902 return -EINVAL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010903 }
10904
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010905 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
David S. Millerc0700f92008-12-16 23:53:20 -080010906 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010907 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010908
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070010909 DP(NETIF_MSG_LINK,
10910 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010911
10912 if (netif_running(dev)) {
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070010913 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070010914 bnx2x_link_set(bp);
10915 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010916
10917 return 0;
10918}
10919
Vladislav Zolotarovdf0f2342008-08-13 15:53:38 -070010920static int bnx2x_set_flags(struct net_device *dev, u32 data)
10921{
10922 struct bnx2x *bp = netdev_priv(dev);
10923 int changed = 0;
10924 int rc = 0;
10925
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000010926 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10927 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
10928 return -EAGAIN;
10929 }
10930
Vladislav Zolotarovdf0f2342008-08-13 15:53:38 -070010931 /* TPA requires Rx CSUM offloading */
10932 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
Vladislav Zolotarovd43a7e62010-02-17 02:03:40 +000010933 if (!disable_tpa) {
10934 if (!(dev->features & NETIF_F_LRO)) {
10935 dev->features |= NETIF_F_LRO;
10936 bp->flags |= TPA_ENABLE_FLAG;
10937 changed = 1;
10938 }
10939 } else
10940 rc = -EINVAL;
Vladislav Zolotarovdf0f2342008-08-13 15:53:38 -070010941 } else if (dev->features & NETIF_F_LRO) {
10942 dev->features &= ~NETIF_F_LRO;
10943 bp->flags &= ~TPA_ENABLE_FLAG;
10944 changed = 1;
10945 }
10946
10947 if (changed && netif_running(dev)) {
10948 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
10949 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
10950 }
10951
10952 return rc;
10953}
10954
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010955static u32 bnx2x_get_rx_csum(struct net_device *dev)
10956{
10957 struct bnx2x *bp = netdev_priv(dev);
10958
10959 return bp->rx_csum;
10960}
10961
10962static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
10963{
10964 struct bnx2x *bp = netdev_priv(dev);
Vladislav Zolotarovdf0f2342008-08-13 15:53:38 -070010965 int rc = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010966
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000010967 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10968 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
10969 return -EAGAIN;
10970 }
10971
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010972 bp->rx_csum = data;
Vladislav Zolotarovdf0f2342008-08-13 15:53:38 -070010973
10974 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
10975 TPA'ed packets will be discarded due to wrong TCP CSUM */
10976 if (!data) {
10977 u32 flags = ethtool_op_get_flags(dev);
10978
10979 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
10980 }
10981
10982 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010983}
10984
10985static int bnx2x_set_tso(struct net_device *dev, u32 data)
10986{
Eilon Greenstein755735e2008-06-23 20:35:13 -070010987 if (data) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010988 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
Eilon Greenstein755735e2008-06-23 20:35:13 -070010989 dev->features |= NETIF_F_TSO6;
10990 } else {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010991 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
Eilon Greenstein755735e2008-06-23 20:35:13 -070010992 dev->features &= ~NETIF_F_TSO6;
10993 }
10994
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010995 return 0;
10996}
10997
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070010998static const struct {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010999 char string[ETH_GSTRING_LEN];
11000} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011001 { "register_test (offline)" },
11002 { "memory_test (offline)" },
11003 { "loopback_test (offline)" },
11004 { "nvram_test (online)" },
11005 { "interrupt_test (online)" },
11006 { "link_test (online)" },
Eilon Greensteind3d4f492009-02-12 08:36:27 +000011007 { "idle check (online)" }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011008};
11009
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011010static int bnx2x_test_registers(struct bnx2x *bp)
11011{
11012 int idx, i, rc = -ENODEV;
11013 u32 wr_val = 0;
Yitchak Gertner9dabc422008-08-13 15:51:28 -070011014 int port = BP_PORT(bp);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011015 static const struct {
11016 u32 offset0;
11017 u32 offset1;
11018 u32 mask;
11019 } reg_tbl[] = {
11020/* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
11021 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
11022 { HC_REG_AGG_INT_0, 4, 0x000003ff },
11023 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
11024 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
11025 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
11026 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
11027 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
11028 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
11029 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
11030/* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
11031 { QM_REG_CONNNUM_0, 4, 0x000fffff },
11032 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
11033 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
11034 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
11035 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
11036 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
11037 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011038 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
Eilon Greensteinc1f1a062009-07-29 00:20:08 +000011039 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
11040/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011041 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
11042 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
11043 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
11044 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
11045 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
11046 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
11047 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
11048 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
Eilon Greensteinc1f1a062009-07-29 00:20:08 +000011049 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
11050/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011051 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
11052 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
11053 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
11054 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
11055 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
11056 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
11057
11058 { 0xffffffff, 0, 0x00000000 }
11059 };
11060
11061 if (!netif_running(bp->dev))
11062 return rc;
11063
11064 /* Repeat the test twice:
11065 First by writing 0x00000000, second by writing 0xffffffff */
11066 for (idx = 0; idx < 2; idx++) {
11067
11068 switch (idx) {
11069 case 0:
11070 wr_val = 0;
11071 break;
11072 case 1:
11073 wr_val = 0xffffffff;
11074 break;
11075 }
11076
11077 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
11078 u32 offset, mask, save_val, val;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011079
11080 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
11081 mask = reg_tbl[i].mask;
11082
11083 save_val = REG_RD(bp, offset);
11084
11085 REG_WR(bp, offset, wr_val);
11086 val = REG_RD(bp, offset);
11087
11088 /* Restore the original register's value */
11089 REG_WR(bp, offset, save_val);
11090
11091 /* verify that value is as expected value */
11092 if ((val & mask) != (wr_val & mask))
11093 goto test_reg_exit;
11094 }
11095 }
11096
11097 rc = 0;
11098
11099test_reg_exit:
11100 return rc;
11101}
11102
11103static int bnx2x_test_memory(struct bnx2x *bp)
11104{
11105 int i, j, rc = -ENODEV;
11106 u32 val;
11107 static const struct {
11108 u32 offset;
11109 int size;
11110 } mem_tbl[] = {
11111 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
11112 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
11113 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
11114 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
11115 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
11116 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
11117 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
11118
11119 { 0xffffffff, 0 }
11120 };
11121 static const struct {
11122 char *name;
11123 u32 offset;
Yitchak Gertner9dabc422008-08-13 15:51:28 -070011124 u32 e1_mask;
11125 u32 e1h_mask;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011126 } prty_tbl[] = {
Yitchak Gertner9dabc422008-08-13 15:51:28 -070011127 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 },
11128 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 },
11129 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 },
11130 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 },
11131 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 },
11132 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 },
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011133
Yitchak Gertner9dabc422008-08-13 15:51:28 -070011134 { NULL, 0xffffffff, 0, 0 }
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011135 };
11136
11137 if (!netif_running(bp->dev))
11138 return rc;
11139
11140 /* Go through all the memories */
11141 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
11142 for (j = 0; j < mem_tbl[i].size; j++)
11143 REG_RD(bp, mem_tbl[i].offset + j*4);
11144
11145 /* Check the parity status */
11146 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
11147 val = REG_RD(bp, prty_tbl[i].offset);
Yitchak Gertner9dabc422008-08-13 15:51:28 -070011148 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
11149 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011150 DP(NETIF_MSG_HW,
11151 "%s is 0x%x\n", prty_tbl[i].name, val);
11152 goto test_mem_exit;
11153 }
11154 }
11155
11156 rc = 0;
11157
11158test_mem_exit:
11159 return rc;
11160}
11161
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011162static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
11163{
11164 int cnt = 1000;
11165
11166 if (link_up)
11167 while (bnx2x_link_test(bp) && cnt--)
11168 msleep(10);
11169}
11170
11171static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
11172{
11173 unsigned int pkt_size, num_pkts, i;
11174 struct sk_buff *skb;
11175 unsigned char *packet;
Eilon Greensteinca003922009-08-12 22:53:28 -070011176 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011177 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011178 u16 tx_start_idx, tx_idx;
11179 u16 rx_start_idx, rx_idx;
Eilon Greensteinca003922009-08-12 22:53:28 -070011180 u16 pkt_prod, bd_prod;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011181 struct sw_tx_bd *tx_buf;
Eilon Greensteinca003922009-08-12 22:53:28 -070011182 struct eth_tx_start_bd *tx_start_bd;
11183 struct eth_tx_parse_bd *pbd = NULL;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011184 dma_addr_t mapping;
11185 union eth_rx_cqe *cqe;
11186 u8 cqe_fp_flags;
11187 struct sw_rx_bd *rx_buf;
11188 u16 len;
11189 int rc = -ENODEV;
11190
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011191 /* check the loopback mode */
11192 switch (loopback_mode) {
11193 case BNX2X_PHY_LOOPBACK:
11194 if (bp->link_params.loopback_mode != LOOPBACK_XGXS_10)
11195 return -EINVAL;
11196 break;
11197 case BNX2X_MAC_LOOPBACK:
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011198 bp->link_params.loopback_mode = LOOPBACK_BMAC;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011199 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011200 break;
11201 default:
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011202 return -EINVAL;
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011203 }
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011204
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011205 /* prepare the loopback packet */
11206 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
11207 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011208 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
11209 if (!skb) {
11210 rc = -ENOMEM;
11211 goto test_loopback_exit;
11212 }
11213 packet = skb_put(skb, pkt_size);
11214 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
Eilon Greensteinca003922009-08-12 22:53:28 -070011215 memset(packet + ETH_ALEN, 0, ETH_ALEN);
11216 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011217 for (i = ETH_HLEN; i < pkt_size; i++)
11218 packet[i] = (unsigned char) (i & 0xff);
11219
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011220 /* send the loopback packet */
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011221 num_pkts = 0;
Eilon Greensteinca003922009-08-12 22:53:28 -070011222 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
11223 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011224
Eilon Greensteinca003922009-08-12 22:53:28 -070011225 pkt_prod = fp_tx->tx_pkt_prod++;
11226 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
11227 tx_buf->first_bd = fp_tx->tx_bd_prod;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011228 tx_buf->skb = skb;
Eilon Greensteinca003922009-08-12 22:53:28 -070011229 tx_buf->flags = 0;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011230
Eilon Greensteinca003922009-08-12 22:53:28 -070011231 bd_prod = TX_BD(fp_tx->tx_bd_prod);
11232 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
FUJITA Tomonori1a983142010-04-04 01:51:03 +000011233 mapping = dma_map_single(&bp->pdev->dev, skb->data,
11234 skb_headlen(skb), DMA_TO_DEVICE);
Eilon Greensteinca003922009-08-12 22:53:28 -070011235 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
11236 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
11237 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
11238 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
11239 tx_start_bd->vlan = cpu_to_le16(pkt_prod);
11240 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
11241 tx_start_bd->general_data = ((UNICAST_ADDRESS <<
11242 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT) | 1);
11243
11244 /* turn on parsing and get a BD */
11245 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
11246 pbd = &fp_tx->tx_desc_ring[bd_prod].parse_bd;
11247
11248 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011249
Eilon Greenstein58f4c4c2009-01-14 21:23:36 -080011250 wmb();
11251
Eilon Greensteinca003922009-08-12 22:53:28 -070011252 fp_tx->tx_db.data.prod += 2;
11253 barrier();
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011254 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011255
11256 mmiowb();
11257
11258 num_pkts++;
Eilon Greensteinca003922009-08-12 22:53:28 -070011259 fp_tx->tx_bd_prod += 2; /* start + pbd */
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011260
11261 udelay(100);
11262
Eilon Greensteinca003922009-08-12 22:53:28 -070011263 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011264 if (tx_idx != tx_start_idx + num_pkts)
11265 goto test_loopback_exit;
11266
Eilon Greensteinca003922009-08-12 22:53:28 -070011267 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011268 if (rx_idx != rx_start_idx + num_pkts)
11269 goto test_loopback_exit;
11270
Eilon Greensteinca003922009-08-12 22:53:28 -070011271 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011272 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
11273 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
11274 goto test_loopback_rx_exit;
11275
11276 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
11277 if (len != pkt_size)
11278 goto test_loopback_rx_exit;
11279
Eilon Greensteinca003922009-08-12 22:53:28 -070011280 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011281 skb = rx_buf->skb;
11282 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
11283 for (i = ETH_HLEN; i < pkt_size; i++)
11284 if (*(skb->data + i) != (unsigned char) (i & 0xff))
11285 goto test_loopback_rx_exit;
11286
11287 rc = 0;
11288
11289test_loopback_rx_exit:
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011290
Eilon Greensteinca003922009-08-12 22:53:28 -070011291 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
11292 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
11293 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
11294 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011295
11296 /* Update producers */
Eilon Greensteinca003922009-08-12 22:53:28 -070011297 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
11298 fp_rx->rx_sge_prod);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011299
11300test_loopback_exit:
11301 bp->link_params.loopback_mode = LOOPBACK_NONE;
11302
11303 return rc;
11304}
11305
11306static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
11307{
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011308 int rc = 0, res;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011309
Vladislav Zolotarov2145a922010-04-19 01:13:49 +000011310 if (BP_NOMCP(bp))
11311 return rc;
11312
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011313 if (!netif_running(bp->dev))
11314 return BNX2X_LOOPBACK_FAILED;
11315
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070011316 bnx2x_netif_stop(bp, 1);
Eilon Greenstein3910c8a2009-01-22 06:01:32 +000011317 bnx2x_acquire_phy_lock(bp);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011318
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011319 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
11320 if (res) {
11321 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
11322 rc |= BNX2X_PHY_LOOPBACK_FAILED;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011323 }
11324
Eilon Greensteinb5bf9062009-02-12 08:38:08 +000011325 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
11326 if (res) {
11327 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
11328 rc |= BNX2X_MAC_LOOPBACK_FAILED;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011329 }
11330
Eilon Greenstein3910c8a2009-01-22 06:01:32 +000011331 bnx2x_release_phy_lock(bp);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011332 bnx2x_netif_start(bp);
11333
11334 return rc;
11335}
11336
11337#define CRC32_RESIDUAL 0xdebb20e3
11338
11339static int bnx2x_test_nvram(struct bnx2x *bp)
11340{
11341 static const struct {
11342 int offset;
11343 int size;
11344 } nvram_tbl[] = {
11345 { 0, 0x14 }, /* bootstrap */
11346 { 0x14, 0xec }, /* dir */
11347 { 0x100, 0x350 }, /* manuf_info */
11348 { 0x450, 0xf0 }, /* feature_info */
11349 { 0x640, 0x64 }, /* upgrade_key_info */
11350 { 0x6a4, 0x64 },
11351 { 0x708, 0x70 }, /* manuf_key_info */
11352 { 0x778, 0x70 },
11353 { 0, 0 }
11354 };
Eilon Greenstein4781bfa2009-02-12 08:38:17 +000011355 __be32 buf[0x350 / 4];
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011356 u8 *data = (u8 *)buf;
11357 int i, rc;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000011358 u32 magic, crc;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011359
Vladislav Zolotarov2145a922010-04-19 01:13:49 +000011360 if (BP_NOMCP(bp))
11361 return 0;
11362
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011363 rc = bnx2x_nvram_read(bp, 0, data, 4);
11364 if (rc) {
Eilon Greensteinf5372252009-02-12 08:38:30 +000011365 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011366 goto test_nvram_exit;
11367 }
11368
11369 magic = be32_to_cpu(buf[0]);
11370 if (magic != 0x669955aa) {
11371 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
11372 rc = -ENODEV;
11373 goto test_nvram_exit;
11374 }
11375
11376 for (i = 0; nvram_tbl[i].size; i++) {
11377
11378 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
11379 nvram_tbl[i].size);
11380 if (rc) {
11381 DP(NETIF_MSG_PROBE,
Eilon Greensteinf5372252009-02-12 08:38:30 +000011382 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011383 goto test_nvram_exit;
11384 }
11385
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000011386 crc = ether_crc_le(nvram_tbl[i].size, data);
11387 if (crc != CRC32_RESIDUAL) {
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011388 DP(NETIF_MSG_PROBE,
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000011389 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011390 rc = -ENODEV;
11391 goto test_nvram_exit;
11392 }
11393 }
11394
11395test_nvram_exit:
11396 return rc;
11397}
11398
11399static int bnx2x_test_intr(struct bnx2x *bp)
11400{
11401 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
11402 int i, rc;
11403
11404 if (!netif_running(bp->dev))
11405 return -ENODEV;
11406
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -080011407 config->hdr.length = 0;
Eilon Greensteinaf246402009-01-14 06:43:59 +000011408 if (CHIP_IS_E1(bp))
Vladislav Zolotarov0c43f432010-02-17 02:04:00 +000011409 /* use last unicast entries */
11410 config->hdr.offset = (BP_PORT(bp) ? 63 : 31);
Eilon Greensteinaf246402009-01-14 06:43:59 +000011411 else
11412 config->hdr.offset = BP_FUNC(bp);
Eilon Greenstein0626b892009-02-12 08:38:14 +000011413 config->hdr.client_id = bp->fp->cl_id;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011414 config->hdr.reserved1 = 0;
11415
Michael Chane665bfd2009-10-10 13:46:54 +000011416 bp->set_mac_pending++;
11417 smp_wmb();
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011418 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
11419 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
11420 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
11421 if (rc == 0) {
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011422 for (i = 0; i < 10; i++) {
11423 if (!bp->set_mac_pending)
11424 break;
Michael Chane665bfd2009-10-10 13:46:54 +000011425 smp_rmb();
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011426 msleep_interruptible(10);
11427 }
11428 if (i == 10)
11429 rc = -ENODEV;
11430 }
11431
11432 return rc;
11433}
11434
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011435static void bnx2x_self_test(struct net_device *dev,
11436 struct ethtool_test *etest, u64 *buf)
11437{
11438 struct bnx2x *bp = netdev_priv(dev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011439
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000011440 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11441 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
11442 etest->flags |= ETH_TEST_FL_FAILED;
11443 return;
11444 }
11445
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011446 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
11447
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011448 if (!netif_running(dev))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011449 return;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011450
Eilon Greenstein33471622008-08-13 15:59:08 -070011451 /* offline tests are not supported in MF mode */
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011452 if (IS_E1HMF(bp))
11453 etest->flags &= ~ETH_TEST_FL_OFFLINE;
11454
11455 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Eilon Greenstein279abdf2009-07-21 05:47:22 +000011456 int port = BP_PORT(bp);
11457 u32 val;
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011458 u8 link_up;
11459
Eilon Greenstein279abdf2009-07-21 05:47:22 +000011460 /* save current value of input enable for TX port IF */
11461 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
11462 /* disable input for TX port IF */
11463 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
11464
Eilon Greenstein061bc702009-10-15 00:18:47 -070011465 link_up = (bnx2x_link_test(bp) == 0);
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011466 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
11467 bnx2x_nic_load(bp, LOAD_DIAG);
11468 /* wait until link state is restored */
11469 bnx2x_wait_for_link(bp, link_up);
11470
11471 if (bnx2x_test_registers(bp) != 0) {
11472 buf[0] = 1;
11473 etest->flags |= ETH_TEST_FL_FAILED;
11474 }
11475 if (bnx2x_test_memory(bp) != 0) {
11476 buf[1] = 1;
11477 etest->flags |= ETH_TEST_FL_FAILED;
11478 }
11479 buf[2] = bnx2x_test_loopback(bp, link_up);
11480 if (buf[2] != 0)
11481 etest->flags |= ETH_TEST_FL_FAILED;
11482
11483 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
Eilon Greenstein279abdf2009-07-21 05:47:22 +000011484
11485 /* restore input for TX port IF */
11486 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
11487
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011488 bnx2x_nic_load(bp, LOAD_NORMAL);
11489 /* wait until link state is restored */
11490 bnx2x_wait_for_link(bp, link_up);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011491 }
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011492 if (bnx2x_test_nvram(bp) != 0) {
11493 buf[3] = 1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011494 etest->flags |= ETH_TEST_FL_FAILED;
11495 }
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011496 if (bnx2x_test_intr(bp) != 0) {
11497 buf[4] = 1;
11498 etest->flags |= ETH_TEST_FL_FAILED;
11499 }
11500 if (bp->port.pmf)
11501 if (bnx2x_link_test(bp) != 0) {
11502 buf[5] = 1;
11503 etest->flags |= ETH_TEST_FL_FAILED;
11504 }
Yitchak Gertnerf3c87cd2008-06-23 20:35:51 -070011505
11506#ifdef BNX2X_EXTRA_DEBUG
11507 bnx2x_panic_dump(bp);
11508#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011509}
11510
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011511static const struct {
11512 long offset;
11513 int size;
Eilon Greensteinde832a52009-02-12 08:36:33 +000011514 u8 string[ETH_GSTRING_LEN];
11515} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
11516/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
11517 { Q_STATS_OFFSET32(error_bytes_received_hi),
11518 8, "[%d]: rx_error_bytes" },
11519 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
11520 8, "[%d]: rx_ucast_packets" },
11521 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
11522 8, "[%d]: rx_mcast_packets" },
11523 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
11524 8, "[%d]: rx_bcast_packets" },
11525 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
11526 { Q_STATS_OFFSET32(rx_err_discard_pkt),
11527 4, "[%d]: rx_phy_ip_err_discards"},
11528 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
11529 4, "[%d]: rx_skb_alloc_discard" },
11530 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
11531
11532/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
11533 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
11534 8, "[%d]: tx_packets" }
11535};
11536
11537static const struct {
11538 long offset;
11539 int size;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011540 u32 flags;
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011541#define STATS_FLAGS_PORT 1
11542#define STATS_FLAGS_FUNC 2
Eilon Greensteinde832a52009-02-12 08:36:33 +000011543#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011544 u8 string[ETH_GSTRING_LEN];
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011545} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
Eilon Greensteinde832a52009-02-12 08:36:33 +000011546/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
11547 8, STATS_FLAGS_BOTH, "rx_bytes" },
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011548 { STATS_OFFSET32(error_bytes_received_hi),
Eilon Greensteinde832a52009-02-12 08:36:33 +000011549 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011550 { STATS_OFFSET32(total_unicast_packets_received_hi),
Eilon Greensteinde832a52009-02-12 08:36:33 +000011551 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011552 { STATS_OFFSET32(total_multicast_packets_received_hi),
Eilon Greensteinde832a52009-02-12 08:36:33 +000011553 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011554 { STATS_OFFSET32(total_broadcast_packets_received_hi),
Eilon Greensteinde832a52009-02-12 08:36:33 +000011555 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011556 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011557 8, STATS_FLAGS_PORT, "rx_crc_errors" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011558 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011559 8, STATS_FLAGS_PORT, "rx_align_errors" },
Eilon Greensteinde832a52009-02-12 08:36:33 +000011560 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
11561 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
11562 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
11563 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
11564/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
11565 8, STATS_FLAGS_PORT, "rx_fragments" },
11566 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
11567 8, STATS_FLAGS_PORT, "rx_jabbers" },
11568 { STATS_OFFSET32(no_buff_discard_hi),
11569 8, STATS_FLAGS_BOTH, "rx_discards" },
11570 { STATS_OFFSET32(mac_filter_discard),
11571 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
11572 { STATS_OFFSET32(xxoverflow_discard),
11573 4, STATS_FLAGS_PORT, "rx_fw_discards" },
11574 { STATS_OFFSET32(brb_drop_hi),
11575 8, STATS_FLAGS_PORT, "rx_brb_discard" },
11576 { STATS_OFFSET32(brb_truncate_hi),
11577 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
11578 { STATS_OFFSET32(pause_frames_received_hi),
11579 8, STATS_FLAGS_PORT, "rx_pause_frames" },
11580 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
11581 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
11582 { STATS_OFFSET32(nig_timer_max),
11583 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
11584/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
11585 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
11586 { STATS_OFFSET32(rx_skb_alloc_failed),
11587 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
11588 { STATS_OFFSET32(hw_csum_err),
11589 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
11590
11591 { STATS_OFFSET32(total_bytes_transmitted_hi),
11592 8, STATS_FLAGS_BOTH, "tx_bytes" },
11593 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
11594 8, STATS_FLAGS_PORT, "tx_error_bytes" },
11595 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
11596 8, STATS_FLAGS_BOTH, "tx_packets" },
11597 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
11598 8, STATS_FLAGS_PORT, "tx_mac_errors" },
11599 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
11600 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011601 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011602 8, STATS_FLAGS_PORT, "tx_single_collisions" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011603 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011604 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
Eilon Greensteinde832a52009-02-12 08:36:33 +000011605/* 30 */{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011606 8, STATS_FLAGS_PORT, "tx_deferred" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011607 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011608 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011609 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011610 8, STATS_FLAGS_PORT, "tx_late_collisions" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011611 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011612 8, STATS_FLAGS_PORT, "tx_total_collisions" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011613 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011614 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011615 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011616 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011617 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011618 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011619 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011620 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011621 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011622 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011623 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011624 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
Eilon Greensteinde832a52009-02-12 08:36:33 +000011625/* 40 */{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011626 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
Eilon Greensteinde832a52009-02-12 08:36:33 +000011627 { STATS_OFFSET32(pause_frames_sent_hi),
11628 8, STATS_FLAGS_PORT, "tx_pause_frames" }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011629};
11630
Eilon Greensteinde832a52009-02-12 08:36:33 +000011631#define IS_PORT_STAT(i) \
11632 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
11633#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
11634#define IS_E1HMF_MODE_STAT(bp) \
Joe Perches7995c642010-02-17 15:01:52 +000011635 (IS_E1HMF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
Yitchak Gertner66e855f2008-08-13 15:49:05 -070011636
Ben Hutchings15f0a392009-10-01 11:58:24 +000011637static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
11638{
11639 struct bnx2x *bp = netdev_priv(dev);
11640 int i, num_stats;
11641
11642 switch(stringset) {
11643 case ETH_SS_STATS:
11644 if (is_multi(bp)) {
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011645 num_stats = BNX2X_NUM_Q_STATS * bp->num_queues;
Ben Hutchings15f0a392009-10-01 11:58:24 +000011646 if (!IS_E1HMF_MODE_STAT(bp))
11647 num_stats += BNX2X_NUM_STATS;
11648 } else {
11649 if (IS_E1HMF_MODE_STAT(bp)) {
11650 num_stats = 0;
11651 for (i = 0; i < BNX2X_NUM_STATS; i++)
11652 if (IS_FUNC_STAT(i))
11653 num_stats++;
11654 } else
11655 num_stats = BNX2X_NUM_STATS;
11656 }
11657 return num_stats;
11658
11659 case ETH_SS_TEST:
11660 return BNX2X_NUM_TESTS;
11661
11662 default:
11663 return -EINVAL;
11664 }
11665}
11666
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011667static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
11668{
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011669 struct bnx2x *bp = netdev_priv(dev);
Eilon Greensteinde832a52009-02-12 08:36:33 +000011670 int i, j, k;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011671
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011672 switch (stringset) {
11673 case ETH_SS_STATS:
Eilon Greensteinde832a52009-02-12 08:36:33 +000011674 if (is_multi(bp)) {
11675 k = 0;
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011676 for_each_queue(bp, i) {
Eilon Greensteinde832a52009-02-12 08:36:33 +000011677 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
11678 sprintf(buf + (k + j)*ETH_GSTRING_LEN,
11679 bnx2x_q_stats_arr[j].string, i);
11680 k += BNX2X_NUM_Q_STATS;
11681 }
11682 if (IS_E1HMF_MODE_STAT(bp))
11683 break;
11684 for (j = 0; j < BNX2X_NUM_STATS; j++)
11685 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
11686 bnx2x_stats_arr[j].string);
11687 } else {
11688 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
11689 if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
11690 continue;
11691 strcpy(buf + j*ETH_GSTRING_LEN,
11692 bnx2x_stats_arr[i].string);
11693 j++;
11694 }
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011695 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011696 break;
11697
11698 case ETH_SS_TEST:
11699 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
11700 break;
11701 }
11702}
11703
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011704static void bnx2x_get_ethtool_stats(struct net_device *dev,
11705 struct ethtool_stats *stats, u64 *buf)
11706{
11707 struct bnx2x *bp = netdev_priv(dev);
Eilon Greensteinde832a52009-02-12 08:36:33 +000011708 u32 *hw_stats, *offset;
11709 int i, j, k;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011710
Eilon Greensteinde832a52009-02-12 08:36:33 +000011711 if (is_multi(bp)) {
11712 k = 0;
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011713 for_each_queue(bp, i) {
Eilon Greensteinde832a52009-02-12 08:36:33 +000011714 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
11715 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
11716 if (bnx2x_q_stats_arr[j].size == 0) {
11717 /* skip this counter */
11718 buf[k + j] = 0;
11719 continue;
11720 }
11721 offset = (hw_stats +
11722 bnx2x_q_stats_arr[j].offset);
11723 if (bnx2x_q_stats_arr[j].size == 4) {
11724 /* 4-byte counter */
11725 buf[k + j] = (u64) *offset;
11726 continue;
11727 }
11728 /* 8-byte counter */
11729 buf[k + j] = HILO_U64(*offset, *(offset + 1));
11730 }
11731 k += BNX2X_NUM_Q_STATS;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011732 }
Eilon Greensteinde832a52009-02-12 08:36:33 +000011733 if (IS_E1HMF_MODE_STAT(bp))
11734 return;
11735 hw_stats = (u32 *)&bp->eth_stats;
11736 for (j = 0; j < BNX2X_NUM_STATS; j++) {
11737 if (bnx2x_stats_arr[j].size == 0) {
11738 /* skip this counter */
11739 buf[k + j] = 0;
11740 continue;
11741 }
11742 offset = (hw_stats + bnx2x_stats_arr[j].offset);
11743 if (bnx2x_stats_arr[j].size == 4) {
11744 /* 4-byte counter */
11745 buf[k + j] = (u64) *offset;
11746 continue;
11747 }
11748 /* 8-byte counter */
11749 buf[k + j] = HILO_U64(*offset, *(offset + 1));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011750 }
Eilon Greensteinde832a52009-02-12 08:36:33 +000011751 } else {
11752 hw_stats = (u32 *)&bp->eth_stats;
11753 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
11754 if (IS_E1HMF_MODE_STAT(bp) && IS_PORT_STAT(i))
11755 continue;
11756 if (bnx2x_stats_arr[i].size == 0) {
11757 /* skip this counter */
11758 buf[j] = 0;
11759 j++;
11760 continue;
11761 }
11762 offset = (hw_stats + bnx2x_stats_arr[i].offset);
11763 if (bnx2x_stats_arr[i].size == 4) {
11764 /* 4-byte counter */
11765 buf[j] = (u64) *offset;
11766 j++;
11767 continue;
11768 }
11769 /* 8-byte counter */
11770 buf[j] = HILO_U64(*offset, *(offset + 1));
11771 j++;
11772 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011773 }
11774}
11775
11776static int bnx2x_phys_id(struct net_device *dev, u32 data)
11777{
11778 struct bnx2x *bp = netdev_priv(dev);
11779 int i;
11780
Eilon Greenstein34f80b02008-06-23 20:33:01 -070011781 if (!netif_running(dev))
11782 return 0;
11783
11784 if (!bp->port.pmf)
11785 return 0;
11786
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011787 if (data == 0)
11788 data = 2;
11789
11790 for (i = 0; i < (data * 2); i++) {
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070011791 if ((i % 2) == 0)
Yaniv Rosner7846e472009-11-05 19:18:07 +020011792 bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
11793 SPEED_1000);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070011794 else
Yaniv Rosner7846e472009-11-05 19:18:07 +020011795 bnx2x_set_led(&bp->link_params, LED_MODE_OFF, 0);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070011796
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011797 msleep_interruptible(500);
11798 if (signal_pending(current))
11799 break;
11800 }
11801
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070011802 if (bp->link_vars.link_up)
Yaniv Rosner7846e472009-11-05 19:18:07 +020011803 bnx2x_set_led(&bp->link_params, LED_MODE_OPER,
11804 bp->link_vars.line_speed);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011805
11806 return 0;
11807}
11808
Stephen Hemminger0fc0b732009-09-02 01:03:33 -070011809static const struct ethtool_ops bnx2x_ethtool_ops = {
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -070011810 .get_settings = bnx2x_get_settings,
11811 .set_settings = bnx2x_set_settings,
11812 .get_drvinfo = bnx2x_get_drvinfo,
Eilon Greenstein0a64ea52009-03-02 08:01:12 +000011813 .get_regs_len = bnx2x_get_regs_len,
11814 .get_regs = bnx2x_get_regs,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011815 .get_wol = bnx2x_get_wol,
11816 .set_wol = bnx2x_set_wol,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -070011817 .get_msglevel = bnx2x_get_msglevel,
11818 .set_msglevel = bnx2x_set_msglevel,
11819 .nway_reset = bnx2x_nway_reset,
Naohiro Ooiwa01e53292009-06-30 12:44:19 -070011820 .get_link = bnx2x_get_link,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -070011821 .get_eeprom_len = bnx2x_get_eeprom_len,
11822 .get_eeprom = bnx2x_get_eeprom,
11823 .set_eeprom = bnx2x_set_eeprom,
11824 .get_coalesce = bnx2x_get_coalesce,
11825 .set_coalesce = bnx2x_set_coalesce,
11826 .get_ringparam = bnx2x_get_ringparam,
11827 .set_ringparam = bnx2x_set_ringparam,
11828 .get_pauseparam = bnx2x_get_pauseparam,
11829 .set_pauseparam = bnx2x_set_pauseparam,
11830 .get_rx_csum = bnx2x_get_rx_csum,
11831 .set_rx_csum = bnx2x_set_rx_csum,
11832 .get_tx_csum = ethtool_op_get_tx_csum,
Eilon Greenstein755735e2008-06-23 20:35:13 -070011833 .set_tx_csum = ethtool_op_set_tx_hw_csum,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -070011834 .set_flags = bnx2x_set_flags,
11835 .get_flags = ethtool_op_get_flags,
11836 .get_sg = ethtool_op_get_sg,
11837 .set_sg = ethtool_op_set_sg,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011838 .get_tso = ethtool_op_get_tso,
11839 .set_tso = bnx2x_set_tso,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -070011840 .self_test = bnx2x_self_test,
Ben Hutchings15f0a392009-10-01 11:58:24 +000011841 .get_sset_count = bnx2x_get_sset_count,
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -070011842 .get_strings = bnx2x_get_strings,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011843 .phys_id = bnx2x_phys_id,
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070011844 .get_ethtool_stats = bnx2x_get_ethtool_stats,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011845};
11846
11847/* end of ethtool_ops */
11848
11849/****************************************************************************
11850* General service functions
11851****************************************************************************/
11852
11853static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
11854{
11855 u16 pmcsr;
11856
11857 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
11858
11859 switch (state) {
11860 case PCI_D0:
Eilon Greenstein34f80b02008-06-23 20:33:01 -070011861 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011862 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
11863 PCI_PM_CTRL_PME_STATUS));
11864
11865 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
Eilon Greenstein33471622008-08-13 15:59:08 -070011866 /* delay required during transition out of D3hot */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011867 msleep(20);
11868 break;
11869
11870 case PCI_D3hot:
11871 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11872 pmcsr |= 3;
11873
11874 if (bp->wol)
11875 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
11876
11877 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
11878 pmcsr);
11879
11880 /* No more memory access after this point until
11881 * device is brought back to D0.
11882 */
11883 break;
11884
11885 default:
11886 return -EINVAL;
11887 }
11888 return 0;
11889}
11890
Eilon Greenstein237907c2009-01-14 06:42:44 +000011891static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
11892{
11893 u16 rx_cons_sb;
11894
11895 /* Tell compiler that status block fields can change */
11896 barrier();
11897 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
11898 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
11899 rx_cons_sb++;
11900 return (fp->rx_comp_cons != rx_cons_sb);
11901}
11902
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011903/*
11904 * net_device service functions
11905 */
11906
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011907static int bnx2x_poll(struct napi_struct *napi, int budget)
11908{
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011909 int work_done = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011910 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
11911 napi);
11912 struct bnx2x *bp = fp->bp;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011913
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011914 while (1) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011915#ifdef BNX2X_STOP_ON_ERROR
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011916 if (unlikely(bp->panic)) {
11917 napi_complete(napi);
11918 return 0;
11919 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011920#endif
11921
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011922 if (bnx2x_has_tx_work(fp))
11923 bnx2x_tx_int(fp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011924
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011925 if (bnx2x_has_rx_work(fp)) {
11926 work_done += bnx2x_rx_int(fp, budget - work_done);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011927
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011928 /* must not complete if we consumed full budget */
11929 if (work_done >= budget)
11930 break;
11931 }
Eilon Greenstein356e2382009-02-12 08:38:32 +000011932
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000011933 /* Fall out from the NAPI loop if needed */
11934 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
11935 bnx2x_update_fpsb_idx(fp);
11936 /* bnx2x_has_rx_work() reads the status block, thus we need
11937 * to ensure that status block indices have been actually read
11938 * (bnx2x_update_fpsb_idx) prior to this check
11939 * (bnx2x_has_rx_work) so that we won't write the "newer"
11940 * value of the status block to IGU (if there was a DMA right
11941 * after bnx2x_has_rx_work and if there is no rmb, the memory
11942 * reading (bnx2x_update_fpsb_idx) may be postponed to right
11943 * before bnx2x_ack_sb). In this case there will never be
11944 * another interrupt until there is another update of the
11945 * status block, while there is still unhandled work.
11946 */
11947 rmb();
11948
11949 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
11950 napi_complete(napi);
11951 /* Re-enable interrupts */
11952 bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID,
11953 le16_to_cpu(fp->fp_c_idx),
11954 IGU_INT_NOP, 1);
11955 bnx2x_ack_sb(bp, fp->sb_id, USTORM_ID,
11956 le16_to_cpu(fp->fp_u_idx),
11957 IGU_INT_ENABLE, 1);
11958 break;
11959 }
11960 }
Eilon Greenstein8534f322009-03-02 07:59:45 +000011961 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011962
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011963 return work_done;
11964}
11965
Eilon Greenstein755735e2008-06-23 20:35:13 -070011966
11967/* we split the first BD into headers and data BDs
Eilon Greenstein33471622008-08-13 15:59:08 -070011968 * to ease the pain of our fellow microcode engineers
Eilon Greenstein755735e2008-06-23 20:35:13 -070011969 * we use one mapping for both BDs
11970 * So far this has only been observed to happen
11971 * in Other Operating Systems(TM)
11972 */
11973static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
11974 struct bnx2x_fastpath *fp,
Eilon Greensteinca003922009-08-12 22:53:28 -070011975 struct sw_tx_bd *tx_buf,
11976 struct eth_tx_start_bd **tx_bd, u16 hlen,
Eilon Greenstein755735e2008-06-23 20:35:13 -070011977 u16 bd_prod, int nbd)
11978{
Eilon Greensteinca003922009-08-12 22:53:28 -070011979 struct eth_tx_start_bd *h_tx_bd = *tx_bd;
Eilon Greenstein755735e2008-06-23 20:35:13 -070011980 struct eth_tx_bd *d_tx_bd;
11981 dma_addr_t mapping;
11982 int old_len = le16_to_cpu(h_tx_bd->nbytes);
11983
11984 /* first fix first BD */
11985 h_tx_bd->nbd = cpu_to_le16(nbd);
11986 h_tx_bd->nbytes = cpu_to_le16(hlen);
11987
11988 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d "
11989 "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi,
11990 h_tx_bd->addr_lo, h_tx_bd->nbd);
11991
11992 /* now get a new data BD
11993 * (after the pbd) and fill it */
11994 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
Eilon Greensteinca003922009-08-12 22:53:28 -070011995 d_tx_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
Eilon Greenstein755735e2008-06-23 20:35:13 -070011996
11997 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
11998 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
11999
12000 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
12001 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
12002 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
Eilon Greensteinca003922009-08-12 22:53:28 -070012003
12004 /* this marks the BD as one that has no individual mapping */
12005 tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
12006
Eilon Greenstein755735e2008-06-23 20:35:13 -070012007 DP(NETIF_MSG_TX_QUEUED,
12008 "TSO split data size is %d (%x:%x)\n",
12009 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
12010
Eilon Greensteinca003922009-08-12 22:53:28 -070012011 /* update tx_bd */
12012 *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012013
12014 return bd_prod;
12015}
12016
12017static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
12018{
12019 if (fix > 0)
12020 csum = (u16) ~csum_fold(csum_sub(csum,
12021 csum_partial(t_header - fix, fix, 0)));
12022
12023 else if (fix < 0)
12024 csum = (u16) ~csum_fold(csum_add(csum,
12025 csum_partial(t_header, -fix, 0)));
12026
12027 return swab16(csum);
12028}
12029
12030static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
12031{
12032 u32 rc;
12033
12034 if (skb->ip_summed != CHECKSUM_PARTIAL)
12035 rc = XMIT_PLAIN;
12036
12037 else {
Eilon Greenstein4781bfa2009-02-12 08:38:17 +000012038 if (skb->protocol == htons(ETH_P_IPV6)) {
Eilon Greenstein755735e2008-06-23 20:35:13 -070012039 rc = XMIT_CSUM_V6;
12040 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
12041 rc |= XMIT_CSUM_TCP;
12042
12043 } else {
12044 rc = XMIT_CSUM_V4;
12045 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
12046 rc |= XMIT_CSUM_TCP;
12047 }
12048 }
12049
12050 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
Eilon Greensteind6a2f982009-11-09 06:09:22 +000012051 rc |= (XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP);
Eilon Greenstein755735e2008-06-23 20:35:13 -070012052
12053 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
Eilon Greensteind6a2f982009-11-09 06:09:22 +000012054 rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6);
Eilon Greenstein755735e2008-06-23 20:35:13 -070012055
12056 return rc;
12057}
12058
Eilon Greenstein632da4d2009-01-14 06:44:10 +000012059#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
Eilon Greensteinf5372252009-02-12 08:38:30 +000012060/* check if packet requires linearization (packet is too fragmented)
12061 no need to check fragmentation if page size > 8K (there will be no
12062 violation to FW restrictions) */
Eilon Greenstein755735e2008-06-23 20:35:13 -070012063static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
12064 u32 xmit_type)
12065{
12066 int to_copy = 0;
12067 int hlen = 0;
12068 int first_bd_sz = 0;
12069
12070 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
12071 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
12072
12073 if (xmit_type & XMIT_GSO) {
12074 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
12075 /* Check if LSO packet needs to be copied:
12076 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
12077 int wnd_size = MAX_FETCH_BD - 3;
Eilon Greenstein33471622008-08-13 15:59:08 -070012078 /* Number of windows to check */
Eilon Greenstein755735e2008-06-23 20:35:13 -070012079 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
12080 int wnd_idx = 0;
12081 int frag_idx = 0;
12082 u32 wnd_sum = 0;
12083
12084 /* Headers length */
12085 hlen = (int)(skb_transport_header(skb) - skb->data) +
12086 tcp_hdrlen(skb);
12087
12088 /* Amount of data (w/o headers) on linear part of SKB*/
12089 first_bd_sz = skb_headlen(skb) - hlen;
12090
12091 wnd_sum = first_bd_sz;
12092
12093 /* Calculate the first sum - it's special */
12094 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
12095 wnd_sum +=
12096 skb_shinfo(skb)->frags[frag_idx].size;
12097
12098 /* If there was data on linear skb data - check it */
12099 if (first_bd_sz > 0) {
12100 if (unlikely(wnd_sum < lso_mss)) {
12101 to_copy = 1;
12102 goto exit_lbl;
12103 }
12104
12105 wnd_sum -= first_bd_sz;
12106 }
12107
12108 /* Others are easier: run through the frag list and
12109 check all windows */
12110 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
12111 wnd_sum +=
12112 skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1].size;
12113
12114 if (unlikely(wnd_sum < lso_mss)) {
12115 to_copy = 1;
12116 break;
12117 }
12118 wnd_sum -=
12119 skb_shinfo(skb)->frags[wnd_idx].size;
12120 }
Eilon Greenstein755735e2008-06-23 20:35:13 -070012121 } else {
12122 /* in non-LSO too fragmented packet should always
12123 be linearized */
12124 to_copy = 1;
12125 }
12126 }
12127
12128exit_lbl:
12129 if (unlikely(to_copy))
12130 DP(NETIF_MSG_TX_QUEUED,
12131 "Linearization IS REQUIRED for %s packet. "
12132 "num_frags %d hlen %d first_bd_sz %d\n",
12133 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
12134 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
12135
12136 return to_copy;
12137}
Eilon Greenstein632da4d2009-01-14 06:44:10 +000012138#endif
Eilon Greenstein755735e2008-06-23 20:35:13 -070012139
12140/* called with netif_tx_lock
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012141 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
Eilon Greenstein755735e2008-06-23 20:35:13 -070012142 * netif_wake_queue()
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012143 */
Stephen Hemminger613573252009-08-31 19:50:58 +000012144static netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012145{
12146 struct bnx2x *bp = netdev_priv(dev);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000012147 struct bnx2x_fastpath *fp;
Eilon Greenstein555f6c72009-02-12 08:36:11 +000012148 struct netdev_queue *txq;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012149 struct sw_tx_bd *tx_buf;
Eilon Greensteinca003922009-08-12 22:53:28 -070012150 struct eth_tx_start_bd *tx_start_bd;
12151 struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012152 struct eth_tx_parse_bd *pbd = NULL;
12153 u16 pkt_prod, bd_prod;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012154 int nbd, fp_index;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012155 dma_addr_t mapping;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012156 u32 xmit_type = bnx2x_xmit_type(bp, skb);
Eilon Greenstein755735e2008-06-23 20:35:13 -070012157 int i;
12158 u8 hlen = 0;
Eilon Greensteinca003922009-08-12 22:53:28 -070012159 __le16 pkt_size = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012160
12161#ifdef BNX2X_STOP_ON_ERROR
12162 if (unlikely(bp->panic))
12163 return NETDEV_TX_BUSY;
12164#endif
12165
Eilon Greenstein555f6c72009-02-12 08:36:11 +000012166 fp_index = skb_get_queue_mapping(skb);
12167 txq = netdev_get_tx_queue(dev, fp_index);
12168
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000012169 fp = &bp->fp[fp_index];
Eilon Greenstein755735e2008-06-23 20:35:13 -070012170
Yitchak Gertner231fd582008-08-25 15:27:06 -070012171 if (unlikely(bnx2x_tx_avail(fp) < (skb_shinfo(skb)->nr_frags + 3))) {
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000012172 fp->eth_q_stats.driver_xoff++;
Eilon Greenstein555f6c72009-02-12 08:36:11 +000012173 netif_tx_stop_queue(txq);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012174 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
12175 return NETDEV_TX_BUSY;
12176 }
12177
Eilon Greenstein755735e2008-06-23 20:35:13 -070012178 DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x protocol %x protocol(%x,%x)"
12179 " gso type %x xmit_type %x\n",
12180 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
12181 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
12182
Eilon Greenstein632da4d2009-01-14 06:44:10 +000012183#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
Eilon Greensteinf5372252009-02-12 08:38:30 +000012184 /* First, check if we need to linearize the skb (due to FW
12185 restrictions). No need to check fragmentation if page size > 8K
12186 (there will be no violation to FW restrictions) */
Eilon Greenstein755735e2008-06-23 20:35:13 -070012187 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
12188 /* Statistics of linearization */
12189 bp->lin_cnt++;
12190 if (skb_linearize(skb) != 0) {
12191 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
12192 "silently dropping this SKB\n");
12193 dev_kfree_skb_any(skb);
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -070012194 return NETDEV_TX_OK;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012195 }
12196 }
Eilon Greenstein632da4d2009-01-14 06:44:10 +000012197#endif
Eilon Greenstein755735e2008-06-23 20:35:13 -070012198
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012199 /*
Eilon Greenstein755735e2008-06-23 20:35:13 -070012200 Please read carefully. First we use one BD which we mark as start,
Eilon Greensteinca003922009-08-12 22:53:28 -070012201 then we have a parsing info BD (used for TSO or xsum),
Eilon Greenstein755735e2008-06-23 20:35:13 -070012202 and only then we have the rest of the TSO BDs.
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012203 (don't forget to mark the last one as last,
12204 and to unmap only AFTER you write to the BD ...)
Eilon Greenstein755735e2008-06-23 20:35:13 -070012205 And above all, all pdb sizes are in words - NOT DWORDS!
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012206 */
12207
12208 pkt_prod = fp->tx_pkt_prod++;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012209 bd_prod = TX_BD(fp->tx_bd_prod);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012210
Eilon Greenstein755735e2008-06-23 20:35:13 -070012211 /* get a tx_buf and first BD */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012212 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
Eilon Greensteinca003922009-08-12 22:53:28 -070012213 tx_start_bd = &fp->tx_desc_ring[bd_prod].start_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012214
Eilon Greensteinca003922009-08-12 22:53:28 -070012215 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
12216 tx_start_bd->general_data = (UNICAST_ADDRESS <<
12217 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
Eilon Greenstein3196a882008-08-13 15:58:49 -070012218 /* header nbd */
Eilon Greensteinca003922009-08-12 22:53:28 -070012219 tx_start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012220
Eilon Greenstein755735e2008-06-23 20:35:13 -070012221 /* remember the first BD of the packet */
12222 tx_buf->first_bd = fp->tx_bd_prod;
12223 tx_buf->skb = skb;
Eilon Greensteinca003922009-08-12 22:53:28 -070012224 tx_buf->flags = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012225
12226 DP(NETIF_MSG_TX_QUEUED,
12227 "sending pkt %u @%p next_idx %u bd %u @%p\n",
Eilon Greensteinca003922009-08-12 22:53:28 -070012228 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012229
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080012230#ifdef BCM_VLAN
12231 if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb) &&
12232 (bp->flags & HW_VLAN_TX_FLAG)) {
Eilon Greensteinca003922009-08-12 22:53:28 -070012233 tx_start_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
12234 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012235 } else
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080012236#endif
Eilon Greensteinca003922009-08-12 22:53:28 -070012237 tx_start_bd->vlan = cpu_to_le16(pkt_prod);
Eilon Greenstein755735e2008-06-23 20:35:13 -070012238
Eilon Greensteinca003922009-08-12 22:53:28 -070012239 /* turn on parsing and get a BD */
12240 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
12241 pbd = &fp->tx_desc_ring[bd_prod].parse_bd;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012242
Eilon Greensteinca003922009-08-12 22:53:28 -070012243 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
Eilon Greenstein755735e2008-06-23 20:35:13 -070012244
12245 if (xmit_type & XMIT_CSUM) {
Eilon Greensteinca003922009-08-12 22:53:28 -070012246 hlen = (skb_network_header(skb) - skb->data) / 2;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012247
12248 /* for now NS flag is not used in Linux */
Eilon Greenstein4781bfa2009-02-12 08:38:17 +000012249 pbd->global_data =
12250 (hlen | ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
12251 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
Eilon Greenstein755735e2008-06-23 20:35:13 -070012252
12253 pbd->ip_hlen = (skb_transport_header(skb) -
12254 skb_network_header(skb)) / 2;
12255
12256 hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
12257
12258 pbd->total_hlen = cpu_to_le16(hlen);
Eilon Greensteinca003922009-08-12 22:53:28 -070012259 hlen = hlen*2;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012260
Eilon Greensteinca003922009-08-12 22:53:28 -070012261 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012262
12263 if (xmit_type & XMIT_CSUM_V4)
Eilon Greensteinca003922009-08-12 22:53:28 -070012264 tx_start_bd->bd_flags.as_bitfield |=
Eilon Greenstein755735e2008-06-23 20:35:13 -070012265 ETH_TX_BD_FLAGS_IP_CSUM;
12266 else
Eilon Greensteinca003922009-08-12 22:53:28 -070012267 tx_start_bd->bd_flags.as_bitfield |=
12268 ETH_TX_BD_FLAGS_IPV6;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012269
12270 if (xmit_type & XMIT_CSUM_TCP) {
12271 pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
12272
12273 } else {
12274 s8 fix = SKB_CS_OFF(skb); /* signed! */
12275
Eilon Greensteinca003922009-08-12 22:53:28 -070012276 pbd->global_data |= ETH_TX_PARSE_BD_UDP_CS_FLG;
Eilon Greenstein755735e2008-06-23 20:35:13 -070012277
12278 DP(NETIF_MSG_TX_QUEUED,
Eilon Greensteinca003922009-08-12 22:53:28 -070012279 "hlen %d fix %d csum before fix %x\n",
12280 le16_to_cpu(pbd->total_hlen), fix, SKB_CS(skb));
Eilon Greenstein755735e2008-06-23 20:35:13 -070012281
12282 /* HW bug: fixup the CSUM */
12283 pbd->tcp_pseudo_csum =
12284 bnx2x_csum_fix(skb_transport_header(skb),
12285 SKB_CS(skb), fix);
12286
12287 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
12288 pbd->tcp_pseudo_csum);
12289 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012290 }
12291
FUJITA Tomonori1a983142010-04-04 01:51:03 +000012292 mapping = dma_map_single(&bp->pdev->dev, skb->data,
12293 skb_headlen(skb), DMA_TO_DEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012294
Eilon Greensteinca003922009-08-12 22:53:28 -070012295 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
12296 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
12297 nbd = skb_shinfo(skb)->nr_frags + 2; /* start_bd + pbd + frags */
12298 tx_start_bd->nbd = cpu_to_le16(nbd);
12299 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
12300 pkt_size = tx_start_bd->nbytes;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012301
12302 DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
Eilon Greenstein755735e2008-06-23 20:35:13 -070012303 " nbytes %d flags %x vlan %x\n",
Eilon Greensteinca003922009-08-12 22:53:28 -070012304 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
12305 le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
12306 tx_start_bd->bd_flags.as_bitfield, le16_to_cpu(tx_start_bd->vlan));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012307
Eilon Greenstein755735e2008-06-23 20:35:13 -070012308 if (xmit_type & XMIT_GSO) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012309
12310 DP(NETIF_MSG_TX_QUEUED,
12311 "TSO packet len %d hlen %d total len %d tso size %d\n",
12312 skb->len, hlen, skb_headlen(skb),
12313 skb_shinfo(skb)->gso_size);
12314
Eilon Greensteinca003922009-08-12 22:53:28 -070012315 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012316
Eilon Greenstein755735e2008-06-23 20:35:13 -070012317 if (unlikely(skb_headlen(skb) > hlen))
Eilon Greensteinca003922009-08-12 22:53:28 -070012318 bd_prod = bnx2x_tx_split(bp, fp, tx_buf, &tx_start_bd,
12319 hlen, bd_prod, ++nbd);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012320
12321 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
12322 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
Eilon Greenstein755735e2008-06-23 20:35:13 -070012323 pbd->tcp_flags = pbd_tcp_flags(skb);
12324
12325 if (xmit_type & XMIT_GSO_V4) {
12326 pbd->ip_id = swab16(ip_hdr(skb)->id);
12327 pbd->tcp_pseudo_csum =
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012328 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
12329 ip_hdr(skb)->daddr,
12330 0, IPPROTO_TCP, 0));
Eilon Greenstein755735e2008-06-23 20:35:13 -070012331
12332 } else
12333 pbd->tcp_pseudo_csum =
12334 swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
12335 &ipv6_hdr(skb)->daddr,
12336 0, IPPROTO_TCP, 0));
12337
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012338 pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
12339 }
Eilon Greensteinca003922009-08-12 22:53:28 -070012340 tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012341
Eilon Greenstein755735e2008-06-23 20:35:13 -070012342 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
12343 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012344
Eilon Greenstein755735e2008-06-23 20:35:13 -070012345 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
Eilon Greensteinca003922009-08-12 22:53:28 -070012346 tx_data_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
12347 if (total_pkt_bd == NULL)
12348 total_pkt_bd = &fp->tx_desc_ring[bd_prod].reg_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012349
FUJITA Tomonori1a983142010-04-04 01:51:03 +000012350 mapping = dma_map_page(&bp->pdev->dev, frag->page,
12351 frag->page_offset,
12352 frag->size, DMA_TO_DEVICE);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012353
Eilon Greensteinca003922009-08-12 22:53:28 -070012354 tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
12355 tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
12356 tx_data_bd->nbytes = cpu_to_le16(frag->size);
12357 le16_add_cpu(&pkt_size, frag->size);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012358
Eilon Greenstein755735e2008-06-23 20:35:13 -070012359 DP(NETIF_MSG_TX_QUEUED,
Eilon Greensteinca003922009-08-12 22:53:28 -070012360 "frag %d bd @%p addr (%x:%x) nbytes %d\n",
12361 i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
12362 le16_to_cpu(tx_data_bd->nbytes));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012363 }
12364
Eilon Greensteinca003922009-08-12 22:53:28 -070012365 DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012366
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012367 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
12368
Eilon Greenstein755735e2008-06-23 20:35:13 -070012369 /* now send a tx doorbell, counting the next BD
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012370 * if the packet contains or ends with it
12371 */
12372 if (TX_BD_POFF(bd_prod) < nbd)
12373 nbd++;
12374
Eilon Greensteinca003922009-08-12 22:53:28 -070012375 if (total_pkt_bd != NULL)
12376 total_pkt_bd->total_pkt_bytes = pkt_size;
12377
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012378 if (pbd)
12379 DP(NETIF_MSG_TX_QUEUED,
12380 "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
12381 " tcp_flags %x xsum %x seq %u hlen %u\n",
12382 pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
12383 pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
Eilon Greenstein755735e2008-06-23 20:35:13 -070012384 pbd->tcp_send_seq, le16_to_cpu(pbd->total_hlen));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012385
Eilon Greenstein755735e2008-06-23 20:35:13 -070012386 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012387
Eilon Greenstein58f4c4c2009-01-14 21:23:36 -080012388 /*
12389 * Make sure that the BD data is updated before updating the producer
12390 * since FW might read the BD right after the producer is updated.
12391 * This is only applicable for weak-ordered memory model archs such
12392 * as IA-64. The following barrier is also mandatory since FW will
12393 * assumes packets must have BDs.
12394 */
12395 wmb();
12396
Eilon Greensteinca003922009-08-12 22:53:28 -070012397 fp->tx_db.data.prod += nbd;
12398 barrier();
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000012399 DOORBELL(bp, fp->index, fp->tx_db.raw);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012400
12401 mmiowb();
12402
Eilon Greenstein755735e2008-06-23 20:35:13 -070012403 fp->tx_bd_prod += nbd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012404
12405 if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
Eilon Greensteinca003922009-08-12 22:53:28 -070012406 netif_tx_stop_queue(txq);
Stanislaw Gruszka9baddeb2010-03-09 06:55:02 +000012407
12408 /* paired memory barrier is in bnx2x_tx_int(), we have to keep
12409 * ordering of set_bit() in netif_tx_stop_queue() and read of
12410 * fp->bd_tx_cons */
Eilon Greenstein58f4c4c2009-01-14 21:23:36 -080012411 smp_mb();
Stanislaw Gruszka9baddeb2010-03-09 06:55:02 +000012412
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000012413 fp->eth_q_stats.driver_xoff++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012414 if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
Eilon Greenstein555f6c72009-02-12 08:36:11 +000012415 netif_tx_wake_queue(txq);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012416 }
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000012417 fp->tx_pkt++;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012418
12419 return NETDEV_TX_OK;
12420}
12421
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070012422/* called with rtnl_lock */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012423static int bnx2x_open(struct net_device *dev)
12424{
12425 struct bnx2x *bp = netdev_priv(dev);
12426
Eilon Greenstein6eccabb2009-01-22 03:37:48 +000012427 netif_carrier_off(dev);
12428
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012429 bnx2x_set_power_state(bp, PCI_D0);
12430
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000012431 if (!bnx2x_reset_is_done(bp)) {
12432 do {
12433 /* Reset MCP mail box sequence if there is on going
12434 * recovery
12435 */
12436 bp->fw_seq = 0;
12437
12438 /* If it's the first function to load and reset done
12439 * is still not cleared it may mean that. We don't
12440 * check the attention state here because it may have
12441 * already been cleared by a "common" reset but we
12442 * shell proceed with "process kill" anyway.
12443 */
12444 if ((bnx2x_get_load_cnt(bp) == 0) &&
12445 bnx2x_trylock_hw_lock(bp,
12446 HW_LOCK_RESOURCE_RESERVED_08) &&
12447 (!bnx2x_leader_reset(bp))) {
12448 DP(NETIF_MSG_HW, "Recovered in open\n");
12449 break;
12450 }
12451
12452 bnx2x_set_power_state(bp, PCI_D3hot);
12453
12454 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
12455 " completed yet. Try again later. If u still see this"
12456 " message after a few retries then power cycle is"
12457 " required.\n", bp->dev->name);
12458
12459 return -EAGAIN;
12460 } while (0);
12461 }
12462
12463 bp->recovery_state = BNX2X_RECOVERY_DONE;
12464
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070012465 return bnx2x_nic_load(bp, LOAD_OPEN);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012466}
12467
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070012468/* called with rtnl_lock */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012469static int bnx2x_close(struct net_device *dev)
12470{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012471 struct bnx2x *bp = netdev_priv(dev);
12472
12473 /* Unload the driver, release IRQs */
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -070012474 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
12475 if (atomic_read(&bp->pdev->enable_cnt) == 1)
12476 if (!CHIP_REV_IS_SLOW(bp))
12477 bnx2x_set_power_state(bp, PCI_D3hot);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012478
12479 return 0;
12480}
12481
Eilon Greensteinf5372252009-02-12 08:38:30 +000012482/* called with netif_tx_lock from dev_mcast.c */
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012483static void bnx2x_set_rx_mode(struct net_device *dev)
12484{
12485 struct bnx2x *bp = netdev_priv(dev);
12486 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12487 int port = BP_PORT(bp);
12488
12489 if (bp->state != BNX2X_STATE_OPEN) {
12490 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12491 return;
12492 }
12493
12494 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
12495
12496 if (dev->flags & IFF_PROMISC)
12497 rx_mode = BNX2X_RX_MODE_PROMISC;
12498
12499 else if ((dev->flags & IFF_ALLMULTI) ||
Jiri Pirko4cd24ea2010-02-08 04:30:35 +000012500 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
12501 CHIP_IS_E1(bp)))
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012502 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12503
12504 else { /* some multicasts */
12505 if (CHIP_IS_E1(bp)) {
12506 int i, old, offset;
Jiri Pirko22bedad2010-04-01 21:22:57 +000012507 struct netdev_hw_addr *ha;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012508 struct mac_configuration_cmd *config =
12509 bnx2x_sp(bp, mcast_config);
12510
Jiri Pirko0ddf4772010-02-20 00:13:58 +000012511 i = 0;
Jiri Pirko22bedad2010-04-01 21:22:57 +000012512 netdev_for_each_mc_addr(ha, dev) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012513 config->config_table[i].
12514 cam_entry.msb_mac_addr =
Jiri Pirko22bedad2010-04-01 21:22:57 +000012515 swab16(*(u16 *)&ha->addr[0]);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012516 config->config_table[i].
12517 cam_entry.middle_mac_addr =
Jiri Pirko22bedad2010-04-01 21:22:57 +000012518 swab16(*(u16 *)&ha->addr[2]);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012519 config->config_table[i].
12520 cam_entry.lsb_mac_addr =
Jiri Pirko22bedad2010-04-01 21:22:57 +000012521 swab16(*(u16 *)&ha->addr[4]);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012522 config->config_table[i].cam_entry.flags =
12523 cpu_to_le16(port);
12524 config->config_table[i].
12525 target_table_entry.flags = 0;
Eilon Greensteinca003922009-08-12 22:53:28 -070012526 config->config_table[i].target_table_entry.
12527 clients_bit_vector =
12528 cpu_to_le32(1 << BP_L_ID(bp));
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012529 config->config_table[i].
12530 target_table_entry.vlan_id = 0;
12531
12532 DP(NETIF_MSG_IFUP,
12533 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
12534 config->config_table[i].
12535 cam_entry.msb_mac_addr,
12536 config->config_table[i].
12537 cam_entry.middle_mac_addr,
12538 config->config_table[i].
12539 cam_entry.lsb_mac_addr);
Jiri Pirko0ddf4772010-02-20 00:13:58 +000012540 i++;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012541 }
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -080012542 old = config->hdr.length;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012543 if (old > i) {
12544 for (; i < old; i++) {
12545 if (CAM_IS_INVALID(config->
12546 config_table[i])) {
Eilon Greensteinaf246402009-01-14 06:43:59 +000012547 /* already invalidated */
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012548 break;
12549 }
12550 /* invalidate */
12551 CAM_INVALIDATE(config->
12552 config_table[i]);
12553 }
12554 }
12555
12556 if (CHIP_REV_IS_SLOW(bp))
12557 offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
12558 else
12559 offset = BNX2X_MAX_MULTICAST*(1 + port);
12560
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -080012561 config->hdr.length = i;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012562 config->hdr.offset = offset;
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -080012563 config->hdr.client_id = bp->fp->cl_id;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012564 config->hdr.reserved1 = 0;
12565
Michael Chane665bfd2009-10-10 13:46:54 +000012566 bp->set_mac_pending++;
12567 smp_wmb();
12568
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012569 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
12570 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
12571 U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
12572 0);
12573 } else { /* E1H */
12574 /* Accept one or more multicasts */
Jiri Pirko22bedad2010-04-01 21:22:57 +000012575 struct netdev_hw_addr *ha;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012576 u32 mc_filter[MC_HASH_SIZE];
12577 u32 crc, bit, regidx;
12578 int i;
12579
12580 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
12581
Jiri Pirko22bedad2010-04-01 21:22:57 +000012582 netdev_for_each_mc_addr(ha, dev) {
Johannes Berg7c510e42008-10-27 17:47:26 -070012583 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
Jiri Pirko22bedad2010-04-01 21:22:57 +000012584 ha->addr);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012585
Jiri Pirko22bedad2010-04-01 21:22:57 +000012586 crc = crc32c_le(0, ha->addr, ETH_ALEN);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012587 bit = (crc >> 24) & 0xff;
12588 regidx = bit >> 5;
12589 bit &= 0x1f;
12590 mc_filter[regidx] |= (1 << bit);
12591 }
12592
12593 for (i = 0; i < MC_HASH_SIZE; i++)
12594 REG_WR(bp, MC_HASH_OFFSET(bp, i),
12595 mc_filter[i]);
12596 }
12597 }
12598
12599 bp->rx_mode = rx_mode;
12600 bnx2x_set_storm_rx_mode(bp);
12601}
12602
12603/* called with rtnl_lock */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012604static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
12605{
12606 struct sockaddr *addr = p;
12607 struct bnx2x *bp = netdev_priv(dev);
12608
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012609 if (!is_valid_ether_addr((u8 *)(addr->sa_data)))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012610 return -EINVAL;
12611
12612 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012613 if (netif_running(dev)) {
12614 if (CHIP_IS_E1(bp))
Michael Chane665bfd2009-10-10 13:46:54 +000012615 bnx2x_set_eth_mac_addr_e1(bp, 1);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012616 else
Michael Chane665bfd2009-10-10 13:46:54 +000012617 bnx2x_set_eth_mac_addr_e1h(bp, 1);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012618 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012619
12620 return 0;
12621}
12622
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070012623/* called with rtnl_lock */
Eilon Greenstein01cd4522009-08-12 08:23:08 +000012624static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12625 int devad, u16 addr)
12626{
12627 struct bnx2x *bp = netdev_priv(netdev);
12628 u16 value;
12629 int rc;
12630 u32 phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
12631
12632 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12633 prtad, devad, addr);
12634
12635 if (prtad != bp->mdio.prtad) {
12636 DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
12637 prtad, bp->mdio.prtad);
12638 return -EINVAL;
12639 }
12640
12641 /* The HW expects different devad if CL22 is used */
12642 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12643
12644 bnx2x_acquire_phy_lock(bp);
12645 rc = bnx2x_cl45_read(bp, BP_PORT(bp), phy_type, prtad,
12646 devad, addr, &value);
12647 bnx2x_release_phy_lock(bp);
12648 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12649
12650 if (!rc)
12651 rc = value;
12652 return rc;
12653}
12654
12655/* called with rtnl_lock */
12656static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12657 u16 addr, u16 value)
12658{
12659 struct bnx2x *bp = netdev_priv(netdev);
12660 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
12661 int rc;
12662
12663 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
12664 " value 0x%x\n", prtad, devad, addr, value);
12665
12666 if (prtad != bp->mdio.prtad) {
12667 DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
12668 prtad, bp->mdio.prtad);
12669 return -EINVAL;
12670 }
12671
12672 /* The HW expects different devad if CL22 is used */
12673 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12674
12675 bnx2x_acquire_phy_lock(bp);
12676 rc = bnx2x_cl45_write(bp, BP_PORT(bp), ext_phy_type, prtad,
12677 devad, addr, value);
12678 bnx2x_release_phy_lock(bp);
12679 return rc;
12680}
12681
12682/* called with rtnl_lock */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012683static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12684{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012685 struct bnx2x *bp = netdev_priv(dev);
Eilon Greenstein01cd4522009-08-12 08:23:08 +000012686 struct mii_ioctl_data *mdio = if_mii(ifr);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012687
Eilon Greenstein01cd4522009-08-12 08:23:08 +000012688 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12689 mdio->phy_id, mdio->reg_num, mdio->val_in);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012690
Eilon Greenstein01cd4522009-08-12 08:23:08 +000012691 if (!netif_running(dev))
12692 return -EAGAIN;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -070012693
Eilon Greenstein01cd4522009-08-12 08:23:08 +000012694 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012695}
12696
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012697/* called with rtnl_lock */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012698static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
12699{
12700 struct bnx2x *bp = netdev_priv(dev);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012701 int rc = 0;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012702
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000012703 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12704 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
12705 return -EAGAIN;
12706 }
12707
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012708 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
12709 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
12710 return -EINVAL;
12711
12712 /* This does not race with packet allocation
Eliezer Tamirc14423f2008-02-28 11:49:42 -080012713 * because the actual alloc size is
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012714 * only updated as part of load
12715 */
12716 dev->mtu = new_mtu;
12717
12718 if (netif_running(dev)) {
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012719 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
12720 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012721 }
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012722
12723 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012724}
12725
12726static void bnx2x_tx_timeout(struct net_device *dev)
12727{
12728 struct bnx2x *bp = netdev_priv(dev);
12729
12730#ifdef BNX2X_STOP_ON_ERROR
12731 if (!bp->panic)
12732 bnx2x_panic();
12733#endif
12734 /* This allows the netif to be shutdown gracefully before resetting */
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000012735 schedule_delayed_work(&bp->reset_task, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012736}
12737
12738#ifdef BCM_VLAN
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012739/* called with rtnl_lock */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012740static void bnx2x_vlan_rx_register(struct net_device *dev,
12741 struct vlan_group *vlgrp)
12742{
12743 struct bnx2x *bp = netdev_priv(dev);
12744
12745 bp->vlgrp = vlgrp;
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080012746
12747 /* Set flags according to the required capabilities */
12748 bp->flags &= ~(HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);
12749
12750 if (dev->features & NETIF_F_HW_VLAN_TX)
12751 bp->flags |= HW_VLAN_TX_FLAG;
12752
12753 if (dev->features & NETIF_F_HW_VLAN_RX)
12754 bp->flags |= HW_VLAN_RX_FLAG;
12755
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012756 if (netif_running(dev))
Eliezer Tamir49d66772008-02-28 11:53:13 -080012757 bnx2x_set_client_config(bp);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012758}
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012759
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012760#endif
12761
Alexey Dobriyan257ddbd2010-01-27 10:17:41 +000012762#ifdef CONFIG_NET_POLL_CONTROLLER
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012763static void poll_bnx2x(struct net_device *dev)
12764{
12765 struct bnx2x *bp = netdev_priv(dev);
12766
12767 disable_irq(bp->pdev->irq);
12768 bnx2x_interrupt(bp->pdev->irq, dev);
12769 enable_irq(bp->pdev->irq);
12770}
12771#endif
12772
Stephen Hemmingerc64213c2008-11-21 17:36:04 -080012773static const struct net_device_ops bnx2x_netdev_ops = {
12774 .ndo_open = bnx2x_open,
12775 .ndo_stop = bnx2x_close,
12776 .ndo_start_xmit = bnx2x_start_xmit,
Eilon Greenstein356e2382009-02-12 08:38:32 +000012777 .ndo_set_multicast_list = bnx2x_set_rx_mode,
Stephen Hemmingerc64213c2008-11-21 17:36:04 -080012778 .ndo_set_mac_address = bnx2x_change_mac_addr,
12779 .ndo_validate_addr = eth_validate_addr,
12780 .ndo_do_ioctl = bnx2x_ioctl,
12781 .ndo_change_mtu = bnx2x_change_mtu,
12782 .ndo_tx_timeout = bnx2x_tx_timeout,
12783#ifdef BCM_VLAN
12784 .ndo_vlan_rx_register = bnx2x_vlan_rx_register,
12785#endif
Alexey Dobriyan257ddbd2010-01-27 10:17:41 +000012786#ifdef CONFIG_NET_POLL_CONTROLLER
Stephen Hemmingerc64213c2008-11-21 17:36:04 -080012787 .ndo_poll_controller = poll_bnx2x,
12788#endif
12789};
12790
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012791static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
12792 struct net_device *dev)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012793{
12794 struct bnx2x *bp;
12795 int rc;
12796
12797 SET_NETDEV_DEV(dev, &pdev->dev);
12798 bp = netdev_priv(dev);
12799
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012800 bp->dev = dev;
12801 bp->pdev = pdev;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012802 bp->flags = 0;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012803 bp->func = PCI_FUNC(pdev->devfn);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012804
12805 rc = pci_enable_device(pdev);
12806 if (rc) {
Joe Perches7995c642010-02-17 15:01:52 +000012807 pr_err("Cannot enable PCI device, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012808 goto err_out;
12809 }
12810
12811 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
Joe Perches7995c642010-02-17 15:01:52 +000012812 pr_err("Cannot find PCI device base address, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012813 rc = -ENODEV;
12814 goto err_out_disable;
12815 }
12816
12817 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
Joe Perches7995c642010-02-17 15:01:52 +000012818 pr_err("Cannot find second PCI device base address, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012819 rc = -ENODEV;
12820 goto err_out_disable;
12821 }
12822
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012823 if (atomic_read(&pdev->enable_cnt) == 1) {
12824 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12825 if (rc) {
Joe Perches7995c642010-02-17 15:01:52 +000012826 pr_err("Cannot obtain PCI resources, aborting\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012827 goto err_out_disable;
12828 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012829
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012830 pci_set_master(pdev);
12831 pci_save_state(pdev);
12832 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012833
12834 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12835 if (bp->pm_cap == 0) {
Joe Perches7995c642010-02-17 15:01:52 +000012836 pr_err("Cannot find power management capability, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012837 rc = -EIO;
12838 goto err_out_release;
12839 }
12840
12841 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
12842 if (bp->pcie_cap == 0) {
Joe Perches7995c642010-02-17 15:01:52 +000012843 pr_err("Cannot find PCI Express capability, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012844 rc = -EIO;
12845 goto err_out_release;
12846 }
12847
FUJITA Tomonori1a983142010-04-04 01:51:03 +000012848 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012849 bp->flags |= USING_DAC_FLAG;
FUJITA Tomonori1a983142010-04-04 01:51:03 +000012850 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
12851 pr_err("dma_set_coherent_mask failed, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012852 rc = -EIO;
12853 goto err_out_release;
12854 }
12855
FUJITA Tomonori1a983142010-04-04 01:51:03 +000012856 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
Joe Perches7995c642010-02-17 15:01:52 +000012857 pr_err("System does not support DMA, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012858 rc = -EIO;
12859 goto err_out_release;
12860 }
12861
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012862 dev->mem_start = pci_resource_start(pdev, 0);
12863 dev->base_addr = dev->mem_start;
12864 dev->mem_end = pci_resource_end(pdev, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012865
12866 dev->irq = pdev->irq;
12867
Arjan van de Ven275f1652008-10-20 21:42:39 -070012868 bp->regview = pci_ioremap_bar(pdev, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012869 if (!bp->regview) {
Joe Perches7995c642010-02-17 15:01:52 +000012870 pr_err("Cannot map register space, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012871 rc = -ENOMEM;
12872 goto err_out_release;
12873 }
12874
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012875 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12876 min_t(u64, BNX2X_DB_SIZE,
12877 pci_resource_len(pdev, 2)));
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012878 if (!bp->doorbells) {
Joe Perches7995c642010-02-17 15:01:52 +000012879 pr_err("Cannot map doorbell space, aborting\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012880 rc = -ENOMEM;
12881 goto err_out_unmap;
12882 }
12883
12884 bnx2x_set_power_state(bp, PCI_D0);
12885
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012886 /* clean indirect addresses */
12887 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12888 PCICFG_VENDOR_ID_OFFSET);
12889 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
12890 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
12891 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
12892 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012893
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000012894 /* Reset the load counter */
12895 bnx2x_clear_load_cnt(bp);
12896
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012897 dev->watchdog_timeo = TX_TIMEOUT;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012898
Stephen Hemmingerc64213c2008-11-21 17:36:04 -080012899 dev->netdev_ops = &bnx2x_netdev_ops;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012900 dev->ethtool_ops = &bnx2x_ethtool_ops;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012901 dev->features |= NETIF_F_SG;
12902 dev->features |= NETIF_F_HW_CSUM;
12903 if (bp->flags & USING_DAC_FLAG)
12904 dev->features |= NETIF_F_HIGHDMA;
Eilon Greenstein5316bc02009-07-21 05:47:43 +000012905 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
12906 dev->features |= NETIF_F_TSO6;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012907#ifdef BCM_VLAN
12908 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
Eilon Greenstein0c6671b2009-01-14 21:26:51 -080012909 bp->flags |= (HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG);
Eilon Greenstein5316bc02009-07-21 05:47:43 +000012910
12911 dev->vlan_features |= NETIF_F_SG;
12912 dev->vlan_features |= NETIF_F_HW_CSUM;
12913 if (bp->flags & USING_DAC_FLAG)
12914 dev->vlan_features |= NETIF_F_HIGHDMA;
12915 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
12916 dev->vlan_features |= NETIF_F_TSO6;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012917#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012918
Eilon Greenstein01cd4522009-08-12 08:23:08 +000012919 /* get_port_hwinfo() will set prtad and mmds properly */
12920 bp->mdio.prtad = MDIO_PRTAD_NONE;
12921 bp->mdio.mmds = 0;
12922 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12923 bp->mdio.dev = dev;
12924 bp->mdio.mdio_read = bnx2x_mdio_read;
12925 bp->mdio.mdio_write = bnx2x_mdio_write;
12926
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012927 return 0;
12928
12929err_out_unmap:
12930 if (bp->regview) {
12931 iounmap(bp->regview);
12932 bp->regview = NULL;
12933 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012934 if (bp->doorbells) {
12935 iounmap(bp->doorbells);
12936 bp->doorbells = NULL;
12937 }
12938
12939err_out_release:
Eilon Greenstein34f80b02008-06-23 20:33:01 -070012940 if (atomic_read(&pdev->enable_cnt) == 1)
12941 pci_release_regions(pdev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020012942
12943err_out_disable:
12944 pci_disable_device(pdev);
12945 pci_set_drvdata(pdev, NULL);
12946
12947err_out:
12948 return rc;
12949}
12950
Eilon Greenstein37f9ce62009-08-12 08:23:34 +000012951static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
12952 int *width, int *speed)
Eliezer Tamir25047952008-02-28 11:50:16 -080012953{
12954 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
12955
Eilon Greenstein37f9ce62009-08-12 08:23:34 +000012956 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12957
12958 /* return value of 1=2.5GHz 2=5GHz */
12959 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
Eliezer Tamir25047952008-02-28 11:50:16 -080012960}
12961
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070012962static int __devinit bnx2x_check_firmware(struct bnx2x *bp)
12963{
Eilon Greenstein37f9ce62009-08-12 08:23:34 +000012964 const struct firmware *firmware = bp->firmware;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070012965 struct bnx2x_fw_file_hdr *fw_hdr;
12966 struct bnx2x_fw_file_section *sections;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070012967 u32 offset, len, num_ops;
Eilon Greenstein37f9ce62009-08-12 08:23:34 +000012968 u16 *ops_offsets;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070012969 int i;
Eilon Greenstein37f9ce62009-08-12 08:23:34 +000012970 const u8 *fw_ver;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070012971
12972 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
12973 return -EINVAL;
12974
12975 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12976 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12977
12978 /* Make sure none of the offsets and sizes make us read beyond
12979 * the end of the firmware data */
12980 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12981 offset = be32_to_cpu(sections[i].offset);
12982 len = be32_to_cpu(sections[i].len);
12983 if (offset + len > firmware->size) {
Joe Perches7995c642010-02-17 15:01:52 +000012984 pr_err("Section %d length is out of bounds\n", i);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070012985 return -EINVAL;
12986 }
12987 }
12988
12989 /* Likewise for the init_ops offsets */
12990 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12991 ops_offsets = (u16 *)(firmware->data + offset);
12992 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12993
12994 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12995 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
Joe Perches7995c642010-02-17 15:01:52 +000012996 pr_err("Section offset %d is out of bounds\n", i);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070012997 return -EINVAL;
12998 }
12999 }
13000
13001 /* Check FW version */
13002 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13003 fw_ver = firmware->data + offset;
13004 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13005 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13006 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13007 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
Joe Perches7995c642010-02-17 15:01:52 +000013008 pr_err("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013009 fw_ver[0], fw_ver[1], fw_ver[2],
13010 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
13011 BCM_5710_FW_MINOR_VERSION,
13012 BCM_5710_FW_REVISION_VERSION,
13013 BCM_5710_FW_ENGINEERING_VERSION);
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013014 return -EINVAL;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013015 }
13016
13017 return 0;
13018}
13019
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013020static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013021{
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013022 const __be32 *source = (const __be32 *)_source;
13023 u32 *target = (u32 *)_target;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013024 u32 i;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013025
13026 for (i = 0; i < n/4; i++)
13027 target[i] = be32_to_cpu(source[i]);
13028}
13029
13030/*
13031 Ops array is stored in the following format:
13032 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13033 */
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013034static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013035{
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013036 const __be32 *source = (const __be32 *)_source;
13037 struct raw_op *target = (struct raw_op *)_target;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013038 u32 i, j, tmp;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013039
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013040 for (i = 0, j = 0; i < n/8; i++, j += 2) {
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013041 tmp = be32_to_cpu(source[j]);
13042 target[i].op = (tmp >> 24) & 0xff;
13043 target[i].offset = tmp & 0xffffff;
13044 target[i].raw_data = be32_to_cpu(source[j+1]);
13045 }
13046}
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013047
13048static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013049{
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013050 const __be16 *source = (const __be16 *)_source;
13051 u16 *target = (u16 *)_target;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013052 u32 i;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013053
13054 for (i = 0; i < n/2; i++)
13055 target[i] = be16_to_cpu(source[i]);
13056}
13057
Joe Perches7995c642010-02-17 15:01:52 +000013058#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13059do { \
13060 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13061 bp->arr = kmalloc(len, GFP_KERNEL); \
13062 if (!bp->arr) { \
13063 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
13064 goto lbl; \
13065 } \
13066 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13067 (u8 *)bp->arr, len); \
13068} while (0)
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013069
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013070static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
13071{
Ben Hutchings45229b42009-11-07 11:53:39 +000013072 const char *fw_file_name;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013073 struct bnx2x_fw_file_hdr *fw_hdr;
Ben Hutchings45229b42009-11-07 11:53:39 +000013074 int rc;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013075
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013076 if (CHIP_IS_E1(bp))
Ben Hutchings45229b42009-11-07 11:53:39 +000013077 fw_file_name = FW_FILE_NAME_E1;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013078 else
Ben Hutchings45229b42009-11-07 11:53:39 +000013079 fw_file_name = FW_FILE_NAME_E1H;
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013080
Joe Perches7995c642010-02-17 15:01:52 +000013081 pr_info("Loading %s\n", fw_file_name);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013082
13083 rc = request_firmware(&bp->firmware, fw_file_name, dev);
13084 if (rc) {
Joe Perches7995c642010-02-17 15:01:52 +000013085 pr_err("Can't load firmware file %s\n", fw_file_name);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013086 goto request_firmware_exit;
13087 }
13088
13089 rc = bnx2x_check_firmware(bp);
13090 if (rc) {
Joe Perches7995c642010-02-17 15:01:52 +000013091 pr_err("Corrupt firmware file %s\n", fw_file_name);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013092 goto request_firmware_exit;
13093 }
13094
13095 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13096
13097 /* Initialize the pointers to the init arrays */
13098 /* Blob */
13099 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13100
13101 /* Opcodes */
13102 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13103
13104 /* Offsets */
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013105 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13106 be16_to_cpu_n);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013107
13108 /* STORMs firmware */
Eilon Greenstein573f2032009-08-12 08:24:14 +000013109 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13110 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13111 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13112 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13113 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13114 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13115 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13116 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13117 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13118 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13119 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13120 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13121 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13122 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13123 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13124 be32_to_cpu(fw_hdr->csem_pram_data.offset);
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013125
13126 return 0;
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +000013127
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013128init_offsets_alloc_err:
13129 kfree(bp->init_ops);
13130init_ops_alloc_err:
13131 kfree(bp->init_data);
13132request_firmware_exit:
13133 release_firmware(bp->firmware);
13134
13135 return rc;
13136}
13137
13138
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013139static int __devinit bnx2x_init_one(struct pci_dev *pdev,
13140 const struct pci_device_id *ent)
13141{
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013142 struct net_device *dev = NULL;
13143 struct bnx2x *bp;
Eilon Greenstein37f9ce62009-08-12 08:23:34 +000013144 int pcie_width, pcie_speed;
Eliezer Tamir25047952008-02-28 11:50:16 -080013145 int rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013146
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013147 /* dev zeroed in init_etherdev */
Eilon Greenstein555f6c72009-02-12 08:36:11 +000013148 dev = alloc_etherdev_mq(sizeof(*bp), MAX_CONTEXT);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013149 if (!dev) {
Joe Perches7995c642010-02-17 15:01:52 +000013150 pr_err("Cannot allocate net device\n");
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013151 return -ENOMEM;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013152 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013153
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013154 bp = netdev_priv(dev);
Joe Perches7995c642010-02-17 15:01:52 +000013155 bp->msg_enable = debug;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013156
Eilon Greensteindf4770de2009-08-12 08:23:28 +000013157 pci_set_drvdata(pdev, dev);
13158
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013159 rc = bnx2x_init_dev(pdev, dev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013160 if (rc < 0) {
13161 free_netdev(dev);
13162 return rc;
13163 }
13164
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013165 rc = bnx2x_init_bp(bp);
Eilon Greenstein693fc0d2009-01-14 06:43:52 +000013166 if (rc)
13167 goto init_one_exit;
13168
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013169 /* Set init arrays */
13170 rc = bnx2x_init_firmware(bp, &pdev->dev);
13171 if (rc) {
Joe Perches7995c642010-02-17 15:01:52 +000013172 pr_err("Error loading firmware\n");
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013173 goto init_one_exit;
13174 }
13175
Eilon Greenstein693fc0d2009-01-14 06:43:52 +000013176 rc = register_netdev(dev);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013177 if (rc) {
Eilon Greenstein693fc0d2009-01-14 06:43:52 +000013178 dev_err(&pdev->dev, "Cannot register net device\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013179 goto init_one_exit;
13180 }
13181
Eilon Greenstein37f9ce62009-08-12 08:23:34 +000013182 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
Joe Perches7995c642010-02-17 15:01:52 +000013183 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13184 board_info[ent->driver_data].name,
13185 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13186 pcie_width, (pcie_speed == 2) ? "5GHz (Gen2)" : "2.5GHz",
13187 dev->base_addr, bp->pdev->irq, dev->dev_addr);
Eilon Greensteinc0162012009-03-02 08:01:05 +000013188
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013189 return 0;
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013190
13191init_one_exit:
13192 if (bp->regview)
13193 iounmap(bp->regview);
13194
13195 if (bp->doorbells)
13196 iounmap(bp->doorbells);
13197
13198 free_netdev(dev);
13199
13200 if (atomic_read(&pdev->enable_cnt) == 1)
13201 pci_release_regions(pdev);
13202
13203 pci_disable_device(pdev);
13204 pci_set_drvdata(pdev, NULL);
13205
13206 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013207}
13208
13209static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
13210{
13211 struct net_device *dev = pci_get_drvdata(pdev);
Eliezer Tamir228241e2008-02-28 11:56:57 -080013212 struct bnx2x *bp;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013213
Eliezer Tamir228241e2008-02-28 11:56:57 -080013214 if (!dev) {
Joe Perches7995c642010-02-17 15:01:52 +000013215 pr_err("BAD net device from bnx2x_init_one\n");
Eliezer Tamir228241e2008-02-28 11:56:57 -080013216 return;
13217 }
Eliezer Tamir228241e2008-02-28 11:56:57 -080013218 bp = netdev_priv(dev);
13219
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013220 unregister_netdev(dev);
13221
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000013222 /* Make sure RESET task is not scheduled before continuing */
13223 cancel_delayed_work_sync(&bp->reset_task);
13224
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013225 kfree(bp->init_ops_offsets);
13226 kfree(bp->init_ops);
13227 kfree(bp->init_data);
13228 release_firmware(bp->firmware);
13229
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013230 if (bp->regview)
13231 iounmap(bp->regview);
13232
13233 if (bp->doorbells)
13234 iounmap(bp->doorbells);
13235
13236 free_netdev(dev);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013237
13238 if (atomic_read(&pdev->enable_cnt) == 1)
13239 pci_release_regions(pdev);
13240
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013241 pci_disable_device(pdev);
13242 pci_set_drvdata(pdev, NULL);
13243}
13244
13245static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
13246{
13247 struct net_device *dev = pci_get_drvdata(pdev);
Eliezer Tamir228241e2008-02-28 11:56:57 -080013248 struct bnx2x *bp;
13249
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013250 if (!dev) {
Joe Perches7995c642010-02-17 15:01:52 +000013251 pr_err("BAD net device from bnx2x_init_one\n");
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013252 return -ENODEV;
13253 }
Eliezer Tamir228241e2008-02-28 11:56:57 -080013254 bp = netdev_priv(dev);
13255
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013256 rtnl_lock();
13257
13258 pci_save_state(pdev);
13259
13260 if (!netif_running(dev)) {
13261 rtnl_unlock();
13262 return 0;
13263 }
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013264
13265 netif_device_detach(dev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013266
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -070013267 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013268
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013269 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
Eliezer Tamir228241e2008-02-28 11:56:57 -080013270
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013271 rtnl_unlock();
13272
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013273 return 0;
13274}
13275
13276static int bnx2x_resume(struct pci_dev *pdev)
13277{
13278 struct net_device *dev = pci_get_drvdata(pdev);
Eliezer Tamir228241e2008-02-28 11:56:57 -080013279 struct bnx2x *bp;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013280 int rc;
13281
Eliezer Tamir228241e2008-02-28 11:56:57 -080013282 if (!dev) {
Joe Perches7995c642010-02-17 15:01:52 +000013283 pr_err("BAD net device from bnx2x_init_one\n");
Eliezer Tamir228241e2008-02-28 11:56:57 -080013284 return -ENODEV;
13285 }
Eliezer Tamir228241e2008-02-28 11:56:57 -080013286 bp = netdev_priv(dev);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013287
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000013288 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13289 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
13290 return -EAGAIN;
13291 }
13292
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013293 rtnl_lock();
13294
Eliezer Tamir228241e2008-02-28 11:56:57 -080013295 pci_restore_state(pdev);
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013296
13297 if (!netif_running(dev)) {
13298 rtnl_unlock();
13299 return 0;
13300 }
13301
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013302 bnx2x_set_power_state(bp, PCI_D0);
13303 netif_device_attach(dev);
13304
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -070013305 rc = bnx2x_nic_load(bp, LOAD_OPEN);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013306
Eilon Greenstein34f80b02008-06-23 20:33:01 -070013307 rtnl_unlock();
13308
13309 return rc;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013310}
13311
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013312static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13313{
13314 int i;
13315
13316 bp->state = BNX2X_STATE_ERROR;
13317
13318 bp->rx_mode = BNX2X_RX_MODE_NONE;
13319
13320 bnx2x_netif_stop(bp, 0);
13321
13322 del_timer_sync(&bp->timer);
13323 bp->stats_state = STATS_STATE_DISABLED;
13324 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
13325
13326 /* Release IRQs */
Vladislav Zolotarov6cbe5062010-02-17 02:03:27 +000013327 bnx2x_free_irq(bp, false);
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013328
13329 if (CHIP_IS_E1(bp)) {
13330 struct mac_configuration_cmd *config =
13331 bnx2x_sp(bp, mcast_config);
13332
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -080013333 for (i = 0; i < config->hdr.length; i++)
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013334 CAM_INVALIDATE(config->config_table[i]);
13335 }
13336
13337 /* Free SKBs, SGEs, TPA pool and driver internals */
13338 bnx2x_free_skbs(bp);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000013339 for_each_queue(bp, i)
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013340 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
Vladislav Zolotarov54b9dda2009-11-16 06:05:58 +000013341 for_each_queue(bp, i)
Eilon Greenstein7cde1c82009-01-22 06:01:25 +000013342 netif_napi_del(&bnx2x_fp(bp, i, napi));
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013343 bnx2x_free_mem(bp);
13344
13345 bp->state = BNX2X_STATE_CLOSED;
13346
13347 netif_carrier_off(bp->dev);
13348
13349 return 0;
13350}
13351
13352static void bnx2x_eeh_recover(struct bnx2x *bp)
13353{
13354 u32 val;
13355
13356 mutex_init(&bp->port.phy_mutex);
13357
13358 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
13359 bp->link_params.shmem_base = bp->common.shmem_base;
13360 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
13361
13362 if (!bp->common.shmem_base ||
13363 (bp->common.shmem_base < 0xA0000) ||
13364 (bp->common.shmem_base >= 0xC0000)) {
13365 BNX2X_DEV_INFO("MCP not active\n");
13366 bp->flags |= NO_MCP_FLAG;
13367 return;
13368 }
13369
13370 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
13371 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
13372 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
13373 BNX2X_ERR("BAD MCP validity signature\n");
13374
13375 if (!BP_NOMCP(bp)) {
13376 bp->fw_seq = (SHMEM_RD(bp, func_mb[BP_FUNC(bp)].drv_mb_header)
13377 & DRV_MSG_SEQ_NUMBER_MASK);
13378 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
13379 }
13380}
13381
Wendy Xiong493adb12008-06-23 20:36:22 -070013382/**
13383 * bnx2x_io_error_detected - called when PCI error is detected
13384 * @pdev: Pointer to PCI device
13385 * @state: The current pci connection state
13386 *
13387 * This function is called after a PCI bus error affecting
13388 * this device has been detected.
13389 */
13390static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13391 pci_channel_state_t state)
13392{
13393 struct net_device *dev = pci_get_drvdata(pdev);
13394 struct bnx2x *bp = netdev_priv(dev);
13395
13396 rtnl_lock();
13397
13398 netif_device_detach(dev);
13399
Dean Nelson07ce50e2009-07-31 09:13:25 +000013400 if (state == pci_channel_io_perm_failure) {
13401 rtnl_unlock();
13402 return PCI_ERS_RESULT_DISCONNECT;
13403 }
13404
Wendy Xiong493adb12008-06-23 20:36:22 -070013405 if (netif_running(dev))
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013406 bnx2x_eeh_nic_unload(bp);
Wendy Xiong493adb12008-06-23 20:36:22 -070013407
13408 pci_disable_device(pdev);
13409
13410 rtnl_unlock();
13411
13412 /* Request a slot reset */
13413 return PCI_ERS_RESULT_NEED_RESET;
13414}
13415
13416/**
13417 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13418 * @pdev: Pointer to PCI device
13419 *
13420 * Restart the card from scratch, as if from a cold-boot.
13421 */
13422static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13423{
13424 struct net_device *dev = pci_get_drvdata(pdev);
13425 struct bnx2x *bp = netdev_priv(dev);
13426
13427 rtnl_lock();
13428
13429 if (pci_enable_device(pdev)) {
13430 dev_err(&pdev->dev,
13431 "Cannot re-enable PCI device after reset\n");
13432 rtnl_unlock();
13433 return PCI_ERS_RESULT_DISCONNECT;
13434 }
13435
13436 pci_set_master(pdev);
13437 pci_restore_state(pdev);
13438
13439 if (netif_running(dev))
13440 bnx2x_set_power_state(bp, PCI_D0);
13441
13442 rtnl_unlock();
13443
13444 return PCI_ERS_RESULT_RECOVERED;
13445}
13446
13447/**
13448 * bnx2x_io_resume - called when traffic can start flowing again
13449 * @pdev: Pointer to PCI device
13450 *
13451 * This callback is called when the error recovery driver tells us that
13452 * its OK to resume normal operation.
13453 */
13454static void bnx2x_io_resume(struct pci_dev *pdev)
13455{
13456 struct net_device *dev = pci_get_drvdata(pdev);
13457 struct bnx2x *bp = netdev_priv(dev);
13458
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +000013459 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13460 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
13461 return;
13462 }
13463
Wendy Xiong493adb12008-06-23 20:36:22 -070013464 rtnl_lock();
13465
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013466 bnx2x_eeh_recover(bp);
13467
Wendy Xiong493adb12008-06-23 20:36:22 -070013468 if (netif_running(dev))
Yitchak Gertnerf8ef6e42008-09-09 05:07:25 -070013469 bnx2x_nic_load(bp, LOAD_NORMAL);
Wendy Xiong493adb12008-06-23 20:36:22 -070013470
13471 netif_device_attach(dev);
13472
13473 rtnl_unlock();
13474}
13475
13476static struct pci_error_handlers bnx2x_err_handler = {
13477 .error_detected = bnx2x_io_error_detected,
Eilon Greenstein356e2382009-02-12 08:38:32 +000013478 .slot_reset = bnx2x_io_slot_reset,
13479 .resume = bnx2x_io_resume,
Wendy Xiong493adb12008-06-23 20:36:22 -070013480};
13481
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013482static struct pci_driver bnx2x_pci_driver = {
Wendy Xiong493adb12008-06-23 20:36:22 -070013483 .name = DRV_MODULE_NAME,
13484 .id_table = bnx2x_pci_tbl,
13485 .probe = bnx2x_init_one,
13486 .remove = __devexit_p(bnx2x_remove_one),
13487 .suspend = bnx2x_suspend,
13488 .resume = bnx2x_resume,
13489 .err_handler = &bnx2x_err_handler,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013490};
13491
13492static int __init bnx2x_init(void)
13493{
Stanislaw Gruszkadd21ca62009-05-05 23:22:01 +000013494 int ret;
13495
Joe Perches7995c642010-02-17 15:01:52 +000013496 pr_info("%s", version);
Eilon Greenstein938cf542009-08-12 08:23:37 +000013497
Eilon Greenstein1cf167f2009-01-14 21:22:18 -080013498 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13499 if (bnx2x_wq == NULL) {
Joe Perches7995c642010-02-17 15:01:52 +000013500 pr_err("Cannot create workqueue\n");
Eilon Greenstein1cf167f2009-01-14 21:22:18 -080013501 return -ENOMEM;
13502 }
13503
Stanislaw Gruszkadd21ca62009-05-05 23:22:01 +000013504 ret = pci_register_driver(&bnx2x_pci_driver);
13505 if (ret) {
Joe Perches7995c642010-02-17 15:01:52 +000013506 pr_err("Cannot register driver\n");
Stanislaw Gruszkadd21ca62009-05-05 23:22:01 +000013507 destroy_workqueue(bnx2x_wq);
13508 }
13509 return ret;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013510}
13511
13512static void __exit bnx2x_cleanup(void)
13513{
13514 pci_unregister_driver(&bnx2x_pci_driver);
Eilon Greenstein1cf167f2009-01-14 21:22:18 -080013515
13516 destroy_workqueue(bnx2x_wq);
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020013517}
13518
13519module_init(bnx2x_init);
13520module_exit(bnx2x_cleanup);
13521
Michael Chan993ac7b2009-10-10 13:46:56 +000013522#ifdef BCM_CNIC
13523
13524/* count denotes the number of new completions we have seen */
13525static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13526{
13527 struct eth_spe *spe;
13528
13529#ifdef BNX2X_STOP_ON_ERROR
13530 if (unlikely(bp->panic))
13531 return;
13532#endif
13533
13534 spin_lock_bh(&bp->spq_lock);
13535 bp->cnic_spq_pending -= count;
13536
13537 for (; bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending;
13538 bp->cnic_spq_pending++) {
13539
13540 if (!bp->cnic_kwq_pending)
13541 break;
13542
13543 spe = bnx2x_sp_get_next(bp);
13544 *spe = *bp->cnic_kwq_cons;
13545
13546 bp->cnic_kwq_pending--;
13547
13548 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
13549 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13550
13551 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13552 bp->cnic_kwq_cons = bp->cnic_kwq;
13553 else
13554 bp->cnic_kwq_cons++;
13555 }
13556 bnx2x_sp_prod_update(bp);
13557 spin_unlock_bh(&bp->spq_lock);
13558}
13559
13560static int bnx2x_cnic_sp_queue(struct net_device *dev,
13561 struct kwqe_16 *kwqes[], u32 count)
13562{
13563 struct bnx2x *bp = netdev_priv(dev);
13564 int i;
13565
13566#ifdef BNX2X_STOP_ON_ERROR
13567 if (unlikely(bp->panic))
13568 return -EIO;
13569#endif
13570
13571 spin_lock_bh(&bp->spq_lock);
13572
13573 for (i = 0; i < count; i++) {
13574 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13575
13576 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13577 break;
13578
13579 *bp->cnic_kwq_prod = *spe;
13580
13581 bp->cnic_kwq_pending++;
13582
13583 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
13584 spe->hdr.conn_and_cmd_data, spe->hdr.type,
13585 spe->data.mac_config_addr.hi,
13586 spe->data.mac_config_addr.lo,
13587 bp->cnic_kwq_pending);
13588
13589 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13590 bp->cnic_kwq_prod = bp->cnic_kwq;
13591 else
13592 bp->cnic_kwq_prod++;
13593 }
13594
13595 spin_unlock_bh(&bp->spq_lock);
13596
13597 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13598 bnx2x_cnic_sp_post(bp, 0);
13599
13600 return i;
13601}
13602
13603static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13604{
13605 struct cnic_ops *c_ops;
13606 int rc = 0;
13607
13608 mutex_lock(&bp->cnic_mutex);
13609 c_ops = bp->cnic_ops;
13610 if (c_ops)
13611 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13612 mutex_unlock(&bp->cnic_mutex);
13613
13614 return rc;
13615}
13616
13617static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13618{
13619 struct cnic_ops *c_ops;
13620 int rc = 0;
13621
13622 rcu_read_lock();
13623 c_ops = rcu_dereference(bp->cnic_ops);
13624 if (c_ops)
13625 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13626 rcu_read_unlock();
13627
13628 return rc;
13629}
13630
13631/*
13632 * for commands that have no data
13633 */
13634static int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13635{
13636 struct cnic_ctl_info ctl = {0};
13637
13638 ctl.cmd = cmd;
13639
13640 return bnx2x_cnic_ctl_send(bp, &ctl);
13641}
13642
13643static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
13644{
13645 struct cnic_ctl_info ctl;
13646
13647 /* first we tell CNIC and only then we count this as a completion */
13648 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13649 ctl.data.comp.cid = cid;
13650
13651 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13652 bnx2x_cnic_sp_post(bp, 1);
13653}
13654
13655static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13656{
13657 struct bnx2x *bp = netdev_priv(dev);
13658 int rc = 0;
13659
13660 switch (ctl->cmd) {
13661 case DRV_CTL_CTXTBL_WR_CMD: {
13662 u32 index = ctl->data.io.offset;
13663 dma_addr_t addr = ctl->data.io.dma_addr;
13664
13665 bnx2x_ilt_wr(bp, index, addr);
13666 break;
13667 }
13668
13669 case DRV_CTL_COMPLETION_CMD: {
13670 int count = ctl->data.comp.comp_count;
13671
13672 bnx2x_cnic_sp_post(bp, count);
13673 break;
13674 }
13675
13676 /* rtnl_lock is held. */
13677 case DRV_CTL_START_L2_CMD: {
13678 u32 cli = ctl->data.ring.client_id;
13679
13680 bp->rx_mode_cl_mask |= (1 << cli);
13681 bnx2x_set_storm_rx_mode(bp);
13682 break;
13683 }
13684
13685 /* rtnl_lock is held. */
13686 case DRV_CTL_STOP_L2_CMD: {
13687 u32 cli = ctl->data.ring.client_id;
13688
13689 bp->rx_mode_cl_mask &= ~(1 << cli);
13690 bnx2x_set_storm_rx_mode(bp);
13691 break;
13692 }
13693
13694 default:
13695 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13696 rc = -EINVAL;
13697 }
13698
13699 return rc;
13700}
13701
13702static void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13703{
13704 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13705
13706 if (bp->flags & USING_MSIX_FLAG) {
13707 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13708 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13709 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13710 } else {
13711 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13712 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13713 }
13714 cp->irq_arr[0].status_blk = bp->cnic_sb;
13715 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
13716 cp->irq_arr[1].status_blk = bp->def_status_blk;
13717 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13718
13719 cp->num_irq = 2;
13720}
13721
13722static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13723 void *data)
13724{
13725 struct bnx2x *bp = netdev_priv(dev);
13726 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13727
13728 if (ops == NULL)
13729 return -EINVAL;
13730
13731 if (atomic_read(&bp->intr_sem) != 0)
13732 return -EBUSY;
13733
13734 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13735 if (!bp->cnic_kwq)
13736 return -ENOMEM;
13737
13738 bp->cnic_kwq_cons = bp->cnic_kwq;
13739 bp->cnic_kwq_prod = bp->cnic_kwq;
13740 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13741
13742 bp->cnic_spq_pending = 0;
13743 bp->cnic_kwq_pending = 0;
13744
13745 bp->cnic_data = data;
13746
13747 cp->num_irq = 0;
13748 cp->drv_state = CNIC_DRV_STATE_REGD;
13749
13750 bnx2x_init_sb(bp, bp->cnic_sb, bp->cnic_sb_mapping, CNIC_SB_ID(bp));
13751
13752 bnx2x_setup_cnic_irq_info(bp);
13753 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
13754 bp->cnic_flags |= BNX2X_CNIC_FLAG_MAC_SET;
13755 rcu_assign_pointer(bp->cnic_ops, ops);
13756
13757 return 0;
13758}
13759
13760static int bnx2x_unregister_cnic(struct net_device *dev)
13761{
13762 struct bnx2x *bp = netdev_priv(dev);
13763 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13764
13765 mutex_lock(&bp->cnic_mutex);
13766 if (bp->cnic_flags & BNX2X_CNIC_FLAG_MAC_SET) {
13767 bp->cnic_flags &= ~BNX2X_CNIC_FLAG_MAC_SET;
13768 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
13769 }
13770 cp->drv_state = 0;
13771 rcu_assign_pointer(bp->cnic_ops, NULL);
13772 mutex_unlock(&bp->cnic_mutex);
13773 synchronize_rcu();
13774 kfree(bp->cnic_kwq);
13775 bp->cnic_kwq = NULL;
13776
13777 return 0;
13778}
13779
13780struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13781{
13782 struct bnx2x *bp = netdev_priv(dev);
13783 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13784
13785 cp->drv_owner = THIS_MODULE;
13786 cp->chip_id = CHIP_ID(bp);
13787 cp->pdev = bp->pdev;
13788 cp->io_base = bp->regview;
13789 cp->io_base2 = bp->doorbells;
13790 cp->max_kwqe_pending = 8;
13791 cp->ctx_blk_size = CNIC_CTX_PER_ILT * sizeof(union cdu_context);
13792 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 1;
13793 cp->ctx_tbl_len = CNIC_ILT_LINES;
13794 cp->starting_cid = BCM_CNIC_CID_START;
13795 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13796 cp->drv_ctl = bnx2x_drv_ctl;
13797 cp->drv_register_cnic = bnx2x_register_cnic;
13798 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13799
13800 return cp;
13801}
13802EXPORT_SYMBOL(bnx2x_cnic_probe);
13803
13804#endif /* BCM_CNIC */
Vladislav Zolotarov94a78b72009-04-27 03:27:43 -070013805