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review.evervolv.com / android_kernel_htc_msm8960 / 225152437092241cb3f6ff5b97896684d856f844 / . / drivers / video / msm / mdp4_util.c
blob: df4c9e4e196cff0124952e7032e7b171986fd1a4 [file] [log] [blame]
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]1/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/hrtimer.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/debugfs.h>
25#include <linux/semaphore.h>
26#include <linux/uaccess.h>
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]27#include <linux/msm_mdp.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]28#include <asm/system.h>
29#include <asm/mach-types.h>
30#include <mach/hardware.h>
31#include "mdp.h"
32#include "msm_fb.h"
33#include "mdp4.h"
34
35struct mdp4_statistic mdp4_stat;
36
37unsigned is_mdp4_hw_reset(void)
38{
39 unsigned hw_reset = 0;
40
41 /* Only revisions > v2.1 may be reset or powered off/on at runtime */
42 if (mdp_hw_revision > MDP4_REVISION_V2_1) {
43 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
44 hw_reset = !inpdw(MDP_BASE + 0x003c);
45 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
46 }
47
48 return hw_reset;
49}
50
51void mdp4_sw_reset(ulong bits)
52{
53 /* MDP cmd block enable */
54 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
55
56 bits &= 0x1f; /* 5 bits */
57 outpdw(MDP_BASE + 0x001c, bits); /* MDP_SW_RESET */
58
59 while (inpdw(MDP_BASE + 0x001c) & bits) /* self clear when complete */
60 ;
61 /* MDP cmd block disable */
62 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
63
64 MSM_FB_DEBUG("mdp4_sw_reset: 0x%x\n", (int)bits);
65}
66
67void mdp4_overlay_cfg(int overlayer, int blt_mode, int refresh, int direct_out)
68{
69 ulong bits = 0;
70
71 if (blt_mode)
72 bits |= (1 << 3);
73 refresh &= 0x03; /* 2 bites */
74 bits |= (refresh << 1);
75 direct_out &= 0x01;
76 bits |= direct_out;
77 /* MDP cmd block enable */
78 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
79
80
81 if (overlayer == MDP4_MIXER0)
82 outpdw(MDP_BASE + 0x10004, bits); /* MDP_OVERLAY0_CFG */
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]83 else if (overlayer == MDP4_MIXER1)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]84 outpdw(MDP_BASE + 0x18004, bits); /* MDP_OVERLAY1_CFG */
85
86 MSM_FB_DEBUG("mdp4_overlay_cfg: 0x%x\n",
87 (int)inpdw(MDP_BASE + 0x10004));
88 /* MDP cmd block disable */
89 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
90}
91
92void mdp4_display_intf_sel(int output, ulong intf)
93{
94 ulong bits, mask, data;
95 /* MDP cmd block enable */
96 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
97
98 bits = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */
99
100 if (intf == DSI_VIDEO_INTF) {
101 data = 0x40; /* bit 6 */
102 intf = MDDI_LCDC_INTF;
103 if (output == SECONDARY_INTF_SEL) {
104 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
105 intf=%d\n", __func__, output, (int)intf);
106 }
107 } else if (intf == DSI_CMD_INTF) {
108 data = 0x80; /* bit 7 */
109 intf = MDDI_INTF;
110 if (output == EXTERNAL_INTF_SEL) {
111 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
112 intf=%d\n", __func__, output, (int)intf);
113 }
114 } else
115 data = 0;
116
117 mask = 0x03; /* 2 bits */
118 intf &= 0x03; /* 2 bits */
119
120 switch (output) {
121 case EXTERNAL_INTF_SEL:
122 intf <<= 4;
123 mask <<= 4;
124 break;
125 case SECONDARY_INTF_SEL:
126 intf &= 0x02; /* only MDDI and EBI2 support */
127 intf <<= 2;
128 mask <<= 2;
129 break;
130 default:
131 break;
132 }
133
134 intf |= data;
135 mask |= data;
136
137 bits &= ~mask;
138 bits |= intf;
139
140 outpdw(MDP_BASE + 0x0038, bits); /* MDP_DISP_INTF_SEL */
141 /* MDP cmd block disable */
142 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
143
144 MSM_FB_DEBUG("mdp4_display_intf_sel: 0x%x\n", (int)inpdw(MDP_BASE + 0x0038));
145}
146
147unsigned long mdp4_display_status(void)
148{
149 ulong status;
150 /* MDP cmd block enable */
151 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
152
153 status = inpdw(MDP_BASE + 0x0018) & 0x3ff; /* MDP_DISPLAY_STATUS */
154
155 /* MDP cmd block disable */
156 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
157 return status;
158}
159
160void mdp4_ebi2_lcd_setup(int lcd, ulong base, int ystride)
161{
162 /* always use memory map */
163 ystride &= 0x01fff; /* 13 bits */
164 /* MDP cmd block enable */
165 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
166
167 if (lcd == EBI2_LCD0) {
168 outpdw(MDP_BASE + 0x0060, base);/* MDP_EBI2_LCD0 */
169 outpdw(MDP_BASE + 0x0068, ystride);/* MDP_EBI2_LCD0_YSTRIDE */
170 } else {
171 outpdw(MDP_BASE + 0x0064, base);/* MDP_EBI2_LCD1 */
172 outpdw(MDP_BASE + 0x006c, ystride);/* MDP_EBI2_LCD1_YSTRIDE */
173 }
174 /* MDP cmd block disable */
175 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
176}
177
178void mdp4_mddi_setup(int mddi, unsigned long id)
179{
180 ulong bits;
181
182 if (mddi == MDDI_EXTERNAL_SET)
183 bits = 0x02;
184 else if (mddi == MDDI_SECONDARY_SET)
185 bits = 0x01;
186 else
187 bits = 0; /* PRIMARY_SET */
188
189 id <<= 16;
190
191 bits |= id;
192 /* MDP cmd block enable */
193 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
194
195 outpdw(MDP_BASE + 0x0090, bits); /* MDP_MDDI_PARAM_WR_SEL */
196 /* MDP cmd block disable */
197 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
198}
199
200int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req)
201{
202
203 /* not implemented yet */
204 return -1;
205}
206
207void mdp4_fetch_cfg(uint32 core_clk)
208{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]209 uint32 dmap_data, vg_data;
210 char *base;
211 int i;
212 /* MDP cmd block enable */
213 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
214
Adrian Salido-Moreno3436dae2011-08-08 12:13:07 -0700[diff] [blame]215 if (mdp_rev >= MDP_REV_41 || core_clk >= 90000000) { /* 90 Mhz */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]216 dmap_data = 0x47; /* 16 bytes-burst x 8 req */
217 vg_data = 0x47; /* 16 bytes-burs x 8 req */
218 } else {
219 dmap_data = 0x27; /* 8 bytes-burst x 8 req */
220 vg_data = 0x43; /* 16 bytes-burst x 4 req */
221 }
222
223 MSM_FB_DEBUG("mdp4_fetch_cfg: dmap=%x vg=%x\n",
224 dmap_data, vg_data);
225
226 /* dma_p fetch config */
227 outpdw(MDP_BASE + 0x91004, dmap_data);
228 /* dma_e fetch config */
229 outpdw(MDP_BASE + 0xB1004, dmap_data);
230
231 /*
232 * set up two vg pipes and two rgb pipes
233 */
234 base = MDP_BASE + MDP4_VIDEO_BASE;
235 for (i = 0; i < 4; i++) {
236 outpdw(base + 0x1004, vg_data);
237 base += MDP4_VIDEO_OFF;
238 }
239 /* MDP cmd block disable */
240 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
241}
242
243void mdp4_hw_init(void)
244{
245 ulong bits;
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]246 uint32 clk_rate;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]247
248 /* MDP cmd block enable */
249 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
250
Nagamalleswararao Ganji074ee022011-09-02 12:06:37 -0700[diff] [blame]251 mdp4_update_perf_level(OVERLAY_PERF_LEVEL4);
252
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]253#ifdef MDP4_ERROR
254 /*
255 * Issue software reset on DMA_P will casue DMA_P dma engine stall
256 * on LCDC mode. However DMA_P does not stall at MDDI mode.
257 * This need further investigation.
258 */
259 mdp4_sw_reset(0x17);
260#endif
261
kuogee hsieh4b910f22011-11-15 09:43:04 -0800[diff] [blame]262 if (mdp_rev > MDP_REV_41) {
263 /* mdp chip select controller */
264 outpdw(MDP_BASE + 0x00c0, CS_CONTROLLER_0);
265 outpdw(MDP_BASE + 0x00c4, CS_CONTROLLER_1);
266 }
267
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]268 mdp4_clear_lcdc();
269
270 mdp4_mixer_blend_init(0);
271 mdp4_mixer_blend_init(1);
272 mdp4_vg_qseed_init(0);
273 mdp4_vg_qseed_init(1);
274
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]275 mdp4_vg_csc_setup(0);
276 mdp4_vg_csc_setup(1);
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]277 mdp4_mixer_csc_setup(1);
278 mdp4_mixer_csc_setup(2);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]279 mdp4_dmap_csc_setup();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]280
Ravishangar Kalyaname7833e22011-07-22 16:20:19 -0700[diff] [blame]281 if (mdp_rev <= MDP_REV_41) {
282 mdp4_mixer_gc_lut_setup(0);
283 mdp4_mixer_gc_lut_setup(1);
284 }
285
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]286 mdp4_vg_igc_lut_setup(0);
287 mdp4_vg_igc_lut_setup(1);
288
289 mdp4_rgb_igc_lut_setup(0);
290 mdp4_rgb_igc_lut_setup(1);
291
292 outp32(MDP_EBI2_PORTMAP_MODE, 0x3);
293
294 /* system interrupts */
295
296 bits = mdp_intr_mask;
297 outpdw(MDP_BASE + 0x0050, bits);/* enable specififed interrupts */
298
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]299 /* For the max read pending cmd config below, if the MDP clock */
300 /* is less than the AXI clock, then we must use 3 pending */
301 /* pending requests. Otherwise, we should use 8 pending requests. */
302 /* In the future we should do this detection automatically. */
303
304 /* max read pending cmd config */
305 outpdw(MDP_BASE + 0x004c, 0x02222); /* 3 pending requests */
306
307#ifndef CONFIG_FB_MSM_OVERLAY
308 /* both REFRESH_MODE and DIRECT_OUT are ignored at BLT mode */
309 mdp4_overlay_cfg(MDP4_MIXER0, OVERLAY_MODE_BLT, 0, 0);
310 mdp4_overlay_cfg(MDP4_MIXER1, OVERLAY_MODE_BLT, 0, 0);
311#endif
312
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]313 clk_rate = mdp_get_core_clk();
314 mdp4_fetch_cfg(clk_rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]315
316 /* Mark hardware as initialized. Only revisions > v2.1 have a register
317 * for tracking core reset status. */
318 if (mdp_hw_revision > MDP4_REVISION_V2_1)
319 outpdw(MDP_BASE + 0x003c, 1);
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]320
321 /* MDP cmd block disable */
322 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]323}
324
325
326void mdp4_clear_lcdc(void)
327{
328 uint32 bits;
329
330 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
331
332 bits = inpdw(MDP_BASE + 0xc0000);
333 if (bits & 0x01) { /* enabled already */
334 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
335 return;
336 }
337
338 outpdw(MDP_BASE + 0xc0004, 0); /* vsync ctrl out */
339 outpdw(MDP_BASE + 0xc0008, 0); /* vsync period */
340 outpdw(MDP_BASE + 0xc000c, 0); /* vsync pusle width */
341 outpdw(MDP_BASE + 0xc0010, 0); /* lcdc display HCTL */
342 outpdw(MDP_BASE + 0xc0014, 0); /* lcdc display v start */
343 outpdw(MDP_BASE + 0xc0018, 0); /* lcdc display v end */
344 outpdw(MDP_BASE + 0xc001c, 0); /* lcdc active hctl */
345 outpdw(MDP_BASE + 0xc0020, 0); /* lcdc active v start */
346 outpdw(MDP_BASE + 0xc0024, 0); /* lcdc active v end */
347 outpdw(MDP_BASE + 0xc0028, 0); /* lcdc board color */
348 outpdw(MDP_BASE + 0xc002c, 0); /* lcdc underflow ctrl */
349 outpdw(MDP_BASE + 0xc0030, 0); /* lcdc hsync skew */
350 outpdw(MDP_BASE + 0xc0034, 0); /* lcdc test ctl */
351 outpdw(MDP_BASE + 0xc0038, 0); /* lcdc ctl polarity */
352
353 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
354}
355
356irqreturn_t mdp4_isr(int irq, void *ptr)
357{
358 uint32 isr, mask, panel;
359 struct mdp_dma_data *dma;
360
361 mdp_is_in_isr = TRUE;
362
363 /* complete all the reads before reading the interrupt
364 * status register - eliminate effects of speculative
365 * reads by the cpu
366 */
367 rmb();
368 isr = inpdw(MDP_INTR_STATUS);
369 if (isr == 0)
370 goto out;
371
372 mdp4_stat.intr_tot++;
373 mask = inpdw(MDP_INTR_ENABLE);
374 outpdw(MDP_INTR_CLEAR, isr);
375
376 if (isr & INTR_PRIMARY_INTF_UDERRUN) {
377 mdp4_stat.intr_underrun_p++;
378 /* When underun occurs mdp clear the histogram registers
379 that are set before in hw_init so restore them back so
380 that histogram works.*/
381 MDP_OUTP(MDP_BASE + 0x95010, 1);
382 outpdw(MDP_BASE + 0x9501c, INTR_HIST_DONE);
Carl Vanderlip6cc11c42012-02-07 15:25:46 -0800[diff] [blame]383 mdp_is_hist_valid = FALSE;
384 __mdp_histogram_reset();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]385 }
386
387 if (isr & INTR_EXTERNAL_INTF_UDERRUN)
388 mdp4_stat.intr_underrun_e++;
389
390 isr &= mask;
391
392 if (isr == 0)
393 goto out;
394
395 panel = mdp4_overlay_panel_list();
396 if (isr & INTR_PRIMARY_VSYNC) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]397 mdp4_stat.intr_vsync_p++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]398 dma = &dma2_data;
399 spin_lock(&mdp_spin_lock);
400 mdp_intr_mask &= ~INTR_PRIMARY_VSYNC;
401 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
402 dma->waiting = FALSE;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]403 if (panel & MDP4_PANEL_LCDC)
404 mdp4_primary_vsync_lcdc();
405#ifdef CONFIG_FB_MSM_MIPI_DSI
406 else if (panel & MDP4_PANEL_DSI_VIDEO)
407 mdp4_primary_vsync_dsi_video();
408#endif
kuogee hsieh3de11f32011-07-08 14:09:11 -0700[diff] [blame]409 spin_unlock(&mdp_spin_lock);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]410 }
411#ifdef CONFIG_FB_MSM_DTV
412 if (isr & INTR_EXTERNAL_VSYNC) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]413 mdp4_stat.intr_vsync_e++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]414 dma = &dma_e_data;
415 spin_lock(&mdp_spin_lock);
416 mdp_intr_mask &= ~INTR_EXTERNAL_VSYNC;
417 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
418 dma->waiting = FALSE;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]419 if (panel & MDP4_PANEL_DTV)
420 mdp4_external_vsync_dtv();
kuogee hsieh3de11f32011-07-08 14:09:11 -0700[diff] [blame]421 spin_unlock(&mdp_spin_lock);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]422 }
423#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]424
425#ifdef CONFIG_FB_MSM_OVERLAY
426 if (isr & INTR_OVERLAY0_DONE) {
427 mdp4_stat.intr_overlay0++;
428 dma = &dma2_data;
429 if (panel & (MDP4_PANEL_LCDC | MDP4_PANEL_DSI_VIDEO)) {
430 /* disable LCDC interrupt */
431 spin_lock(&mdp_spin_lock);
432 mdp_intr_mask &= ~INTR_OVERLAY0_DONE;
433 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
434 dma->waiting = FALSE;
435 spin_unlock(&mdp_spin_lock);
436 if (panel & MDP4_PANEL_LCDC)
437 mdp4_overlay0_done_lcdc(dma);
438#ifdef CONFIG_FB_MSM_MIPI_DSI
439 else if (panel & MDP4_PANEL_DSI_VIDEO)
440 mdp4_overlay0_done_dsi_video(dma);
441#endif
442 } else { /* MDDI, DSI_CMD */
443#ifdef CONFIG_FB_MSM_MIPI_DSI
444 if (panel & MDP4_PANEL_DSI_CMD)
445 mdp4_overlay0_done_dsi_cmd(dma);
446#else
447 if (panel & MDP4_PANEL_MDDI)
448 mdp4_overlay0_done_mddi(dma);
449#endif
450 }
451 mdp_hw_cursor_done();
452 }
453 if (isr & INTR_OVERLAY1_DONE) {
454 mdp4_stat.intr_overlay1++;
455 /* disable DTV interrupt */
456 dma = &dma_e_data;
457 spin_lock(&mdp_spin_lock);
458 mdp_intr_mask &= ~INTR_OVERLAY1_DONE;
459 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
460 dma->waiting = FALSE;
461 spin_unlock(&mdp_spin_lock);
462#if defined(CONFIG_FB_MSM_DTV)
463 if (panel & MDP4_PANEL_DTV)
464 mdp4_overlay1_done_dtv();
465#endif
466#if defined(CONFIG_FB_MSM_TVOUT)
467 if (panel & MDP4_PANEL_ATV)
468 mdp4_overlay1_done_atv();
469#endif
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]470 }
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]471#if defined(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL)
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]472 if (isr & INTR_OVERLAY2_DONE) {
473 mdp4_stat.intr_overlay2++;
474 /* disable DTV interrupt */
475 dma = &dma_wb_data;
476 spin_lock(&mdp_spin_lock);
477 mdp_intr_mask &= ~INTR_OVERLAY2_DONE;
478 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
479 dma->waiting = FALSE;
480 spin_unlock(&mdp_spin_lock);
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]481 if (panel & MDP4_PANEL_WRITEBACK)
482 mdp4_overlay1_done_writeback(dma);
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]483 }
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]484#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]485#endif /* OVERLAY */
486
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]487 if (isr & INTR_DMA_P_DONE) {
488 mdp4_stat.intr_dma_p++;
489 dma = &dma2_data;
490 if (panel & MDP4_PANEL_LCDC) {
491 /* disable LCDC interrupt */
492 spin_lock(&mdp_spin_lock);
493 mdp_intr_mask &= ~INTR_DMA_P_DONE;
494 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
495 dma->waiting = FALSE;
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]496 mdp4_dma_p_done_lcdc();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]497 spin_unlock(&mdp_spin_lock);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]498 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]499#ifdef CONFIG_FB_MSM_OVERLAY
500#ifdef CONFIG_FB_MSM_MIPI_DSI
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]501 else if (panel & MDP4_PANEL_DSI_VIDEO) {
502 /* disable LCDC interrupt */
503 spin_lock(&mdp_spin_lock);
504 mdp_intr_mask &= ~INTR_DMA_P_DONE;
505 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
506 dma->waiting = FALSE;
507 mdp4_dma_p_done_dsi_video();
508 spin_unlock(&mdp_spin_lock);
509 } else if (panel & MDP4_PANEL_DSI_CMD) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]510 mdp4_dma_p_done_dsi(dma);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]511 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]512#else
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]513 else { /* MDDI */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]514 mdp4_dma_p_done_mddi();
515 mdp_pipe_ctrl(MDP_DMA2_BLOCK,
516 MDP_BLOCK_POWER_OFF, TRUE);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]517 complete(&dma->comp);
518 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]519#endif
520#else
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]521 else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]522 spin_lock(&mdp_spin_lock);
523 dma->busy = FALSE;
524 spin_unlock(&mdp_spin_lock);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]525 complete(&dma->comp);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]526 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]527#endif
528 }
529 if (isr & INTR_DMA_S_DONE) {
530 mdp4_stat.intr_dma_s++;
531#if defined(CONFIG_FB_MSM_OVERLAY) && defined(CONFIG_FB_MSM_MDDI)
532 dma = &dma2_data;
533#else
534 dma = &dma_s_data;
535#endif
536
537 dma->busy = FALSE;
538 mdp_pipe_ctrl(MDP_DMA_S_BLOCK,
539 MDP_BLOCK_POWER_OFF, TRUE);
540 complete(&dma->comp);
541 }
542 if (isr & INTR_DMA_E_DONE) {
543 mdp4_stat.intr_dma_e++;
544 dma = &dma_e_data;
545 spin_lock(&mdp_spin_lock);
546 mdp_intr_mask &= ~INTR_DMA_E_DONE;
547 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
548 dma->busy = FALSE;
Huaibin Yang0da46922011-11-29 15:08:04 -0800[diff] [blame]549 mdp4_dma_e_done_dtv();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]550 if (dma->waiting) {
551 dma->waiting = FALSE;
552 complete(&dma->comp);
553 }
554 spin_unlock(&mdp_spin_lock);
555 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]556 if (isr & INTR_DMA_P_HISTOGRAM) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]557 mdp4_stat.intr_histogram++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]558 isr = inpdw(MDP_DMA_P_HIST_INTR_STATUS);
559 mask = inpdw(MDP_DMA_P_HIST_INTR_ENABLE);
560 outpdw(MDP_DMA_P_HIST_INTR_CLEAR, isr);
Ravishangar Kalyanam115d7972011-08-09 12:52:14 -0700[diff] [blame]561 mb();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]562 isr &= mask;
Carl Vanderlip6cc11c42012-02-07 15:25:46 -0800[diff] [blame]563 if (isr & INTR_HIST_RESET_SEQ_DONE)
564 __mdp_histogram_kickoff();
565
Carl Vanderlipe2833e92011-09-27 13:26:01 -0700[diff] [blame]566 if (isr & INTR_HIST_DONE) {
Carl Vanderlip6cc11c42012-02-07 15:25:46 -0800[diff] [blame]567 if (waitqueue_active(&mdp_hist_comp.wait)) {
568 if (!queue_work(mdp_hist_wq,
569 &mdp_histogram_worker)) {
570 pr_err("%s - can't queue hist_read\n",
571 __func__);
Carl Vanderlipe2833e92011-09-27 13:26:01 -0700[diff] [blame]572 }
Carl Vanderlip6cc11c42012-02-07 15:25:46 -0800[diff] [blame]573 } else
574 __mdp_histogram_reset();
Carl Vanderlipe2833e92011-09-27 13:26:01 -0700[diff] [blame]575 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]576 }
577
578out:
579 mdp_is_in_isr = FALSE;
580
581 return IRQ_HANDLED;
582}
583
584
585/*
586 * QSEED tables
587 */
588
589static uint32 vg_qseed_table0[] = {
590 0x5556aaff, 0x00000000, 0x00000000, 0x00000000
591};
592
593static uint32 vg_qseed_table1[] = {
594 0x76543210, 0xfedcba98
595};
596
597static uint32 vg_qseed_table2[] = {
598 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
599 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
600 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
601 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
602 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
603 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
604 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
605 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
606 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
607 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
608 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
609 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
610 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
611 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
612 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
613 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
614
615 0x02000000, 0x00000000, 0x02000000, 0x00000000,
616 0x02000000, 0x00000000, 0x02000000, 0x00000000,
617 0x02000000, 0x00000000, 0x02000000, 0x00000000,
618 0x02000000, 0x00000000, 0x02000000, 0x00000000,
619 0x02000000, 0x00000000, 0x02000000, 0x00000000,
620 0x02000000, 0x00000000, 0x02000000, 0x00000000,
621 0x02000000, 0x00000000, 0x02000000, 0x00000000,
622 0x02000000, 0x00000000, 0x02000000, 0x00000000,
623 0x02000000, 0x00000000, 0x02000000, 0x00000000,
624 0x02000000, 0x00000000, 0x02000000, 0x00000000,
625 0x02000000, 0x00000000, 0x02000000, 0x00000000,
626 0x02000000, 0x00000000, 0x02000000, 0x00000000,
627 0x02000000, 0x00000000, 0x02000000, 0x00000000,
628 0x02000000, 0x00000000, 0x02000000, 0x00000000,
629 0x02000000, 0x00000000, 0x02000000, 0x00000000,
630 0x02000000, 0x00000000, 0x02000000, 0x00000000,
631
632 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
633 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
634 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
635 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
636 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
637 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
638 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
639 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
640 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
641 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
642 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
643 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
644 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
645 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
646 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
647 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
648
649 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
650 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
651 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
652 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
653 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
654 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
655 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
656 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
657 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
658 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
659 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
660 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
661 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
662 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
663 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
664 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
665
666 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
667 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
668 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
669 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
670 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
671 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
672 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
673 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
674 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
675 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
676 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
677 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
678 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
679 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
680 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
681 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
682
683 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
684 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
685 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
686 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
687 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
688 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
689 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
690 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
691 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
692 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
693 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
694 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
695 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
696 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
697 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
698 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
699
700 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
701 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
702 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
703 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
704 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
705 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
706 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
707 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
708 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
709 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
710 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
711 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
712 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
713 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
714 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
715 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
716
717 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
718 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
719 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
720 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
721 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
722 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
723 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
724 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
725 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
726 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
727 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
728 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
729 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
730 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
731 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
732 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
733
734 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
735 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
736 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
737 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
738 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
739 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
740 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
741 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
742 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
743 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
744 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
745 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
746 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
747 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
748 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
749 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
750
751 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
752 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
753 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
754 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
755 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
756 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
757 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
758 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
759 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
760 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
761 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
762 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
763 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
764 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
765 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
766 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
767
768 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
769 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
770 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
771 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
772 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
773 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
774 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
775 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
776 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
777 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
778 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
779 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
780 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
781 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
782 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
783 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
784
785 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
786 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
787 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
788 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
789 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
790 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
791 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
792 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
793 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
794 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
795 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
796 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
797 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
798 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
799 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
800 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
801
802 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
803 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
804 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
805 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
806 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
807 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
808 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
809 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
810 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
811 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
812 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
813 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
814 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
815 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
816 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
817 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
818
819 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
820 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
821 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
822 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
823 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
824 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
825 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
826 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
827 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
828 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
829 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
830 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
831 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
832 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
833 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
834 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
835
836 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
837 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
838 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
839 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
840 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
841 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
842 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
843 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
844 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
845 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
846 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
847 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
848 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
849 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
850 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
851 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
852
853 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
854 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
855 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
856 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
857 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
858 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
859 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
860 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
861 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
862 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
863 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
864 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
865 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
866 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
867 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
868 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e,
869
870 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
871 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
872 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
873 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
874 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
875 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
876 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
877 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
878 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
879 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
880 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
881 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
882 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
883 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
884 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
885 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
886
887 0x02000000, 0x00000000, 0x02000000, 0x00000000,
888 0x02000000, 0x00000000, 0x02000000, 0x00000000,
889 0x02000000, 0x00000000, 0x02000000, 0x00000000,
890 0x02000000, 0x00000000, 0x02000000, 0x00000000,
891 0x02000000, 0x00000000, 0x02000000, 0x00000000,
892 0x02000000, 0x00000000, 0x02000000, 0x00000000,
893 0x02000000, 0x00000000, 0x02000000, 0x00000000,
894 0x02000000, 0x00000000, 0x02000000, 0x00000000,
895 0x02000000, 0x00000000, 0x02000000, 0x00000000,
896 0x02000000, 0x00000000, 0x02000000, 0x00000000,
897 0x02000000, 0x00000000, 0x02000000, 0x00000000,
898 0x02000000, 0x00000000, 0x02000000, 0x00000000,
899 0x02000000, 0x00000000, 0x02000000, 0x00000000,
900 0x02000000, 0x00000000, 0x02000000, 0x00000000,
901 0x02000000, 0x00000000, 0x02000000, 0x00000000,
902 0x02000000, 0x00000000, 0x02000000, 0x00000000,
903
904 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
905 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
906 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
907 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
908 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
909 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
910 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
911 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
912 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
913 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
914 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
915 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
916 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
917 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
918 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
919 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
920
921 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
922 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
923 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
924 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
925 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
926 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
927 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
928 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
929 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
930 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
931 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
932 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
933 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
934 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
935 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
936 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
937
938 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
939 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
940 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
941 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
942 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
943 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
944 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
945 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
946 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
947 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
948 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
949 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
950 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
951 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
952 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
953 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
954
955 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
956 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
957 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
958 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
959 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
960 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
961 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
962 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
963 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
964 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
965 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
966 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
967 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
968 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
969 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
970 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
971
972 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
973 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
974 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
975 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
976 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
977 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
978 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
979 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
980 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
981 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
982 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
983 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
984 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
985 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
986 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
987 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
988
989 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
990 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
991 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
992 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
993 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
994 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
995 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
996 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
997 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
998 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
999 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
1000 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
1001 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
1002 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
1003 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
1004 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
1005
1006 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
1007 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
1008 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
1009 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
1010 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
1011 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
1012 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
1013 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
1014 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
1015 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
1016 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
1017 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
1018 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
1019 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
1020 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
1021 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
1022
1023 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
1024 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
1025 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
1026 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
1027 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
1028 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
1029 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
1030 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
1031 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
1032 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
1033 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
1034 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
1035 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
1036 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
1037 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
1038 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
1039
1040 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
1041 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
1042 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
1043 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
1044 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
1045 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
1046 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
1047 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
1048 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
1049 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
1050 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
1051 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
1052 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
1053 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
1054 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
1055 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
1056
1057 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
1058 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
1059 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
1060 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
1061 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
1062 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
1063 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
1064 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
1065 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
1066 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
1067 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
1068 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
1069 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
1070 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
1071 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
1072 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
1073
1074 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
1075 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
1076 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
1077 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
1078 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
1079 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
1080 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
1081 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
1082 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
1083 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
1084 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
1085 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
1086 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
1087 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
1088 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
1089 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
1090
1091 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
1092 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
1093 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
1094 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
1095 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
1096 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
1097 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
1098 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
1099 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
1100 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
1101 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
1102 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
1103 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
1104 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
1105 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
1106 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
1107
1108 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
1109 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
1110 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
1111 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
1112 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
1113 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
1114 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
1115 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
1116 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
1117 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
1118 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
1119 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
1120 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
1121 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
1122 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
1123 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
1124
1125 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
1126 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
1127 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
1128 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
1129 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
1130 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
1131 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
1132 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
1133 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
1134 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
1135 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
1136 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
1137 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
1138 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
1139 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
1140 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e
1141};
1142
1143
1144#define MDP4_QSEED_TABLE0_OFF 0x8100
1145#define MDP4_QSEED_TABLE1_OFF 0x8200
1146#define MDP4_QSEED_TABLE2_OFF 0x9000
1147
1148void mdp4_vg_qseed_init(int vp_num)
1149{
1150 uint32 *off;
1151 int i, voff;
1152
1153 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1154
1155 voff = MDP4_VIDEO_OFF * vp_num;
1156 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1157 MDP4_QSEED_TABLE0_OFF);
1158 for (i = 0; i < (sizeof(vg_qseed_table0) / sizeof(uint32)); i++) {
1159 outpdw(off, vg_qseed_table0[i]);
1160 off++;
1161 /* This code is added to workaround the 1K Boundary AXI
1162 Interleave operations from Scorpion that can potentially
1163 corrupt the QSEED table. The idea is to complete the prevous
1164 to the buffer before making the next write when address is
1165 1KB aligned to ensure the write has been committed prior to
1166 next instruction write that can go out from the secondary AXI
1167 port.This happens also because of the expected write sequence
1168 from QSEED table, where LSP has to be written first then the
1169 MSP to trigger both to write out to SRAM, if this has not been
1170 the expectation, then corruption wouldn't have happened.*/
1171
1172 if (!((uint32)off & 0x3FF))
1173 wmb();
1174 }
1175
1176 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1177 MDP4_QSEED_TABLE1_OFF);
1178 for (i = 0; i < (sizeof(vg_qseed_table1) / sizeof(uint32)); i++) {
1179 outpdw(off, vg_qseed_table1[i]);
1180 off++;
1181 if (!((uint32)off & 0x3FF))
1182 wmb();
1183 }
1184
1185 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1186 MDP4_QSEED_TABLE2_OFF);
1187 for (i = 0; i < (sizeof(vg_qseed_table2) / sizeof(uint32)); i++) {
1188 outpdw(off, vg_qseed_table2[i]);
1189 off++;
1190 if (!((uint32)off & 0x3FF))
1191 wmb();
1192 }
1193
1194 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1195
1196}
1197
1198void mdp4_mixer_blend_init(mixer_num)
1199{
1200 unsigned char *overlay_base;
1201 int off;
1202
1203 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1204 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1205 else
1206 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1207
1208 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1209
1210 /* stage 0 to stage 2 */
1211 off = 0;
1212 outpdw(overlay_base + off + 0x104, 0x010);
1213 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1214 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1215
1216 off += 0x20;
1217 outpdw(overlay_base + off + 0x104, 0x010);
1218 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1219 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1220
1221 off += 0x20;
1222 outpdw(overlay_base + off + 0x104, 0x010);
1223 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1224 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1225
1226 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1227}
1228
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1229struct mdp_csc_cfg mdp_csc_convert[4] = {
1230 { /*RGB2RGB*/
1231 0,
1232 {
1233 0x0200, 0x0000, 0x0000,
1234 0x0000, 0x0200, 0x0000,
1235 0x0000, 0x0000, 0x0200,
1236 },
1237 { 0x0, 0x0, 0x0, },
1238 { 0x0, 0x0, 0x0, },
1239 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1240 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1241 },
1242 { /*YUV2RGB*/
1243 0,
1244 {
1245 0x0254, 0x0000, 0x0331,
1246 0x0254, 0xff37, 0xfe60,
1247 0x0254, 0x0409, 0x0000,
1248 },
1249 { 0xfff0, 0xff80, 0xff80, },
1250 { 0x0, 0x0, 0x0, },
1251 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1252 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1253 },
1254 { /*RGB2YUV*/
1255 0,
1256 {
1257 0x0083, 0x0102, 0x0032,
1258 0x1fb5, 0x1f6c, 0x00e1,
1259 0x00e1, 0x1f45, 0x1fdc
1260 },
1261 { 0x0, 0x0, 0x0, },
1262 { 0x0010, 0x0080, 0x0080, },
1263 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1264 { 0x0010, 0x00eb, 0x0010, 0x00f0, 0x0010, 0x00f0, },
1265 },
1266 { /*YUV2YUV ???*/
1267 0,
1268 {
1269 0x0200, 0x0000, 0x0000,
1270 0x0000, 0x0200, 0x0000,
1271 0x0000, 0x0000, 0x0200,
1272 },
1273 { 0x0, 0x0, 0x0, },
1274 { 0x0, 0x0, 0x0, },
1275 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1276 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1277 },
1278};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1279
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1280struct mdp_csc_cfg csc_matrix[3] = {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1281 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1282 (MDP_CSC_FLAG_YUV_OUT),
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1283 {
1284 0x0254, 0x0000, 0x0331,
1285 0x0254, 0xff37, 0xfe60,
1286 0x0254, 0x0409, 0x0000,
1287 },
1288 {
1289 0xfff0, 0xff80, 0xff80,
1290 },
1291 {
1292 0, 0, 0,
1293 },
1294 {
1295 0, 0xff, 0, 0xff, 0, 0xff,
1296 },
1297 {
1298 0, 0xff, 0, 0xff, 0, 0xff,
1299 },
1300 },
1301 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1302 (MDP_CSC_FLAG_YUV_OUT),
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1303 {
1304 0x0254, 0x0000, 0x0331,
1305 0x0254, 0xff37, 0xfe60,
1306 0x0254, 0x0409, 0x0000,
1307 },
1308 {
1309 0xfff0, 0xff80, 0xff80,
1310 },
1311 {
1312 0, 0, 0,
1313 },
1314 {
1315 0, 0xff, 0, 0xff, 0, 0xff,
1316 },
1317 {
1318 0, 0xff, 0, 0xff, 0, 0xff,
1319 },
1320 },
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1321 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1322 (0),
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1323 {
1324 0x0200, 0x0000, 0x0000,
1325 0x0000, 0x0200, 0x0000,
1326 0x0000, 0x0000, 0x0200,
1327 },
1328 {
1329 0x0, 0x0, 0x0,
1330 },
1331 {
1332 0, 0, 0,
1333 },
1334 {
1335 0, 0xff, 0, 0xff, 0, 0xff,
1336 },
1337 {
1338 0, 0xff, 0, 0xff, 0, 0xff,
1339 },
1340 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1341};
1342
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1343
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1344
1345#define MDP4_CSC_MV_OFF 0x4400
1346#define MDP4_CSC_PRE_BV_OFF 0x4500
1347#define MDP4_CSC_POST_BV_OFF 0x4580
1348#define MDP4_CSC_PRE_LV_OFF 0x4600
1349#define MDP4_CSC_POST_LV_OFF 0x4680
1350
1351void mdp4_vg_csc_mv_setup(int vp_num)
1352{
1353 uint32 *off;
1354 int i, voff;
1355
1356 voff = MDP4_VIDEO_OFF * vp_num;
1357 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1358 MDP4_CSC_MV_OFF);
1359
1360 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1361 for (i = 0; i < 9; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1362 outpdw(off, csc_matrix[vp_num].csc_mv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1363 off++;
1364 }
1365 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1366}
1367
1368void mdp4_vg_csc_pre_bv_setup(int vp_num)
1369{
1370 uint32 *off;
1371 int i, voff;
1372
1373 voff = MDP4_VIDEO_OFF * vp_num;
1374 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1375 MDP4_CSC_PRE_BV_OFF);
1376
1377 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1378 for (i = 0; i < 3; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1379 outpdw(off, csc_matrix[vp_num].csc_pre_bv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1380 off++;
1381 }
1382 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1383}
1384
1385void mdp4_vg_csc_post_bv_setup(int vp_num)
1386{
1387 uint32 *off;
1388 int i, voff;
1389
1390 voff = MDP4_VIDEO_OFF * vp_num;
1391 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1392 MDP4_CSC_POST_BV_OFF);
1393
1394 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1395 for (i = 0; i < 3; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1396 outpdw(off, csc_matrix[vp_num].csc_post_bv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1397 off++;
1398 }
1399 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1400}
1401
1402void mdp4_vg_csc_pre_lv_setup(int vp_num)
1403{
1404 uint32 *off;
1405 int i, voff;
1406
1407 voff = MDP4_VIDEO_OFF * vp_num;
1408 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1409 MDP4_CSC_PRE_LV_OFF);
1410
1411 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1412 for (i = 0; i < 6; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1413 outpdw(off, csc_matrix[vp_num].csc_pre_lv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1414 off++;
1415 }
1416 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1417}
1418
1419void mdp4_vg_csc_post_lv_setup(int vp_num)
1420{
1421 uint32 *off;
1422 int i, voff;
1423
1424 voff = MDP4_VIDEO_OFF * vp_num;
1425 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1426 MDP4_CSC_POST_LV_OFF);
1427
1428 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1429 for (i = 0; i < 6; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1430 outpdw(off, csc_matrix[vp_num].csc_post_lv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1431 off++;
1432 }
1433 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1434}
1435
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1436void mdp4_vg_csc_convert_setup(int vp_num)
1437{
1438 struct mdp_csc_cfg_data cfg;
1439
1440 switch (vp_num) {
1441 case 0:
1442 cfg.block = MDP_BLOCK_VG_1;
1443 break;
1444 case 1:
1445 cfg.block = MDP_BLOCK_VG_2;
1446 break;
1447 default:
1448 pr_err("%s - invalid vp_num = %d", __func__, vp_num);
1449 return;
1450 }
1451 cfg.csc_data = csc_matrix[vp_num];
1452 mdp4_csc_enable(&cfg);
1453}
1454
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1455void mdp4_vg_csc_setup(int vp_num)
1456{
1457 /* yuv2rgb */
1458 mdp4_vg_csc_mv_setup(vp_num);
1459 mdp4_vg_csc_pre_bv_setup(vp_num);
1460 mdp4_vg_csc_post_bv_setup(vp_num);
1461 mdp4_vg_csc_pre_lv_setup(vp_num);
1462 mdp4_vg_csc_post_lv_setup(vp_num);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1463 mdp4_vg_csc_convert_setup(vp_num);
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1464}
1465void mdp4_vg_csc_update(struct mdp_csc *p)
1466{
1467 struct mdp4_overlay_pipe *pipe;
1468 int vp_num;
1469
1470 pipe = mdp4_overlay_ndx2pipe(p->id);
1471 if (pipe == NULL) {
1472 pr_err("%s: p->id = %d Error\n", __func__, p->id);
1473 return;
1474 }
1475
1476 vp_num = pipe->pipe_num - OVERLAY_PIPE_VG1;
1477
1478 if (vp_num == 0 || vp_num == 1) {
1479 memcpy(csc_matrix[vp_num].csc_mv, p->csc_mv, sizeof(p->csc_mv));
1480 memcpy(csc_matrix[vp_num].csc_pre_bv, p->csc_pre_bv,
1481 sizeof(p->csc_pre_bv));
1482 memcpy(csc_matrix[vp_num].csc_post_bv, p->csc_post_bv,
1483 sizeof(p->csc_post_bv));
1484 memcpy(csc_matrix[vp_num].csc_pre_lv, p->csc_pre_lv,
1485 sizeof(p->csc_pre_lv));
1486 memcpy(csc_matrix[vp_num].csc_post_lv, p->csc_post_lv,
1487 sizeof(p->csc_post_lv));
1488 mdp4_vg_csc_setup(vp_num);
1489 }
1490}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1491static uint32 csc_rgb2yuv_matrix_tab[9] = {
1492 0x0083, 0x0102, 0x0032,
1493 0x1fb5, 0x1f6c, 0x00e1,
1494 0x00e1, 0x1f45, 0x1fdc
1495};
1496
1497static uint32 csc_rgb2yuv_pre_bv_tab[3] = {0, 0, 0};
1498
1499static uint32 csc_rgb2yuv_post_bv_tab[3] = {0x0010, 0x0080, 0x0080};
1500
1501static uint32 csc_rgb2yuv_pre_lv_tab[6] = {
1502 0x00, 0xff, 0x00,
1503 0xff, 0x00, 0xff
1504};
1505
1506static uint32 csc_rgb2yuv_post_lv_tab[6] = {
1507 0x0010, 0x00eb, 0x0010,
1508 0x00f0, 0x0010, 0x00f0
1509};
1510
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1511void mdp4_mixer_csc_mv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1512{
1513 uint32 *off;
1514 int i;
1515
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1516 if (mixer == MDP4_MIXER1)
1517 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2400);
1518 else
1519 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2400);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1520
1521 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1522 for (i = 0; i < 9; i++) {
1523 outpdw(off, csc_rgb2yuv_matrix_tab[i]);
1524 off++;
1525 }
1526 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1527}
1528
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1529void mdp4_mixer_csc_pre_bv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1530{
1531 uint32 *off;
1532 int i;
1533
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1534 if (mixer == MDP4_MIXER1)
1535 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2500);
1536 else
1537 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2500);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1538
1539 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1540 for (i = 0; i < 3; i++) {
1541 outpdw(off, csc_rgb2yuv_pre_bv_tab[i]);
1542 off++;
1543 }
1544 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1545}
1546
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1547void mdp4_mixer_csc_post_bv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1548{
1549 uint32 *off;
1550 int i;
1551
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1552 if (mixer == MDP4_MIXER1)
1553 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2580);
1554 else
1555 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2580);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1556
1557 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1558 for (i = 0; i < 3; i++) {
1559 outpdw(off, csc_rgb2yuv_post_bv_tab[i]);
1560 off++;
1561 }
1562 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1563}
1564
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1565void mdp4_mixer_csc_pre_lv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1566{
1567 uint32 *off;
1568 int i;
1569
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1570 if (mixer == MDP4_MIXER1)
1571 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2600);
1572 else
1573 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2600);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1574
1575 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1576 for (i = 0; i < 6; i++) {
1577 outpdw(off, csc_rgb2yuv_pre_lv_tab[i]);
1578 off++;
1579 }
1580 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1581}
1582
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1583void mdp4_mixer_csc_post_lv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1584{
1585 uint32 *off;
1586 int i;
1587
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1588 if (mixer == MDP4_MIXER1)
1589 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2680);
1590 else
1591 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2680);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1592
1593 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1594 for (i = 0; i < 6; i++) {
1595 outpdw(off, csc_rgb2yuv_post_lv_tab[i]);
1596 off++;
1597 }
1598 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1599}
1600
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1601void mdp4_mixer_csc_setup(uint32 mixer)
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1602{
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1603 if (mixer >= MDP4_MIXER1) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1604 /* rgb2yuv */
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1605 mdp4_mixer_csc_mv_setup(mixer);
1606 mdp4_mixer_csc_pre_bv_setup(mixer);
1607 mdp4_mixer_csc_post_bv_setup(mixer);
1608 mdp4_mixer_csc_pre_lv_setup(mixer);
1609 mdp4_mixer_csc_post_lv_setup(mixer);
1610 }
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1611}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1612
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1613#define DMA_P_BASE 0x90000
1614void mdp4_dmap_csc_mv_setup(void)
1615{
1616 uint32 *off;
1617 int i;
1618
1619 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3400);
1620
1621 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1622 for (i = 0; i < 9; i++) {
1623 outpdw(off, csc_matrix[2].csc_mv[i]);
1624 off++;
1625 }
1626 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1627}
1628
1629void mdp4_dmap_csc_pre_bv_setup(void)
1630{
1631 uint32 *off;
1632 int i;
1633
1634 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3500);
1635
1636 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1637 for (i = 0; i < 3; i++) {
1638 outpdw(off, csc_matrix[2].csc_pre_bv[i]);
1639 off++;
1640 }
1641 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1642}
1643
1644void mdp4_dmap_csc_post_bv_setup(void)
1645{
1646 uint32 *off;
1647 int i;
1648
1649 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3580);
1650
1651 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1652 for (i = 0; i < 3; i++) {
1653 outpdw(off, csc_matrix[2].csc_post_bv[i]);
1654 off++;
1655 }
1656 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1657}
1658
1659void mdp4_dmap_csc_pre_lv_setup(void)
1660{
1661 uint32 *off;
1662 int i;
1663
1664 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3600);
1665
1666 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1667 for (i = 0; i < 6; i++) {
1668 outpdw(off, csc_matrix[2].csc_pre_lv[i]);
1669 off++;
1670 }
1671 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1672}
1673
1674void mdp4_dmap_csc_post_lv_setup(void)
1675{
1676 uint32 *off;
1677 int i;
1678
1679 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3680);
1680
1681 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1682 for (i = 0; i < 6; i++) {
1683 outpdw(off, csc_matrix[2].csc_post_lv[i]);
1684 off++;
1685 }
1686 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1687}
1688
1689void mdp4_dmap_csc_setup(void)
1690{
1691 mdp4_dmap_csc_mv_setup();
1692 mdp4_dmap_csc_pre_bv_setup();
1693 mdp4_dmap_csc_post_bv_setup();
1694 mdp4_dmap_csc_pre_lv_setup();
1695 mdp4_dmap_csc_post_lv_setup();
1696}
1697
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1698char gc_lut[] = {
1699 0x0, 0x1, 0x2, 0x2, 0x3, 0x4, 0x5, 0x6,
1700 0x6, 0x7, 0x8, 0x9, 0xA, 0xA, 0xB, 0xC,
1701 0xD, 0xD, 0xE, 0xF, 0xF, 0x10, 0x10, 0x11,
1702 0x12, 0x12, 0x13, 0x13, 0x14, 0x14, 0x15, 0x15,
1703 0x16, 0x16, 0x17, 0x17, 0x17, 0x18, 0x18, 0x19,
1704 0x19, 0x19, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1C,
1705 0x1C, 0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F,
1706 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21,
1707 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24,
1708 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x26, 0x26,
1709 0x26, 0x26, 0x27, 0x27, 0x27, 0x28, 0x28, 0x28,
1710 0x28, 0x29, 0x29, 0x29, 0x29, 0x2A, 0x2A, 0x2A,
1711 0x2A, 0x2B, 0x2B, 0x2B, 0x2B, 0x2B, 0x2C, 0x2C,
1712 0x2C, 0x2C, 0x2D, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E,
1713 0x2E, 0x2E, 0x2E, 0x2F, 0x2F, 0x2F, 0x2F, 0x30,
1714 0x30, 0x30, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31,
1715 0x31, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33,
1716 0x33, 0x33, 0x33, 0x34, 0x34, 0x34, 0x34, 0x34,
1717 0x35, 0x35, 0x35, 0x35, 0x35, 0x36, 0x36, 0x36,
1718 0x36, 0x36, 0x37, 0x37, 0x37, 0x37, 0x37, 0x37,
1719 0x38, 0x38, 0x38, 0x38, 0x38, 0x39, 0x39, 0x39,
1720 0x39, 0x39, 0x39, 0x3A, 0x3A, 0x3A, 0x3A, 0x3A,
1721 0x3A, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3C,
1722 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D,
1723 0x3D, 0x3D, 0x3D, 0x3E, 0x3E, 0x3E, 0x3E, 0x3E,
1724 0x3E, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x40,
1725 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41,
1726 0x41, 0x41, 0x41, 0x41, 0x42, 0x42, 0x42, 0x42,
1727 0x42, 0x42, 0x42, 0x43, 0x43, 0x43, 0x43, 0x43,
1728 0x43, 0x43, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
1729 0x44, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45,
1730 0x46, 0x46, 0x46, 0x46, 0x46, 0x46, 0x46, 0x47,
1731 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x48, 0x48,
1732 0x48, 0x48, 0x48, 0x48, 0x48, 0x48, 0x49, 0x49,
1733 0x49, 0x49, 0x49, 0x49, 0x49, 0x4A, 0x4A, 0x4A,
1734 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4B, 0x4B, 0x4B,
1735 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4C, 0x4C, 0x4C,
1736 0x4C, 0x4C, 0x4C, 0x4C, 0x4D, 0x4D, 0x4D, 0x4D,
1737 0x4D, 0x4D, 0x4D, 0x4D, 0x4E, 0x4E, 0x4E, 0x4E,
1738 0x4E, 0x4E, 0x4E, 0x4E, 0x4E, 0x4F, 0x4F, 0x4F,
1739 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x50, 0x50, 0x50,
1740 0x50, 0x50, 0x50, 0x50, 0x50, 0x51, 0x51, 0x51,
1741 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52,
1742 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x53, 0x53,
1743 0x53, 0x53, 0x53, 0x53, 0x53, 0x53, 0x53, 0x54,
1744 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54,
1745 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
1746 0x55, 0x56, 0x56, 0x56, 0x56, 0x56, 0x56, 0x56,
1747 0x56, 0x56, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57,
1748 0x57, 0x57, 0x57, 0x58, 0x58, 0x58, 0x58, 0x58,
1749 0x58, 0x58, 0x58, 0x58, 0x58, 0x59, 0x59, 0x59,
1750 0x59, 0x59, 0x59, 0x59, 0x59, 0x59, 0x5A, 0x5A,
1751 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,
1752 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B,
1753 0x5B, 0x5B, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C,
1754 0x5C, 0x5C, 0x5C, 0x5C, 0x5D, 0x5D, 0x5D, 0x5D,
1755 0x5D, 0x5D, 0x5D, 0x5D, 0x5D, 0x5D, 0x5E, 0x5E,
1756 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E,
1757 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F,
1758 0x5F, 0x5F, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60,
1759 0x60, 0x60, 0x60, 0x60, 0x60, 0x61, 0x61, 0x61,
1760 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x62,
1761 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62,
1762 0x62, 0x62, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
1763 0x63, 0x63, 0x63, 0x63, 0x63, 0x64, 0x64, 0x64,
1764 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64,
1765 0x65, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65,
1766 0x65, 0x65, 0x65, 0x66, 0x66, 0x66, 0x66, 0x66,
1767 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x67, 0x67,
1768 0x67, 0x67, 0x67, 0x67, 0x67, 0x67, 0x67, 0x67,
1769 0x67, 0x67, 0x68, 0x68, 0x68, 0x68, 0x68, 0x68,
1770 0x68, 0x68, 0x68, 0x68, 0x68, 0x69, 0x69, 0x69,
1771 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69,
1772 0x69, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A,
1773 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6B, 0x6B, 0x6B,
1774 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B,
1775 0x6B, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C,
1776 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6D, 0x6D, 0x6D,
1777 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D,
1778 0x6D, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E,
1779 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6F, 0x6F, 0x6F,
1780 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F,
1781 0x6F, 0x6F, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
1782 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x71, 0x71,
1783 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
1784 0x71, 0x71, 0x71, 0x72, 0x72, 0x72, 0x72, 0x72,
1785 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72,
1786 0x73, 0x73, 0x73, 0x73, 0x73, 0x73, 0x73, 0x73,
1787 0x73, 0x73, 0x73, 0x73, 0x73, 0x74, 0x74, 0x74,
1788 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74,
1789 0x74, 0x74, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
1790 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
1791 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76,
1792 0x76, 0x76, 0x76, 0x76, 0x76, 0x77, 0x77, 0x77,
1793 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,
1794 0x77, 0x77, 0x77, 0x78, 0x78, 0x78, 0x78, 0x78,
1795 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
1796 0x78, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79,
1797 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x7A, 0x7A,
1798 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A,
1799 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7B, 0x7B, 0x7B,
1800 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B,
1801 0x7B, 0x7B, 0x7B, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C,
1802 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C,
1803 0x7C, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D,
1804 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D,
1805 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E,
1806 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7F, 0x7F,
1807 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F,
1808 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x80, 0x80, 0x80,
1809 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
1810 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81,
1811 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
1812 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x82, 0x82,
1813 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82,
1814 0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83,
1815 0x83, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83,
1816 0x83, 0x83, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84,
1817 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84,
1818 0x84, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
1819 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
1820 0x85, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86,
1821 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86,
1822 0x86, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87,
1823 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87,
1824 0x87, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1825 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1826 0x88, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89,
1827 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89,
1828 0x89, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
1829 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
1830 0x8A, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B,
1831 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B,
1832 0x8B, 0x8B, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C,
1833 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C,
1834 0x8C, 0x8C, 0x8C, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D,
1835 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D,
1836 0x8D, 0x8D, 0x8D, 0x8D, 0x8E, 0x8E, 0x8E, 0x8E,
1837 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E,
1838 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8F, 0x8F, 0x8F,
1839 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F,
1840 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x90, 0x90,
1841 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90,
1842 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x91,
1843 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91,
1844 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91,
1845 0x91, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92,
1846 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92,
1847 0x92, 0x92, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93,
1848 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93,
1849 0x93, 0x93, 0x93, 0x93, 0x94, 0x94, 0x94, 0x94,
1850 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94,
1851 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x95, 0x95,
1852 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
1853 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
1854 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96,
1855 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96,
1856 0x96, 0x96, 0x96, 0x97, 0x97, 0x97, 0x97, 0x97,
1857 0x97, 0x97, 0x97, 0x97, 0x97, 0x97, 0x97, 0x97,
1858 0x97, 0x97, 0x97, 0x97, 0x97, 0x98, 0x98, 0x98,
1859 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
1860 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
1861 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99,
1862 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99,
1863 0x99, 0x99, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A,
1864 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A,
1865 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9B, 0x9B, 0x9B,
1866 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B,
1867 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B,
1868 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C,
1869 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C,
1870 0x9C, 0x9C, 0x9C, 0x9C, 0x9D, 0x9D, 0x9D, 0x9D,
1871 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
1872 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9E,
1873 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E,
1874 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E,
1875 0x9E, 0x9E, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1876 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1877 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0xA0, 0xA0,
1878 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1879 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1880 0xA0, 0xA0, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1881 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1882 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA2, 0xA2,
1883 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1884 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1885 0xA2, 0xA2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1886 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1887 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA4, 0xA4,
1888 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1889 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1890 0xA4, 0xA4, 0xA4, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1891 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1892 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1893 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1894 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1895 0xA6, 0xA6, 0xA6, 0xA6, 0xA7, 0xA7, 0xA7, 0xA7,
1896 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1897 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1898 0xA7, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1899 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1900 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA9,
1901 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
1902 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
1903 0xA9, 0xA9, 0xA9, 0xA9, 0xAA, 0xAA, 0xAA, 0xAA,
1904 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1905 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1906 0xAA, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB,
1907 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB,
1908 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAC,
1909 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC,
1910 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC,
1911 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAD, 0xAD, 0xAD,
1912 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD,
1913 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD,
1914 0xAD, 0xAD, 0xAD, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1915 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1916 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1917 0xAE, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF,
1918 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF,
1919 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xB0,
1920 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1921 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1922 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB1, 0xB1,
1923 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1924 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1925 0xB1, 0xB1, 0xB1, 0xB1, 0xB2, 0xB2, 0xB2, 0xB2,
1926 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1927 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1928 0xB2, 0xB2, 0xB2, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1929 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1930 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1931 0xB3, 0xB3, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1932 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1933 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1934 0xB4, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1935 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1936 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1937 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1938 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1939 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1940 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1941 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1942 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB8,
1943 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1944 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1945 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB9,
1946 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1947 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1948 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xBA,
1949 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1950 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1951 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBB,
1952 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1953 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1954 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1955 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1956 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1957 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1958 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1959 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1960 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1961 0xBD, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1962 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1963 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1964 0xBE, 0xBE, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1965 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1966 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1967 0xBF, 0xBF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1968 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1969 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1970 0xC0, 0xC0, 0xC0, 0xC0, 0xC1, 0xC1, 0xC1, 0xC1,
1971 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1972 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1973 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC2, 0xC2, 0xC2,
1974 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1975 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1976 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC3, 0xC3,
1977 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1978 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1979 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1980 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1981 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1982 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1983 0xC4, 0xC4, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1984 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1985 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1986 0xC5, 0xC5, 0xC5, 0xC5, 0xC6, 0xC6, 0xC6, 0xC6,
1987 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
1988 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
1989 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC7, 0xC7,
1990 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
1991 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
1992 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
1993 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
1994 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
1995 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
1996 0xC8, 0xC8, 0xC8, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
1997 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
1998 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
1999 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xCA, 0xCA,
2000 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2001 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2002 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2003 0xCA, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2004 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2005 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2006 0xCB, 0xCB, 0xCB, 0xCB, 0xCC, 0xCC, 0xCC, 0xCC,
2007 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
2008 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
2009 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCD,
2010 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2011 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2012 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2013 0xCD, 0xCD, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2014 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2015 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2016 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCF, 0xCF,
2017 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2018 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2019 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2020 0xCF, 0xCF, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2021 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2022 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2023 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD1, 0xD1, 0xD1,
2024 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2025 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2026 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2027 0xD1, 0xD1, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2028 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2029 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2030 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD3, 0xD3,
2031 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2032 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2033 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2034 0xD3, 0xD3, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2035 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2036 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2037 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD5,
2038 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2039 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2040 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2041 0xD5, 0xD5, 0xD5, 0xD5, 0xD6, 0xD6, 0xD6, 0xD6,
2042 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2043 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2044 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2045 0xD6, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2046 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2047 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2048 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD8, 0xD8,
2049 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2050 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2051 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2052 0xD8, 0xD8, 0xD8, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2053 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2054 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2055 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2056 0xD9, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2057 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2058 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2059 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDB, 0xDB,
2060 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2061 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2062 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2063 0xDB, 0xDB, 0xDB, 0xDB, 0xDC, 0xDC, 0xDC, 0xDC,
2064 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2065 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2066 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2067 0xDC, 0xDC, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2068 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2069 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2070 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2071 0xDD, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2072 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2073 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2074 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDF,
2075 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2076 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2077 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2078 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xE0, 0xE0,
2079 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2080 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2081 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2082 0xE0, 0xE0, 0xE0, 0xE0, 0xE1, 0xE1, 0xE1, 0xE1,
2083 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2084 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2085 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2086 0xE1, 0xE1, 0xE1, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2087 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2088 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2089 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2090 0xE2, 0xE2, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2091 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2092 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2093 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2094 0xE3, 0xE3, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2095 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2096 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2097 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2098 0xE4, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2099 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2100 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2101 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2102 0xE5, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2103 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2104 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2105 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2106 0xE6, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2107 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2108 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2109 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2110 0xE7, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2111 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2112 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2113 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2114 0xE8, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2115 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2116 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2117 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2118 0xE9, 0xE9, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2119 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2120 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2121 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2122 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2123 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2124 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2125 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2126 0xEB, 0xEB, 0xEB, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2127 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2128 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2129 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2130 0xEC, 0xEC, 0xEC, 0xEC, 0xED, 0xED, 0xED, 0xED,
2131 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2132 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2133 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2134 0xED, 0xED, 0xED, 0xED, 0xED, 0xEE, 0xEE, 0xEE,
2135 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2136 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2137 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2138 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEF, 0xEF,
2139 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2140 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2141 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2142 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2143 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2144 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2145 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2146 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2147 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2148 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2149 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2150 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2151 0xF1, 0xF1, 0xF1, 0xF1, 0xF2, 0xF2, 0xF2, 0xF2,
2152 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2153 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2154 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2155 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF3, 0xF3,
2156 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2157 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2158 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2159 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2160 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2161 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2162 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2163 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2164 0xF4, 0xF4, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2165 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2166 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2167 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2168 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF6, 0xF6, 0xF6,
2169 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2170 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2171 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2172 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2173 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2174 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2175 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2176 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2177 0xF7, 0xF7, 0xF7, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2178 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2179 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2180 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2181 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF9, 0xF9,
2182 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2183 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2184 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2185 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2186 0xF9, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2187 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2188 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2189 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2190 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB,
2191 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2192 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2193 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2194 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2195 0xFB, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2196 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2197 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2198 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2199 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFD, 0xFD, 0xFD,
2200 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2201 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2202 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2203 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2204 0xFD, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2205 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2206 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2207 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2208 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF,
2209 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2210 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2211};
2212
2213void mdp4_mixer_gc_lut_setup(int mixer_num)
2214{
2215 unsigned char *base;
2216 uint32 data;
2217 char val;
2218 int i, off;
2219
2220 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
2221 base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
2222 else
2223 base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
2224
2225 base += 0x4000; /* GC_LUT offset */
2226
2227 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2228 off = 0;
2229 for (i = 0; i < 4096; i++) {
2230 val = gc_lut[i];
2231 data = (val << 16 | val << 8 | val); /* R, B, and G are same */
2232 outpdw(base + off, data);
2233 off += 4;
2234 }
2235 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2236}
2237
2238uint32 igc_video_lut[] = { /* non linear */
2239 0x0, 0x1, 0x2, 0x4, 0x5, 0x6, 0x7, 0x9,
2240 0xA, 0xB, 0xC, 0xE, 0xF, 0x10, 0x12, 0x14,
2241 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F, 0x21, 0x23,
2242 0x25, 0x28, 0x2A, 0x2D, 0x30, 0x32, 0x35, 0x38,
2243 0x3B, 0x3E, 0x42, 0x45, 0x48, 0x4C, 0x4F, 0x53,
2244 0x57, 0x5B, 0x5F, 0x63, 0x67, 0x6B, 0x70, 0x74,
2245 0x79, 0x7E, 0x83, 0x88, 0x8D, 0x92, 0x97, 0x9C,
2246 0xA2, 0xA8, 0xAD, 0xB3, 0xB9, 0xBF, 0xC5, 0xCC,
2247 0xD2, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, 0xFB, 0x102,
2248 0x109, 0x111, 0x118, 0x120, 0x128, 0x130, 0x138, 0x140,
2249 0x149, 0x151, 0x15A, 0x162, 0x16B, 0x174, 0x17D, 0x186,
2250 0x190, 0x199, 0x1A3, 0x1AC, 0x1B6, 0x1C0, 0x1CA, 0x1D5,
2251 0x1DF, 0x1EA, 0x1F4, 0x1FF, 0x20A, 0x215, 0x220, 0x22B,
2252 0x237, 0x242, 0x24E, 0x25A, 0x266, 0x272, 0x27F, 0x28B,
2253 0x298, 0x2A4, 0x2B1, 0x2BE, 0x2CB, 0x2D8, 0x2E6, 0x2F3,
2254 0x301, 0x30F, 0x31D, 0x32B, 0x339, 0x348, 0x356, 0x365,
2255 0x374, 0x383, 0x392, 0x3A1, 0x3B1, 0x3C0, 0x3D0, 0x3E0,
2256 0x3F0, 0x400, 0x411, 0x421, 0x432, 0x443, 0x454, 0x465,
2257 0x476, 0x487, 0x499, 0x4AB, 0x4BD, 0x4CF, 0x4E1, 0x4F3,
2258 0x506, 0x518, 0x52B, 0x53E, 0x551, 0x565, 0x578, 0x58C,
2259 0x5A0, 0x5B3, 0x5C8, 0x5DC, 0x5F0, 0x605, 0x61A, 0x62E,
2260 0x643, 0x659, 0x66E, 0x684, 0x699, 0x6AF, 0x6C5, 0x6DB,
2261 0x6F2, 0x708, 0x71F, 0x736, 0x74D, 0x764, 0x77C, 0x793,
2262 0x7AB, 0x7C3, 0x7DB, 0x7F3, 0x80B, 0x824, 0x83D, 0x855,
2263 0x86F, 0x888, 0x8A1, 0x8BB, 0x8D4, 0x8EE, 0x908, 0x923,
2264 0x93D, 0x958, 0x973, 0x98E, 0x9A9, 0x9C4, 0x9DF, 0x9FB,
2265 0xA17, 0xA33, 0xA4F, 0xA6C, 0xA88, 0xAA5, 0xAC2, 0xADF,
2266 0xAFC, 0xB19, 0xB37, 0xB55, 0xB73, 0xB91, 0xBAF, 0xBCE,
2267 0xBEC, 0xC0B, 0xC2A, 0xC4A, 0xC69, 0xC89, 0xCA8, 0xCC8,
2268 0xCE8, 0xD09, 0xD29, 0xD4A, 0xD6B, 0xD8C, 0xDAD, 0xDCF,
2269 0xDF0, 0xE12, 0xE34, 0xE56, 0xE79, 0xE9B, 0xEBE, 0xEE1,
2270 0xF04, 0xF27, 0xF4B, 0xF6E, 0xF92, 0xFB6, 0xFDB, 0xFFF,
2271};
2272
2273void mdp4_vg_igc_lut_setup(int vp_num)
2274{
2275 unsigned char *base;
2276 int i, voff, off;
2277 uint32 data, val;
2278
2279 voff = MDP4_VIDEO_OFF * vp_num;
2280 base = MDP_BASE + MDP4_VIDEO_BASE + voff + 0x5000;
2281
2282 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2283 off = 0;
2284 for (i = 0; i < 256; i++) {
2285 val = igc_video_lut[i];
2286 data = (val << 16 | val); /* color 0 and 1 */
2287 outpdw(base + off, data);
2288 outpdw(base + off + 0x800, val); /* color 2 */
2289 off += 4;
2290 }
2291 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2292}
2293
2294uint32 igc_rgb_lut[] = { /* linear */
2295 0x0, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
2296 0x80, 0x91, 0xA1, 0xB1, 0xC1, 0xD1, 0xE1, 0xF1,
2297 0x101, 0x111, 0x121, 0x131, 0x141, 0x151, 0x161, 0x171,
2298 0x181, 0x191, 0x1A2, 0x1B2, 0x1C2, 0x1D2, 0x1E2, 0x1F2,
2299 0x202, 0x212, 0x222, 0x232, 0x242, 0x252, 0x262, 0x272,
2300 0x282, 0x292, 0x2A2, 0x2B3, 0x2C3, 0x2D3, 0x2E3, 0x2F3,
2301 0x303, 0x313, 0x323, 0x333, 0x343, 0x353, 0x363, 0x373,
2302 0x383, 0x393, 0x3A3, 0x3B3, 0x3C4, 0x3D4, 0x3E4, 0x3F4,
2303 0x404, 0x414, 0x424, 0x434, 0x444, 0x454, 0x464, 0x474,
2304 0x484, 0x494, 0x4A4, 0x4B4, 0x4C4, 0x4D5, 0x4E5, 0x4F5,
2305 0x505, 0x515, 0x525, 0x535, 0x545, 0x555, 0x565, 0x575,
2306 0x585, 0x595, 0x5A5, 0x5B5, 0x5C5, 0x5D5, 0x5E6, 0x5F6,
2307 0x606, 0x616, 0x626, 0x636, 0x646, 0x656, 0x666, 0x676,
2308 0x686, 0x696, 0x6A6, 0x6B6, 0x6C6, 0x6D6, 0x6E6, 0x6F7,
2309 0x707, 0x717, 0x727, 0x737, 0x747, 0x757, 0x767, 0x777,
2310 0x787, 0x797, 0x7A7, 0x7B7, 0x7C7, 0x7D7, 0x7E7, 0x7F7,
2311 0x808, 0x818, 0x828, 0x838, 0x848, 0x858, 0x868, 0x878,
2312 0x888, 0x898, 0x8A8, 0x8B8, 0x8C8, 0x8D8, 0x8E8, 0x8F8,
2313 0x908, 0x919, 0x929, 0x939, 0x949, 0x959, 0x969, 0x979,
2314 0x989, 0x999, 0x9A9, 0x9B9, 0x9C9, 0x9D9, 0x9E9, 0x9F9,
2315 0xA09, 0xA19, 0xA2A, 0xA3A, 0xA4A, 0xA5A, 0xA6A, 0xA7A,
2316 0xA8A, 0xA9A, 0xAAA, 0xABA, 0xACA, 0xADA, 0xAEA, 0xAFA,
2317 0xB0A, 0xB1A, 0xB2A, 0xB3B, 0xB4B, 0xB5B, 0xB6B, 0xB7B,
2318 0xB8B, 0xB9B, 0xBAB, 0xBBB, 0xBCB, 0xBDB, 0xBEB, 0xBFB,
2319 0xC0B, 0xC1B, 0xC2B, 0xC3B, 0xC4C, 0xC5C, 0xC6C, 0xC7C,
2320 0xC8C, 0xC9C, 0xCAC, 0xCBC, 0xCCC, 0xCDC, 0xCEC, 0xCFC,
2321 0xD0C, 0xD1C, 0xD2C, 0xD3C, 0xD4C, 0xD5D, 0xD6D, 0xD7D,
2322 0xD8D, 0xD9D, 0xDAD, 0xDBD, 0xDCD, 0xDDD, 0xDED, 0xDFD,
2323 0xE0D, 0xE1D, 0xE2D, 0xE3D, 0xE4D, 0xE5D, 0xE6E, 0xE7E,
2324 0xE8E, 0xE9E, 0xEAE, 0xEBE, 0xECE, 0xEDE, 0xEEE, 0xEFE,
2325 0xF0E, 0xF1E, 0xF2E, 0xF3E, 0xF4E, 0xF5E, 0xF6E, 0xF7F,
2326 0xF8F, 0xF9F, 0xFAF, 0xFBF, 0xFCF, 0xFDF, 0xFEF, 0xFFF,
2327};
2328
2329void mdp4_rgb_igc_lut_setup(int num)
2330{
2331 unsigned char *base;
2332 int i, voff, off;
2333 uint32 data, val;
2334
2335 voff = MDP4_RGB_OFF * num;
2336 base = MDP_BASE + MDP4_RGB_BASE + voff + 0x5000;
2337
2338 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2339 off = 0;
2340 for (i = 0; i < 256; i++) {
2341 val = igc_rgb_lut[i];
2342 data = (val << 16 | val); /* color 0 and 1 */
2343 outpdw(base + off, data);
2344 outpdw(base + off + 0x800, val); /* color 2 */
2345 off += 4;
2346 }
2347 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2348}
2349
2350uint32 mdp4_rgb_igc_lut_cvt(uint32 ndx)
2351{
2352 return igc_rgb_lut[ndx & 0x0ff];
2353}
2354
2355uint32_t mdp4_ss_table_value(int8_t value, int8_t index)
2356{
2357 uint32_t out = 0x0;
2358 int8_t level = -1;
2359 uint32_t mask = 0xffffffff;
2360
2361 if (value < 0) {
2362 if (value == -128)
2363 value = 127;
2364 else
2365 value = -value;
2366 out = 0x11111111;
2367 } else {
2368 out = 0x88888888;
2369 mask = 0x0fffffff;
2370 }
2371
2372 if (value == 0)
2373 level = 0;
2374 else {
2375 while (value > 0 && level < 7) {
2376 level++;
2377 value -= 16;
2378 }
2379 }
2380
2381 if (level == 0) {
2382 if (index == 0)
2383 out = 0x0;
2384 else
2385 out = 0x20000000;
2386 } else {
2387 out += (0x11111111 * level);
2388 if (index == 1)
2389 out &= mask;
2390 }
2391
2392 return out;
2393}
2394
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2395static uint32_t mdp4_csc_block2base(uint32_t block)
2396{
2397 uint32_t base = 0x0;
2398 switch (block) {
2399 case MDP_BLOCK_OVERLAY_1:
2400 base = 0x1A000;
2401 break;
2402 case MDP_BLOCK_VG_1:
2403 base = 0x24000;
2404 break;
2405 case MDP_BLOCK_VG_2:
2406 base = 0x34000;
2407 break;
2408 case MDP_BLOCK_DMA_P:
2409 base = 0x93000;
2410 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2411 case MDP_BLOCK_DMA_S:
2412 base = (mdp_rev >= MDP_REV_42) ? 0xA3000 : 0x0;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2413 default:
2414 break;
2415 }
2416 return base;
2417}
2418
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2419int mdp4_csc_enable(struct mdp_csc_cfg_data *config)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2420{
2421 uint32_t output, base, temp, mask;
2422
2423 switch (config->block) {
2424 case MDP_BLOCK_DMA_P:
2425 base = 0x90070;
2426 output = (config->csc_data.flags << 3) & (0x08);
2427 temp = (config->csc_data.flags << 10) & (0x1800);
2428 output |= temp;
2429 mask = 0x08 | 0x1800;
2430 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2431 case MDP_BLOCK_DMA_S:
2432 base = 0xA0028;
2433 output = (config->csc_data.flags << 3) & (0x08);
2434 temp = (config->csc_data.flags << 10) & (0x1800);
2435 output |= temp;
2436 mask = 0x08 | 0x1800;
2437 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2438 case MDP_BLOCK_VG_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2439 base = 0x20058;
2440 output = (config->csc_data.flags << 11) & (0x800);
2441 temp = (config->csc_data.flags << 8) & (0x600);
2442 output |= temp;
2443 mask = 0x800 | 0x600;
2444 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2445 case MDP_BLOCK_VG_2:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2446 base = 0x30058;
2447 output = (config->csc_data.flags << 11) & (0x800);
2448 temp = (config->csc_data.flags << 8) & (0x600);
2449 output |= temp;
2450 mask = 0x800 | 0x600;
2451 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2452 case MDP_BLOCK_OVERLAY_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2453 base = 0x18200;
2454 output = config->csc_data.flags;
2455 mask = 0x07;
2456 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2457 default:
2458 pr_err("%s - CSC block does not exist on MDP_BLOCK = %d\n",
2459 __func__, config->block);
2460 return -EINVAL;
2461 }
2462
2463 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2464 temp = inpdw(MDP_BASE + base) & ~mask;
2465 output |= temp;
2466 outpdw(MDP_BASE + base, output);
2467 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2468 return 0;
2469}
2470
2471#define CSC_MV_OFF 0x400
2472#define CSC_BV_OFF 0x500
2473#define CSC_LV_OFF 0x600
2474#define CSC_POST_OFF 0x80
2475
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2476void mdp4_csc_write(struct mdp_csc_cfg *data, uint32_t base)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2477{
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2478 int i;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2479 uint32_t *off;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2480
2481 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2482 off = (uint32_t *) ((uint32_t) base + CSC_MV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2483 for (i = 0; i < 9; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2484 outpdw(off, data->csc_mv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2485 off++;
2486 }
2487
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2488 off = (uint32_t *) ((uint32_t) base + CSC_BV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2489 for (i = 0; i < 3; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2490 outpdw(off, data->csc_pre_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2491 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2492 data->csc_post_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2493 off++;
2494 }
2495
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2496 off = (uint32_t *) ((uint32_t) base + CSC_LV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2497 for (i = 0; i < 6; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2498 outpdw(off, data->csc_pre_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2499 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2500 data->csc_post_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2501 off++;
2502 }
2503 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2504}
2505
2506int mdp4_csc_config(struct mdp_csc_cfg_data *config)
2507{
2508 int ret = 0;
2509 uint32_t base;
2510
2511 base = mdp4_csc_block2base(config->block);
2512 if (!base) {
2513 pr_warn("%s: Block type %d isn't supported by CSC.\n",
2514 __func__, config->block);
2515 return -EINVAL;
2516 }
2517
2518 mdp4_csc_write(&config->csc_data, (uint32_t) (MDP_BASE + base));
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2519
2520 ret = mdp4_csc_enable(config);
2521
2522 return ret;
2523}
2524
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2525void mdp4_init_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2526{
2527 struct mdp_buf_type *buf;
2528
2529 if (mix_num == MDP4_MIXER0)
2530 buf = mfd->ov0_wb_buf;
2531 else
2532 buf = mfd->ov1_wb_buf;
2533
2534 buf->ihdl = NULL;
2535 buf->phys_addr = 0;
2536}
2537
2538u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2539{
2540 struct mdp_buf_type *buf;
2541 ion_phys_addr_t addr;
2542 u32 len;
2543
2544 if (mix_num == MDP4_MIXER0)
2545 buf = mfd->ov0_wb_buf;
2546 else
2547 buf = mfd->ov1_wb_buf;
2548
2549 if (buf->phys_addr || !IS_ERR_OR_NULL(buf->ihdl))
2550 return 0;
2551
2552 if (!buf->size) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2553 pr_err("%s:%d In valid size\n", __func__, __LINE__);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2554 return -EINVAL;
2555 }
2556
2557 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2558 pr_info("%s:%d ion based allocation\n", __func__, __LINE__);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2559 buf->ihdl = ion_alloc(mfd->iclient, buf->size, 4,
2560 (1 << mfd->mem_hid));
2561 if (!IS_ERR_OR_NULL(buf->ihdl)) {
2562 if (ion_phys(mfd->iclient, buf->ihdl,
2563 &addr, &len)) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2564 pr_err("%s:%d: ion_phys map failed\n",
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2565 __func__, __LINE__);
2566 return -ENOMEM;
2567 }
2568 } else {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2569 pr_err("%s:%d: ion_alloc failed\n", __func__,
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2570 __LINE__);
2571 return -ENOMEM;
2572 }
2573 } else {
2574 addr = allocate_contiguous_memory_nomap(buf->size,
2575 mfd->mem_hid, 4);
2576 }
2577 if (addr) {
2578 pr_info("allocating %d bytes at %x for mdp writeback\n",
2579 buf->size, (u32) addr);
2580 buf->phys_addr = addr;
2581 return 0;
2582 } else {
2583 pr_err("%s cannot allocate memory for mdp writeback!\n",
2584 __func__);
2585 return -ENOMEM;
2586 }
2587}
2588
2589void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2590{
2591 struct mdp_buf_type *buf;
2592
2593 if (mix_num == MDP4_MIXER0)
2594 buf = mfd->ov0_wb_buf;
2595 else
2596 buf = mfd->ov1_wb_buf;
2597
2598 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2599 if (!IS_ERR_OR_NULL(buf->ihdl)) {
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2600 ion_free(mfd->iclient, buf->ihdl);
Jeff Ohlstein9cb0ead2011-12-16 13:30:08 -0800[diff] [blame]2601 pr_debug("%s:%d free writeback imem\n", __func__,
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2602 __LINE__);
2603 buf->ihdl = NULL;
2604 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2605 } else {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2606 if (buf->phys_addr) {
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2607 free_contiguous_memory_by_paddr(buf->phys_addr);
Jeff Ohlstein9cb0ead2011-12-16 13:30:08 -0800[diff] [blame]2608 pr_debug("%s:%d free writeback pmem\n", __func__,
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2609 __LINE__);
2610 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2611 }
2612 buf->phys_addr = 0;
2613}
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2614
2615static int mdp4_update_pcc_regs(uint32_t offset,
2616 struct mdp_pcc_cfg_data *cfg_ptr)
2617{
2618 int ret = -1;
2619
2620 if (offset && cfg_ptr) {
2621
2622 outpdw(offset, cfg_ptr->r.c);
2623 outpdw(offset + 0x30, cfg_ptr->g.c);
2624 outpdw(offset + 0x60, cfg_ptr->b.c);
2625 offset += 4;
2626
2627 outpdw(offset, cfg_ptr->r.r);
2628 outpdw(offset + 0x30, cfg_ptr->g.r);
2629 outpdw(offset + 0x60, cfg_ptr->b.r);
2630 offset += 4;
2631
2632 outpdw(offset, cfg_ptr->r.g);
2633 outpdw(offset + 0x30, cfg_ptr->g.g);
2634 outpdw(offset + 0x60, cfg_ptr->b.g);
2635 offset += 4;
2636
2637 outpdw(offset, cfg_ptr->r.b);
2638 outpdw(offset + 0x30, cfg_ptr->g.b);
2639 outpdw(offset + 0x60, cfg_ptr->b.b);
2640 offset += 4;
2641
2642 outpdw(offset, cfg_ptr->r.rr);
2643 outpdw(offset + 0x30, cfg_ptr->g.rr);
2644 outpdw(offset + 0x60, cfg_ptr->b.rr);
2645 offset += 4;
2646
2647 outpdw(offset, cfg_ptr->r.gg);
2648 outpdw(offset + 0x30, cfg_ptr->g.gg);
2649 outpdw(offset + 0x60, cfg_ptr->b.gg);
2650 offset += 4;
2651
2652 outpdw(offset, cfg_ptr->r.bb);
2653 outpdw(offset + 0x30, cfg_ptr->g.bb);
2654 outpdw(offset + 0x60, cfg_ptr->b.bb);
2655 offset += 4;
2656
2657 outpdw(offset, cfg_ptr->r.rg);
2658 outpdw(offset + 0x30, cfg_ptr->g.rg);
2659 outpdw(offset + 0x60, cfg_ptr->b.rg);
2660 offset += 4;
2661
2662 outpdw(offset, cfg_ptr->r.gb);
2663 outpdw(offset + 0x30, cfg_ptr->g.gb);
2664 outpdw(offset + 0x60, cfg_ptr->b.gb);
2665 offset += 4;
2666
2667 outpdw(offset, cfg_ptr->r.rb);
2668 outpdw(offset + 0x30, cfg_ptr->g.rb);
2669 outpdw(offset + 0x60, cfg_ptr->b.rb);
2670 offset += 4;
2671
2672 outpdw(offset, cfg_ptr->r.rgb_0);
2673 outpdw(offset + 0x30, cfg_ptr->g.rgb_0);
2674 outpdw(offset + 0x60, cfg_ptr->b.rgb_0);
2675 offset += 4;
2676
2677 outpdw(offset, cfg_ptr->r.rgb_1);
2678 outpdw(offset + 0x30, cfg_ptr->g.rgb_1);
2679 outpdw(offset + 0x60, cfg_ptr->b.rgb_1);
2680
2681 ret = 0;
2682 }
2683
2684 return ret;
2685}
2686
2687static int mdp4_read_pcc_regs(uint32_t offset,
2688 struct mdp_pcc_cfg_data *cfg_ptr)
2689{
2690 int ret = -1;
2691
2692 if (offset && cfg_ptr) {
2693 cfg_ptr->r.c = inpdw(offset);
2694 cfg_ptr->g.c = inpdw(offset + 0x30);
2695 cfg_ptr->b.c = inpdw(offset + 0x60);
2696 offset += 4;
2697
2698 cfg_ptr->r.r = inpdw(offset);
2699 cfg_ptr->g.r = inpdw(offset + 0x30);
2700 cfg_ptr->b.r = inpdw(offset + 0x60);
2701 offset += 4;
2702
2703 cfg_ptr->r.g = inpdw(offset);
2704 cfg_ptr->g.g = inpdw(offset + 0x30);
2705 cfg_ptr->b.g = inpdw(offset + 0x60);
2706 offset += 4;
2707
2708 cfg_ptr->r.b = inpdw(offset);
2709 cfg_ptr->g.b = inpdw(offset + 0x30);
2710 cfg_ptr->b.b = inpdw(offset + 0x60);
2711 offset += 4;
2712
2713 cfg_ptr->r.rr = inpdw(offset);
2714 cfg_ptr->g.rr = inpdw(offset + 0x30);
2715 cfg_ptr->b.rr = inpdw(offset + 0x60);
2716 offset += 4;
2717
2718 cfg_ptr->r.gg = inpdw(offset);
2719 cfg_ptr->g.gg = inpdw(offset + 0x30);
2720 cfg_ptr->b.gg = inpdw(offset + 0x60);
2721 offset += 4;
2722
2723 cfg_ptr->r.bb = inpdw(offset);
2724 cfg_ptr->g.bb = inpdw(offset + 0x30);
2725 cfg_ptr->b.bb = inpdw(offset + 0x60);
2726 offset += 4;
2727
2728 cfg_ptr->r.rg = inpdw(offset);
2729 cfg_ptr->g.rg = inpdw(offset + 0x30);
2730 cfg_ptr->b.rg = inpdw(offset + 0x60);
2731 offset += 4;
2732
2733 cfg_ptr->r.gb = inpdw(offset);
2734 cfg_ptr->g.gb = inpdw(offset + 0x30);
2735 cfg_ptr->b.gb = inpdw(offset + 0x60);
2736 offset += 4;
2737
2738 cfg_ptr->r.rb = inpdw(offset);
2739 cfg_ptr->g.rb = inpdw(offset + 0x30);
2740 cfg_ptr->b.rb = inpdw(offset + 0x60);
2741 offset += 4;
2742
2743 cfg_ptr->r.rgb_0 = inpdw(offset);
2744 cfg_ptr->g.rgb_0 = inpdw(offset + 0x30);
2745 cfg_ptr->b.rgb_0 = inpdw(offset + 0x60);
2746 offset += 4;
2747
2748 cfg_ptr->r.rgb_1 = inpdw(offset);
2749 cfg_ptr->g.rgb_1 = inpdw(offset + 0x30);
2750 cfg_ptr->b.rgb_1 = inpdw(offset + 0x60);
2751
2752 ret = 0;
2753 }
2754
2755 return ret;
2756}
2757
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2758
2759#define MDP_PCC_OFFSET 0xA000
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2760#define MDP_DMA_GC_OFFSET 0x8800
2761#define MDP_LM_0_GC_OFFSET 0x4800
2762#define MDP_LM_1_GC_OFFSET 0x4880
2763
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2764
2765#define MDP_DMA_P_OP_MODE_OFFSET 0x70
2766#define MDP_DMA_S_OP_MODE_OFFSET 0x28
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2767#define MDP_LM_OP_MODE_OFFSET 0x10
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2768
2769#define DMA_PCC_R2_OFFSET 0x100
2770
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2771#define MDP_GC_COLOR_OFFSET 0x100
2772#define MDP_GC_PARMS_OFFSET 0x80
2773
2774#define MDP_AR_GC_MAX_STAGES 16
2775
2776static uint32_t mdp_pp_block2pcc(uint32_t block)
2777{
2778 uint32_t valid = 0;
2779
2780 switch (block) {
2781 case MDP_BLOCK_DMA_P:
2782 case MDP_BLOCK_DMA_S:
2783 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2784 break;
2785
2786 default:
2787 break;
2788 }
2789
2790 return valid;
2791}
2792
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2793int mdp4_pcc_cfg(struct mdp_pcc_cfg_data *cfg_ptr)
2794{
2795 int ret = -1;
2796 uint32_t pcc_offset = 0, mdp_cfg_offset = 0;
2797 uint32_t mdp_dma_op_mode = 0;
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2798 uint32_t blockbase;
2799
2800 if (!mdp_pp_block2pcc(cfg_ptr->block))
2801 return ret;
2802
2803 blockbase = mdp_block2base(cfg_ptr->block);
2804 if (!blockbase)
2805 return ret;
2806
2807 blockbase += (uint32_t) MDP_BASE;
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2808
2809 switch (cfg_ptr->block) {
2810 case MDP_BLOCK_DMA_P:
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2811 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2812 pcc_offset = blockbase + MDP_PCC_OFFSET;
2813 mdp_cfg_offset = blockbase;
2814 mdp_dma_op_mode = blockbase +
2815 (MDP_BLOCK_DMA_P == cfg_ptr->block ?
2816 MDP_DMA_P_OP_MODE_OFFSET
2817 : MDP_DMA_S_OP_MODE_OFFSET);
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2818 break;
2819
2820 default:
2821 break;
2822 }
2823
2824 if (0x8 & cfg_ptr->ops)
2825 pcc_offset += DMA_PCC_R2_OFFSET;
2826
2827 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2828
2829 switch ((0x6 & cfg_ptr->ops)>>1) {
2830 case 0x1:
2831 ret = mdp4_read_pcc_regs(pcc_offset, cfg_ptr);
2832 break;
2833
2834 case 0x2:
2835 ret = mdp4_update_pcc_regs(pcc_offset, cfg_ptr);
2836 break;
2837
2838 default:
2839 break;
2840 }
2841
2842 if (0x8 & cfg_ptr->ops)
2843 outpdw(mdp_dma_op_mode,
2844 (inpdw(mdp_dma_op_mode)|((0x8&cfg_ptr->ops)<<10)));
2845
2846 outpdw(mdp_cfg_offset,
2847 (inpdw(mdp_cfg_offset)|((cfg_ptr->ops&0x1)<<29)));
2848
2849 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2850
2851 return ret;
2852}
2853
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2854static uint32_t mdp_pp_block2argc(uint32_t block)
2855{
2856 uint32_t valid = 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2857
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2858 switch (block) {
2859 case MDP_BLOCK_DMA_P:
2860 case MDP_BLOCK_DMA_S:
2861 case MDP_BLOCK_OVERLAY_0:
2862 case MDP_BLOCK_OVERLAY_1:
2863 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2864 break;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2865
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2866 default:
2867 break;
2868 }
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2869
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2870 return valid;
2871}
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2872
2873static int update_ar_gc_lut(uint32_t *offset, struct mdp_pgc_lut_data *lut_data)
2874{
2875 int ret = -1, count = 0;
2876
2877 uint32_t *c0_offset = offset;
2878 uint32_t *c0_params_offset = (uint32_t *)((uint32_t)c0_offset
2879 + MDP_GC_PARMS_OFFSET);
2880
2881 uint32_t *c1_offset = (uint32_t *)((uint32_t)offset
2882 + MDP_GC_COLOR_OFFSET);
2883
2884 uint32_t *c1_params_offset = (uint32_t *)((uint32_t)c1_offset
2885 + MDP_GC_PARMS_OFFSET);
2886
2887 uint32_t *c2_offset = (uint32_t *)((uint32_t)offset
2888 + 2*MDP_GC_COLOR_OFFSET);
2889
2890 uint32_t *c2_params_offset = (uint32_t *)((uint32_t)c2_offset
2891 +MDP_GC_PARMS_OFFSET);
2892
2893
2894 for (count = 0; count < MDP_AR_GC_MAX_STAGES; count++) {
2895 if (count < lut_data->num_r_stages) {
2896 outpdw(c0_offset+count,
2897 ((0xfff & lut_data->r_data[count].x_start)
2898 | 0x10000));
2899
2900 outpdw(c0_params_offset+count,
2901 ((0x7fff & lut_data->r_data[count].slope)
2902 | ((0xffff
2903 & lut_data->r_data[count].offset)
2904 << 16)));
2905 } else
2906 outpdw(c0_offset+count, 0);
2907
2908 if (count < lut_data->num_b_stages) {
2909 outpdw(c1_offset+count,
2910 ((0xfff & lut_data->b_data[count].x_start)
2911 | 0x10000));
2912
2913 outpdw(c1_params_offset+count,
2914 ((0x7fff & lut_data->b_data[count].slope)
2915 | ((0xffff
2916 & lut_data->b_data[count].offset)
2917 << 16)));
2918 } else
2919 outpdw(c1_offset+count, 0);
2920
2921 if (count < lut_data->num_g_stages) {
2922 outpdw(c2_offset+count,
2923 ((0xfff & lut_data->g_data[count].x_start)
2924 | 0x10000));
2925
2926 outpdw(c2_params_offset+count,
2927 ((0x7fff & lut_data->g_data[count].slope)
2928 | ((0xffff
2929 & lut_data->g_data[count].offset)
2930 << 16)));
2931 } else
2932 outpdw(c2_offset+count, 0);
2933 }
2934
2935 ret = 0;
2936
2937 return ret;
2938}
2939
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2940int mdp4_argc_cfg(struct mdp_pgc_lut_data *pgc_ptr)
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2941{
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2942 int ret = -1;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2943 uint32_t *offset = 0, *pgc_enable_offset = 0, lshift_bits = 0;
2944 struct mdp_ar_gc_lut_data r[MDP_AR_GC_MAX_STAGES];
2945 struct mdp_ar_gc_lut_data g[MDP_AR_GC_MAX_STAGES];
2946 struct mdp_ar_gc_lut_data b[MDP_AR_GC_MAX_STAGES];
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2947 uint32_t blockbase;
2948
2949 if (!mdp_pp_block2argc(pgc_ptr->block))
2950 return ret;
2951
2952 blockbase = mdp_block2base(pgc_ptr->block);
2953 if (!blockbase)
2954 return ret;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2955
2956 ret = copy_from_user(&r[0], pgc_ptr->r_data,
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2957 pgc_ptr->num_r_stages * sizeof(struct mdp_ar_gc_lut_data));
2958
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2959 if (!ret) {
2960 ret = copy_from_user(&g[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2961 pgc_ptr->g_data,
2962 pgc_ptr->num_g_stages
2963 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2964 if (!ret)
2965 ret = copy_from_user(&b[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2966 pgc_ptr->b_data,
2967 pgc_ptr->num_b_stages
2968 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2969 }
2970
2971 if (ret)
2972 return ret;
2973
2974 pgc_ptr->r_data = &r[0];
2975 pgc_ptr->g_data = &g[0];
2976 pgc_ptr->b_data = &b[0];
2977
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2978 blockbase += (uint32_t) MDP_BASE;
2979
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2980 switch (pgc_ptr->block) {
2981 case MDP_BLOCK_DMA_P:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2982 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2983 offset = (uint32_t *)(blockbase + MDP_DMA_GC_OFFSET);
2984 pgc_enable_offset = (uint32_t *) blockbase;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2985 lshift_bits = 28;
2986 break;
2987
2988 case MDP_BLOCK_OVERLAY_0:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2989 case MDP_BLOCK_OVERLAY_1:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame^]2990 offset = (uint32_t *)(blockbase +
2991 (MDP_BLOCK_OVERLAY_0 == pgc_ptr->block ?
2992 MDP_LM_0_GC_OFFSET
2993 : MDP_LM_1_GC_OFFSET));
2994
2995 pgc_enable_offset = (uint32_t *)(blockbase
2996 + MDP_LM_OP_MODE_OFFSET);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2997 lshift_bits = 2;
2998 break;
2999
3000 default:
3001 ret = -1;
3002 break;
3003 }
3004
3005 if (!ret) {
3006 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3007
3008 ret = update_ar_gc_lut(offset, pgc_ptr);
3009 if (!ret)
3010 outpdw(pgc_enable_offset, (inpdw(pgc_enable_offset)
3011 |(1<<lshift_bits)));
3012
3013 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3014 }
3015
3016 return ret;
3017}
3018
Carl Vanderlipacde4b62011-12-16 15:50:56 -0800[diff] [blame]3019static uint32_t mdp4_pp_block2igc(uint32_t block)
3020{
3021 uint32_t valid = 0;
3022 switch (block) {
3023 case MDP_BLOCK_VG_1:
3024 valid = 0x1;
3025 break;
3026 case MDP_BLOCK_VG_2:
3027 valid = 0x1;
3028 break;
3029 case MDP_BLOCK_RGB_1:
3030 valid = 0x1;
3031 break;
3032 case MDP_BLOCK_RGB_2:
3033 valid = 0x1;
3034 break;
3035 case MDP_BLOCK_DMA_P:
3036 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
3037 break;
3038 case MDP_BLOCK_DMA_S:
3039 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
3040 break;
3041 default:
3042 break;
3043 }
3044 return valid;
3045}
3046
3047static int mdp4_igc_lut_write(struct mdp_igc_lut_data *cfg, uint32_t en_off,
3048 uint32_t lut_off)
3049{
3050 int i;
3051 uint32_t base, *off_low, *off_high;
3052 uint32_t low[cfg->len];
3053 uint32_t high[cfg->len];
3054
3055 base = mdp_block2base(cfg->block);
3056
3057 if (cfg->len != 256)
3058 return -EINVAL;
3059
3060 off_low = (uint32_t *)(MDP_BASE + base + lut_off);
3061 off_high = (uint32_t *)(MDP_BASE + base + lut_off + 0x800);
3062 if (copy_from_user(&low, cfg->c0_c1_data, cfg->len * sizeof(uint32_t)))
3063 return -EFAULT;
3064 if (copy_from_user(&high, cfg->c2_data, cfg->len * sizeof(uint32_t)))
3065 return -EFAULT;
3066
3067 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3068 for (i = 0; i < cfg->len; i++) {
3069 MDP_OUTP(off_low++, low[i]);
3070 /*low address write should occur before high address write*/
3071 wmb();
3072 MDP_OUTP(off_high++, high[i]);
3073 }
3074 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3075 return 0;
3076}
3077
3078static int mdp4_igc_lut_ctrl(struct mdp_igc_lut_data *cfg)
3079{
3080 uint32_t mask, out;
3081 uint32_t base = mdp_block2base(cfg->block);
3082 int8_t shift = 0;
3083
3084 switch (cfg->block) {
3085 case MDP_BLOCK_DMA_P:
3086 case MDP_BLOCK_DMA_S:
3087 base = base;
3088 shift = 30;
3089 break;
3090 case MDP_BLOCK_VG_1:
3091 case MDP_BLOCK_VG_2:
3092 case MDP_BLOCK_RGB_1:
3093 case MDP_BLOCK_RGB_2:
3094 base += 0x58;
3095 shift = 16;
3096 break;
3097 default:
3098 return -EINVAL;
3099
3100 }
3101 out = 1<<shift;
3102 mask = ~out;
3103 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3104 out = inpdw(MDP_BASE + base) & mask;
3105 MDP_OUTP(MDP_BASE + base, out | ((cfg->ops & 0x1)<<shift));
3106 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3107
3108 return 0;
3109}
3110
3111static int mdp4_igc_lut_write_cfg(struct mdp_igc_lut_data *cfg)
3112{
3113 int ret = 0;
3114
3115 switch (cfg->block) {
3116 case MDP_BLOCK_DMA_P:
3117 case MDP_BLOCK_DMA_S:
3118 ret = mdp4_igc_lut_write(cfg, 0x00, 0x9000);
3119 break;
3120 case MDP_BLOCK_VG_1:
3121 case MDP_BLOCK_VG_2:
3122 case MDP_BLOCK_RGB_1:
3123 case MDP_BLOCK_RGB_2:
3124 ret = mdp4_igc_lut_write(cfg, 0x58, 0x5000);
3125 break;
3126 default:
3127 ret = -EINVAL;
3128 }
3129
3130 return ret;
3131}
3132
3133int mdp4_igc_lut_config(struct mdp_igc_lut_data *cfg)
3134{
3135 int ret = 0;
3136
3137 if (!mdp4_pp_block2igc(cfg->block)) {
3138 ret = -ENOTTY;
3139 goto error;
3140 }
3141
3142 switch ((cfg->ops & 0x6) >> 1) {
3143 case 0x1:
3144 pr_info("%s: IGC LUT read not supported\n", __func__);
3145 break;
3146 case 0x2:
3147 ret = mdp4_igc_lut_write_cfg(cfg);
3148 if (ret)
3149 goto error;
3150 break;
3151 default:
3152 break;
3153 }
3154
3155 ret = mdp4_igc_lut_ctrl(cfg);
3156
3157error:
3158 return ret;
3159}