| Gregory Bean | 2783cc2 | 2010-09-10 15:03:36 -0700 | [diff] [blame] | 1 | /* arch/arm/mach-msm/gpio_hw.h |
| 2 | * |
| 3 | * Copyright (C) 2007 Google, Inc. |
| 4 | * Author: Brian Swetland <swetland@google.com> |
| 5 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. |
| 6 | * |
| 7 | * This software is licensed under the terms of the GNU General Public |
| 8 | * License version 2, as published by the Free Software Foundation, and |
| 9 | * may be copied, distributed, and modified under those terms. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H |
| 19 | #define __ARCH_ARM_MACH_MSM_GPIO_HW_H |
| 20 | |
| 21 | #include <mach/msm_iomap.h> |
| 22 | |
| 23 | /* see 80-VA736-2 Rev C pp 695-751 |
| 24 | ** |
| 25 | ** These are actually the *shadow* gpio registers, since the |
| 26 | ** real ones (which allow full access) are only available to the |
| 27 | ** ARM9 side of the world. |
| 28 | ** |
| 29 | ** Since the _BASE need to be page-aligned when we're mapping them |
| 30 | ** to virtual addresses, adjust for the additional offset in these |
| 31 | ** macros. |
| 32 | */ |
| 33 | |
| 34 | #if defined(CONFIG_ARCH_MSM7X30) |
| 35 | #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) |
| 36 | #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) |
| 37 | #else |
| 38 | #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) |
| 39 | #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) |
| 40 | #endif |
| 41 | |
| 42 | #if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\ |
| 43 | defined(CONFIG_ARCH_MSM7X27) |
| 44 | |
| 45 | /* output value */ |
| 46 | #define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ |
| 47 | #define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */ |
| 48 | #define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */ |
| 49 | #define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ |
| 50 | #define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ |
| 51 | #define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */ |
| 52 | |
| 53 | /* same pin map as above, output enable */ |
| 54 | #define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) |
| 55 | #define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) |
| 56 | #define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) |
| 57 | #define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) |
| 58 | #define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) |
| 59 | #define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) |
| 60 | |
| 61 | /* same pin map as above, input read */ |
| 62 | #define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) |
| 63 | #define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) |
| 64 | #define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) |
| 65 | #define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) |
| 66 | #define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) |
| 67 | #define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) |
| 68 | |
| 69 | /* same pin map as above, 1=edge 0=level interrup */ |
| 70 | #define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) |
| 71 | #define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) |
| 72 | #define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) |
| 73 | #define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) |
| 74 | #define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) |
| 75 | #define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) |
| 76 | |
| 77 | /* same pin map as above, 1=positive 0=negative */ |
| 78 | #define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) |
| 79 | #define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) |
| 80 | #define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) |
| 81 | #define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) |
| 82 | #define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) |
| 83 | #define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) |
| 84 | |
| 85 | /* same pin map as above, interrupt enable */ |
| 86 | #define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) |
| 87 | #define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) |
| 88 | #define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) |
| 89 | #define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) |
| 90 | #define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) |
| 91 | #define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) |
| 92 | |
| 93 | /* same pin map as above, write 1 to clear interrupt */ |
| 94 | #define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) |
| 95 | #define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) |
| 96 | #define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) |
| 97 | #define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) |
| 98 | #define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) |
| 99 | #define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) |
| 100 | |
| 101 | /* same pin map as above, 1=interrupt pending */ |
| 102 | #define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) |
| 103 | #define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) |
| 104 | #define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) |
| 105 | #define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) |
| 106 | #define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) |
| 107 | #define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) |
| 108 | |
| 109 | #endif |
| 110 | |
| 111 | #if defined(CONFIG_ARCH_QSD8X50) |
| 112 | /* output value */ |
| 113 | #define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ |
| 114 | #define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */ |
| 115 | #define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */ |
| 116 | #define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ |
| 117 | #define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */ |
| 118 | #define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */ |
| 119 | #define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */ |
| 120 | #define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */ |
| 121 | |
| 122 | /* same pin map as above, output enable */ |
| 123 | #define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20) |
| 124 | #define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) |
| 125 | #define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24) |
| 126 | #define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28) |
| 127 | #define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C) |
| 128 | #define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30) |
| 129 | #define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34) |
| 130 | #define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38) |
| 131 | |
| 132 | /* same pin map as above, input read */ |
| 133 | #define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50) |
| 134 | #define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) |
| 135 | #define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54) |
| 136 | #define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58) |
| 137 | #define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C) |
| 138 | #define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60) |
| 139 | #define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64) |
| 140 | #define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68) |
| 141 | |
| 142 | /* same pin map as above, 1=edge 0=level interrup */ |
| 143 | #define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70) |
| 144 | #define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) |
| 145 | #define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74) |
| 146 | #define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78) |
| 147 | #define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C) |
| 148 | #define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80) |
| 149 | #define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84) |
| 150 | #define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88) |
| 151 | |
| 152 | /* same pin map as above, 1=positive 0=negative */ |
| 153 | #define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90) |
| 154 | #define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) |
| 155 | #define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94) |
| 156 | #define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98) |
| 157 | #define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C) |
| 158 | #define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0) |
| 159 | #define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4) |
| 160 | #define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8) |
| 161 | |
| 162 | /* same pin map as above, interrupt enable */ |
| 163 | #define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0) |
| 164 | #define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) |
| 165 | #define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4) |
| 166 | #define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8) |
| 167 | #define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC) |
| 168 | #define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0) |
| 169 | #define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4) |
| 170 | #define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8) |
| 171 | |
| 172 | /* same pin map as above, write 1 to clear interrupt */ |
| 173 | #define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0) |
| 174 | #define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) |
| 175 | #define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4) |
| 176 | #define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8) |
| 177 | #define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC) |
| 178 | #define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0) |
| 179 | #define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4) |
| 180 | #define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8) |
| 181 | |
| 182 | /* same pin map as above, 1=interrupt pending */ |
| 183 | #define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0) |
| 184 | #define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) |
| 185 | #define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4) |
| 186 | #define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8) |
| 187 | #define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC) |
| 188 | #define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100) |
| 189 | #define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104) |
| 190 | #define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108) |
| 191 | |
| 192 | #endif |
| 193 | |
| 194 | #if defined(CONFIG_ARCH_MSM7X30) |
| 195 | |
| 196 | /* output value */ |
| 197 | #define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ |
| 198 | #define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */ |
| 199 | #define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */ |
| 200 | #define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ |
| 201 | #define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ |
| 202 | #define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */ |
| 203 | #define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */ |
| 204 | #define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */ |
| 205 | |
| 206 | /* same pin map as above, output enable */ |
| 207 | #define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) |
| 208 | #define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) |
| 209 | #define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) |
| 210 | #define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) |
| 211 | #define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) |
| 212 | #define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) |
| 213 | #define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8) |
| 214 | #define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218) |
| 215 | |
| 216 | /* same pin map as above, input read */ |
| 217 | #define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) |
| 218 | #define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) |
| 219 | #define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) |
| 220 | #define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) |
| 221 | #define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) |
| 222 | #define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) |
| 223 | #define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC) |
| 224 | #define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C) |
| 225 | |
| 226 | /* same pin map as above, 1=edge 0=level interrup */ |
| 227 | #define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) |
| 228 | #define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) |
| 229 | #define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) |
| 230 | #define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) |
| 231 | #define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) |
| 232 | #define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) |
| 233 | #define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0) |
| 234 | #define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240) |
| 235 | |
| 236 | /* same pin map as above, 1=positive 0=negative */ |
| 237 | #define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) |
| 238 | #define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) |
| 239 | #define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) |
| 240 | #define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) |
| 241 | #define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) |
| 242 | #define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) |
| 243 | #define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4) |
| 244 | #define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228) |
| 245 | |
| 246 | /* same pin map as above, interrupt enable */ |
| 247 | #define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) |
| 248 | #define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) |
| 249 | #define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) |
| 250 | #define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) |
| 251 | #define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) |
| 252 | #define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) |
| 253 | #define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8) |
| 254 | #define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C) |
| 255 | |
| 256 | /* same pin map as above, write 1 to clear interrupt */ |
| 257 | #define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) |
| 258 | #define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) |
| 259 | #define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) |
| 260 | #define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) |
| 261 | #define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) |
| 262 | #define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) |
| 263 | #define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC) |
| 264 | #define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230) |
| 265 | |
| 266 | /* same pin map as above, 1=interrupt pending */ |
| 267 | #define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) |
| 268 | #define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) |
| 269 | #define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) |
| 270 | #define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) |
| 271 | #define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) |
| 272 | #define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) |
| 273 | #define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0) |
| 274 | #define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234) |
| 275 | |
| 276 | #endif |
| 277 | |
| 278 | #endif |