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Chintan Pandya40762702011-12-06 13:47:06 +05301/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Chintan Pandyacf467fc2011-12-01 17:11:11 +05302 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#ifndef __ARCH_ARM_MACH_MSM_BOARD_7627A__
14#define __ARCH_ARM_MACH_MSM_BOARD_7627A__
15
16void __init msm7627a_init_mmc(void);
17
Chintan Pandya250c2e52012-01-19 17:15:49 +053018void __init msm_msm7627a_allocate_memory_regions(void);
19void __init msm_fb_add_devices(void);
20
Chintan Pandya40762702011-12-06 13:47:06 +053021enum {
22 GPIO_EXPANDER_IRQ_BASE = NR_MSM_IRQS + NR_GPIO_IRQS,
23 GPIO_EXPANDER_GPIO_BASE = NR_MSM_GPIOS,
24 /* SURF expander */
25 GPIO_CORE_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
26 GPIO_BT_SYS_REST_EN = GPIO_CORE_EXPANDER_BASE,
27 GPIO_WLAN_EXT_POR_N,
28 GPIO_DISPLAY_PWR_EN,
29 GPIO_BACKLIGHT_EN,
30 GPIO_PRESSURE_XCLR,
31 GPIO_VREG_S3_EXP,
32 GPIO_UBM2M_PWRDWN,
33 GPIO_ETM_MODE_CS_N,
34 GPIO_HOST_VBUS_EN,
35 GPIO_SPI_MOSI,
36 GPIO_SPI_MISO,
37 GPIO_SPI_CLK,
38 GPIO_SPI_CS0_N,
39 GPIO_CORE_EXPANDER_IO13,
40 GPIO_CORE_EXPANDER_IO14,
41 GPIO_CORE_EXPANDER_IO15,
42 /* Camera expander */
43 GPIO_CAM_EXPANDER_BASE = GPIO_CORE_EXPANDER_BASE + 16,
44 GPIO_CAM_GP_STROBE_READY = GPIO_CAM_EXPANDER_BASE,
45 GPIO_CAM_GP_AFBUSY,
46 GPIO_CAM_GP_CAM_PWDN,
47 GPIO_CAM_GP_CAM1MP_XCLR,
48 GPIO_CAM_GP_CAMIF_RESET_N,
49 GPIO_CAM_GP_STROBE_CE,
50 GPIO_CAM_GP_LED_EN1,
51 GPIO_CAM_GP_LED_EN2,
52};
53
54enum {
55 QRD_GPIO_HOST_VBUS_EN = 107,
56 QRD_GPIO_BT_SYS_REST_EN = 114,
57 QRD_GPIO_WAKE_ON_WIRELESS,
58 QRD_GPIO_BACKLIGHT_EN,
59 QRD_GPIO_NC,
60 QRD_GPIO_CAM_3MP_PWDN, /* CAM_VGA */
61 QRD_GPIO_WLAN_EN,
62 QRD_GPIO_CAM_5MP_SHDN_EN,
63 QRD_GPIO_CAM_5MP_RESET,
64 QRD_GPIO_TP,
65 QRD_GPIO_CAM_GP_CAMIF_RESET,
66};
67
Chintan Pandya13490c02011-12-20 13:03:36 +053068#if defined(CONFIG_BT) && defined(CONFIG_MARIMBA_CORE)
69
70#define FPGA_MSM_CNTRL_REG2 0x90008010
71#define BAHAMA_SLAVE_ID_FM_REG 0x02
72#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
73#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
74#define FM_GPIO 83
75#define BT_PCM_BCLK_MODE 0x88
76#define BT_PCM_DIN_MODE 0x89
77#define BT_PCM_DOUT_MODE 0x8A
78#define BT_PCM_SYNC_MODE 0x8B
79#define FM_I2S_SD_MODE 0x8E
80#define FM_I2S_WS_MODE 0x8F
81#define FM_I2S_SCK_MODE 0x90
82#define I2C_PIN_CTL 0x15
Chintan Pandya40762702011-12-06 13:47:06 +053083#define I2C_NORMAL 0x40
Chintan Pandya13490c02011-12-20 13:03:36 +053084
85struct bahama_config_register {
86 u8 reg;
87 u8 value;
88 u8 mask;
89};
90
91struct bt_vreg_info {
92 const char *name;
93 unsigned int pmapp_id;
94 unsigned int min_level;
95 unsigned int max_level;
96 unsigned int is_pin_controlled;
97 struct regulator *reg;
98};
99
100extern struct platform_device msm_bt_power_device;
101
102void __init msm7627a_bt_power_init(void);
103#endif
104
Chintan Pandya40762702011-12-06 13:47:06 +0530105void __init msm7627a_camera_init(void);
106
Chintan Pandyacf467fc2011-12-01 17:11:11 +0530107#endif