blob: a6c2a12da17ac73038f787a0a56e699eb29b3707 [file] [log] [blame]
Daniel Walker10932762010-05-12 12:02:25 -07001/*
2 * Copyright (C) 2008 Google, Inc.
Stepan Moskovchenkod41cb8c2011-01-17 20:33:32 -08003 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
Daniel Walker10932762010-05-12 12:02:25 -07004 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070018#include <linux/msm_rotator.h>
Daniel Walker10932762010-05-12 12:02:25 -070019#include <linux/dma-mapping.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070020#include <linux/msm_kgsl.h>
21#include <linux/android_pmem.h>
22#include <linux/regulator/machine.h>
Daniel Walker10932762010-05-12 12:02:25 -070023#include <mach/irqs.h>
24#include <mach/msm_iomap.h>
25#include <mach/dma.h>
26#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070027#include <asm/clkdev.h>
Daniel Walker10932762010-05-12 12:02:25 -070028
29#include "devices.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030#include "gpio_hw.h"
31#include "footswitch.h"
Daniel Walker10932762010-05-12 12:02:25 -070032
33#include <asm/mach/flash.h>
34
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070035#include <asm/mach/mmc.h>
36#include <mach/msm_hsusb.h>
37#ifdef CONFIG_PMIC8058
38#include <linux/mfd/pmic8058.h>
39#endif
40#include <mach/dal_axi.h>
41#include <mach/msm_memtypes.h>
Daniel Walker10932762010-05-12 12:02:25 -070042
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070043/* EBI THERMAL DRIVER */
44static struct resource msm_ebi0_thermal_resources[] = {
45 {
46 .start = 0xA8600000,
47 .end = 0xA86005FF,
48 .name = "physbase",
49 .flags = IORESOURCE_MEM
50 }
51};
52
53struct platform_device msm_ebi0_thermal = {
54 .name = "msm_popmem-tm",
55 .id = 0,
56 .num_resources = 1,
57 .resource = msm_ebi0_thermal_resources
58};
59
60static struct resource msm_ebi1_thermal_resources[] = {
61 {
62 .start = 0xA8700000,
63 .end = 0xA87005FF,
64 .name = "physbase",
65 .flags = IORESOURCE_MEM
66 }
67};
68
69struct platform_device msm_ebi1_thermal = {
70 .name = "msm_popmem-tm",
71 .id = 1,
72 .num_resources = 1,
73 .resource = msm_ebi1_thermal_resources
74};
75
76
77static struct resource resources_uart1[] = {
78 {
79 .start = INT_UART1,
80 .end = INT_UART1,
81 .flags = IORESOURCE_IRQ,
82 },
83 {
84 .start = MSM_UART1_PHYS,
85 .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
86 .flags = IORESOURCE_MEM,
87 },
88};
Daniel Walker10932762010-05-12 12:02:25 -070089
90static struct resource resources_uart2[] = {
91 {
92 .start = INT_UART2,
93 .end = INT_UART2,
94 .flags = IORESOURCE_IRQ,
95 },
96 {
97 .start = MSM_UART2_PHYS,
98 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
99 .flags = IORESOURCE_MEM,
Stepan Moskovchenkod41cb8c2011-01-17 20:33:32 -0800100 .name = "uart_resource"
Daniel Walker10932762010-05-12 12:02:25 -0700101 },
102};
103
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104static struct resource resources_uart3[] = {
105 {
106 .start = INT_UART3,
107 .end = INT_UART3,
108 .flags = IORESOURCE_IRQ,
109 },
110 {
111 .start = MSM_UART3_PHYS,
112 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
113 .flags = IORESOURCE_MEM,
114 },
115};
116
117struct platform_device msm_device_uart1 = {
118 .name = "msm_serial",
119 .id = 0,
120 .num_resources = ARRAY_SIZE(resources_uart1),
121 .resource = resources_uart1,
122};
123
Daniel Walker10932762010-05-12 12:02:25 -0700124struct platform_device msm_device_uart2 = {
125 .name = "msm_serial",
126 .id = 1,
127 .num_resources = ARRAY_SIZE(resources_uart2),
128 .resource = resources_uart2,
129};
130
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700131struct platform_device msm_device_uart3 = {
132 .name = "msm_serial",
133 .id = 2,
134 .num_resources = ARRAY_SIZE(resources_uart3),
135 .resource = resources_uart3,
Niranjana Vishwanathapuraa8855e92010-10-06 13:52:10 -0700136};
137
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700138#define MSM_UART1DM_PHYS 0xA3300000
139#define MSM_UART2DM_PHYS 0xA3200000
140static struct resource msm_uart1_dm_resources[] = {
141 {
142 .start = MSM_UART1DM_PHYS,
143 .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1,
144 .flags = IORESOURCE_MEM,
145 },
146 {
147 .start = INT_UART1DM_IRQ,
148 .end = INT_UART1DM_IRQ,
149 .flags = IORESOURCE_IRQ,
150 },
151 {
152 .start = INT_UART1DM_RX,
153 .end = INT_UART1DM_RX,
154 .flags = IORESOURCE_IRQ,
155 },
156 {
157 .start = DMOV_HSUART1_TX_CHAN,
158 .end = DMOV_HSUART1_RX_CHAN,
159 .name = "uartdm_channels",
160 .flags = IORESOURCE_DMA,
161 },
162 {
163 .start = DMOV_HSUART1_TX_CRCI,
164 .end = DMOV_HSUART1_RX_CRCI,
165 .name = "uartdm_crci",
166 .flags = IORESOURCE_DMA,
167 },
168};
169
170static u64 msm_uart_dm1_dma_mask = DMA_BIT_MASK(32);
171
172struct platform_device msm_device_uart_dm1 = {
173 .name = "msm_serial_hs",
174 .id = 0,
175 .num_resources = ARRAY_SIZE(msm_uart1_dm_resources),
176 .resource = msm_uart1_dm_resources,
177 .dev = {
178 .dma_mask = &msm_uart_dm1_dma_mask,
179 .coherent_dma_mask = DMA_BIT_MASK(32),
180 },
181};
182
183static struct resource msm_uart2_dm_resources[] = {
184 {
185 .start = MSM_UART2DM_PHYS,
186 .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
187 .flags = IORESOURCE_MEM,
188 },
189 {
190 .start = INT_UART2DM_IRQ,
191 .end = INT_UART2DM_IRQ,
192 .flags = IORESOURCE_IRQ,
193 },
194 {
195 .start = INT_UART2DM_RX,
196 .end = INT_UART2DM_RX,
197 .flags = IORESOURCE_IRQ,
198 },
199 {
200 .start = DMOV_HSUART2_TX_CHAN,
201 .end = DMOV_HSUART2_RX_CHAN,
202 .name = "uartdm_channels",
203 .flags = IORESOURCE_DMA,
204 },
205 {
206 .start = DMOV_HSUART2_TX_CRCI,
207 .end = DMOV_HSUART2_RX_CRCI,
208 .name = "uartdm_crci",
209 .flags = IORESOURCE_DMA,
210 },
211};
212
213static u64 msm_uart_dm2_dma_mask = DMA_BIT_MASK(32);
214
215struct platform_device msm_device_uart_dm2 = {
216 .name = "msm_serial_hs",
217 .id = 1,
218 .num_resources = ARRAY_SIZE(msm_uart2_dm_resources),
219 .resource = msm_uart2_dm_resources,
220 .dev = {
221 .dma_mask = &msm_uart_dm2_dma_mask,
222 .coherent_dma_mask = DMA_BIT_MASK(32),
223 },
224};
225
226#define MSM_I2C_SIZE SZ_4K
227#define MSM_I2C_PHYS 0xACD00000
228#define MSM_I2C_2_PHYS 0xACF00000
229static struct resource resources_i2c_2[] = {
230 {
231 .start = MSM_I2C_2_PHYS,
232 .end = MSM_I2C_2_PHYS + MSM_I2C_SIZE - 1,
233 .flags = IORESOURCE_MEM,
234 },
235 {
236 .start = INT_PWB_I2C_2,
237 .end = INT_PWB_I2C_2,
238 .flags = IORESOURCE_IRQ,
239 },
240};
241
242struct platform_device msm_device_i2c_2 = {
243 .name = "msm_i2c",
244 .id = 2,
245 .num_resources = ARRAY_SIZE(resources_i2c_2),
246 .resource = resources_i2c_2,
247};
248
249static struct resource resources_i2c[] = {
250 {
251 .start = MSM_I2C_PHYS,
252 .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
253 .flags = IORESOURCE_MEM,
254 },
255 {
256 .start = INT_PWB_I2C,
257 .end = INT_PWB_I2C,
258 .flags = IORESOURCE_IRQ,
259 },
260};
261
262struct platform_device msm_device_i2c = {
263 .name = "msm_i2c",
264 .id = 0,
265 .num_resources = ARRAY_SIZE(resources_i2c),
266 .resource = resources_i2c,
267};
268
269#define MSM_QUP_PHYS 0xA8301000
270#define MSM_GSBI_QUP_I2C_PHYS 0xA8300000
271#define MSM_QUP_SIZE SZ_4K
272static struct resource resources_qup[] = {
273 {
274 .name = "qup_phys_addr",
275 .start = MSM_QUP_PHYS,
276 .end = MSM_QUP_PHYS + MSM_QUP_SIZE - 1,
277 .flags = IORESOURCE_MEM,
278 },
279 {
280 .name = "gsbi_qup_i2c_addr",
281 .start = MSM_GSBI_QUP_I2C_PHYS,
282 .end = MSM_GSBI_QUP_I2C_PHYS + 4 - 1,
283 .flags = IORESOURCE_MEM,
284 },
285 {
286 .name = "qup_in_intr",
287 .start = INT_PWB_QUP_IN,
288 .end = INT_PWB_QUP_IN,
289 .flags = IORESOURCE_IRQ,
290 },
291 {
292 .name = "qup_out_intr",
293 .start = INT_PWB_QUP_OUT,
294 .end = INT_PWB_QUP_OUT,
295 .flags = IORESOURCE_IRQ,
296 },
297 {
298 .name = "qup_err_intr",
299 .start = INT_PWB_QUP_ERR,
300 .end = INT_PWB_QUP_ERR,
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305struct platform_device qup_device_i2c = {
306 .name = "qup_i2c",
307 .id = 4,
308 .num_resources = ARRAY_SIZE(resources_qup),
309 .resource = resources_qup,
310};
311
312#ifdef CONFIG_I2C_SSBI
313#define MSM_SSBI6_PHYS 0xAD900000
314static struct resource msm_ssbi6_resources[] = {
315 {
316 .name = "ssbi_base",
317 .start = MSM_SSBI6_PHYS,
318 .end = MSM_SSBI6_PHYS + SZ_4K - 1,
319 .flags = IORESOURCE_MEM,
320 },
321};
322
323struct platform_device msm_device_ssbi6 = {
324 .name = "i2c_ssbi",
325 .id = 6,
326 .num_resources = ARRAY_SIZE(msm_ssbi6_resources),
327 .resource = msm_ssbi6_resources,
328};
329
330#define MSM_SSBI7_PHYS 0xAC800000
331static struct resource msm_ssbi7_resources[] = {
332 {
333 .name = "ssbi_base",
334 .start = MSM_SSBI7_PHYS,
335 .end = MSM_SSBI7_PHYS + SZ_4K - 1,
336 .flags = IORESOURCE_MEM,
337 },
338};
339
340struct platform_device msm_device_ssbi7 = {
341 .name = "i2c_ssbi",
342 .id = 7,
343 .num_resources = ARRAY_SIZE(msm_ssbi7_resources),
344 .resource = msm_ssbi7_resources,
345};
346#endif /* CONFIG_I2C_SSBI */
347
348#define MSM_HSUSB_PHYS 0xA3600000
349static struct resource resources_hsusb_otg[] = {
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530350 {
351 .start = MSM_HSUSB_PHYS,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700352 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530353 .flags = IORESOURCE_MEM,
354 },
355 {
356 .start = INT_USB_HS,
357 .end = INT_USB_HS,
358 .flags = IORESOURCE_IRQ,
359 },
360};
361
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530362static u64 dma_mask = 0xffffffffULL;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700363struct platform_device msm_device_hsusb_otg = {
364 .name = "msm_hsusb_otg",
365 .id = -1,
366 .num_resources = ARRAY_SIZE(resources_hsusb_otg),
367 .resource = resources_hsusb_otg,
368 .dev = {
369 .dma_mask = &dma_mask,
370 .coherent_dma_mask = 0xffffffffULL,
371 },
372};
373
374static struct resource resources_hsusb_peripheral[] = {
375 {
376 .start = MSM_HSUSB_PHYS,
377 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
378 .flags = IORESOURCE_MEM,
379 },
380 {
381 .start = INT_USB_HS,
382 .end = INT_USB_HS,
383 .flags = IORESOURCE_IRQ,
384 },
385};
386
387static struct resource resources_gadget_peripheral[] = {
388 {
389 .start = MSM_HSUSB_PHYS,
390 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
391 .flags = IORESOURCE_MEM,
392 },
393 {
394 .start = INT_USB_HS,
395 .end = INT_USB_HS,
396 .flags = IORESOURCE_IRQ,
397 },
398};
399
400struct platform_device msm_device_hsusb_peripheral = {
401 .name = "msm_hsusb_peripheral",
402 .id = -1,
403 .num_resources = ARRAY_SIZE(resources_hsusb_peripheral),
404 .resource = resources_hsusb_peripheral,
405 .dev = {
406 .dma_mask = &dma_mask,
407 .coherent_dma_mask = 0xffffffffULL,
408 },
409};
410
411struct platform_device msm_device_gadget_peripheral = {
412 .name = "msm_hsusb",
413 .id = -1,
414 .num_resources = ARRAY_SIZE(resources_gadget_peripheral),
415 .resource = resources_gadget_peripheral,
416 .dev = {
417 .dma_mask = &dma_mask,
418 .coherent_dma_mask = 0xffffffffULL,
419 },
420};
421
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530422static struct resource resources_hsusb_host[] = {
423 {
424 .start = MSM_HSUSB_PHYS,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700425 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530426 .flags = IORESOURCE_MEM,
427 },
428 {
429 .start = INT_USB_HS,
430 .end = INT_USB_HS,
431 .flags = IORESOURCE_IRQ,
432 },
433};
434
435struct platform_device msm_device_hsusb_host = {
436 .name = "msm_hsusb_host",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700437 .id = 0,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530438 .num_resources = ARRAY_SIZE(resources_hsusb_host),
439 .resource = resources_hsusb_host,
440 .dev = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700441 .dma_mask = &dma_mask,
442 .coherent_dma_mask = 0xffffffffULL,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530443 },
444};
445
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700446static struct platform_device *msm_host_devices[] = {
447 &msm_device_hsusb_host,
Daniel Walker10932762010-05-12 12:02:25 -0700448};
449
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700450int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat)
451{
452 struct platform_device *pdev;
Daniel Walker10932762010-05-12 12:02:25 -0700453
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700454 pdev = msm_host_devices[host];
455 if (!pdev)
456 return -ENODEV;
457 pdev->dev.platform_data = plat;
458 return platform_device_register(pdev);
459}
460
461struct platform_device asoc_msm_pcm = {
462 .name = "msm-dsp-audio",
463 .id = 0,
464};
465
466struct platform_device asoc_msm_dai0 = {
467 .name = "msm-codec-dai",
468 .id = 0,
469};
470
471struct platform_device asoc_msm_dai1 = {
472 .name = "msm-cpu-dai",
473 .id = 0,
474};
475
476#if defined (CONFIG_SND_MSM_MVS_DAI_SOC)
477struct platform_device asoc_msm_mvs = {
478 .name = "msm-mvs-audio",
479 .id = 0,
480};
481
482struct platform_device asoc_mvs_dai0 = {
483 .name = "mvs-codec-dai",
484 .id = 0,
485};
486
487struct platform_device asoc_mvs_dai1 = {
488 .name = "mvs-cpu-dai",
489 .id = 0,
490};
491#endif
492
493#define MSM_NAND_PHYS 0xA0200000
494#define MSM_NANDC01_PHYS 0xA0240000
495#define MSM_NANDC10_PHYS 0xA0280000
496#define MSM_NANDC11_PHYS 0xA02C0000
497#define EBI2_REG_BASE 0xA0000000
498static struct resource resources_nand[] = {
499 [0] = {
500 .name = "msm_nand_dmac",
501 .start = DMOV_NAND_CHAN,
502 .end = DMOV_NAND_CHAN,
503 .flags = IORESOURCE_DMA,
504 },
505 [1] = {
506 .name = "msm_nand_phys",
507 .start = MSM_NAND_PHYS,
508 .end = MSM_NAND_PHYS + 0x7FF,
509 .flags = IORESOURCE_MEM,
510 },
511 [2] = {
512 .name = "msm_nandc01_phys",
513 .start = MSM_NANDC01_PHYS,
514 .end = MSM_NANDC01_PHYS + 0x7FF,
515 .flags = IORESOURCE_MEM,
516 },
517 [3] = {
518 .name = "msm_nandc10_phys",
519 .start = MSM_NANDC10_PHYS,
520 .end = MSM_NANDC10_PHYS + 0x7FF,
521 .flags = IORESOURCE_MEM,
522 },
523 [4] = {
524 .name = "msm_nandc11_phys",
525 .start = MSM_NANDC11_PHYS,
526 .end = MSM_NANDC11_PHYS + 0x7FF,
527 .flags = IORESOURCE_MEM,
528 },
529 [5] = {
530 .name = "ebi2_reg_base",
531 .start = EBI2_REG_BASE,
532 .end = EBI2_REG_BASE + 0x60,
533 .flags = IORESOURCE_MEM,
534 },
535};
536
537static struct resource resources_otg[] = {
538 {
539 .start = MSM_HSUSB_PHYS,
540 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
541 .flags = IORESOURCE_MEM,
542 },
543 {
544 .start = INT_USB_HS,
545 .end = INT_USB_HS,
546 .flags = IORESOURCE_IRQ,
547 },
548 {
549 .name = "vbus_on",
550 .start = PM8058_CHGVAL_IRQ(PMIC8058_IRQ_BASE),
551 .end = PM8058_CHGVAL_IRQ(PMIC8058_IRQ_BASE),
552 .flags = IORESOURCE_IRQ,
553 },
554};
555
556struct platform_device msm_device_otg = {
557 .name = "msm_otg",
558 .id = -1,
559 .num_resources = ARRAY_SIZE(resources_otg),
560 .resource = resources_otg,
561 .dev = {
562 .coherent_dma_mask = 0xffffffffULL,
563 },
564};
565
566struct flash_platform_data msm_nand_data = {
567 .parts = NULL,
568 .nr_parts = 0,
569 .interleave = 0,
570};
571
572struct platform_device msm_device_nand = {
573 .name = "msm_nand",
574 .id = -1,
575 .num_resources = ARRAY_SIZE(resources_nand),
576 .resource = resources_nand,
577 .dev = {
578 .platform_data = &msm_nand_data,
579 },
580};
581
582struct platform_device msm_device_smd = {
583 .name = "msm_smd",
584 .id = -1,
585};
586
587struct resource msm_dmov_resource[] = {
588 {
589 .start = INT_ADM_AARM,
590 .end = (resource_size_t)MSM_DMOV_BASE,
591 .flags = IORESOURCE_IRQ,
592 },
593};
594
595struct platform_device msm_device_dmov = {
596 .name = "msm_dmov",
597 .id = -1,
598 .resource = msm_dmov_resource,
599 .num_resources = ARRAY_SIZE(msm_dmov_resource),
600};
601
602#define MSM_SDC1_BASE 0xA0400000
603#define MSM_SDC2_BASE 0xA0500000
604#define MSM_SDC3_BASE 0xA3000000
605#define MSM_SDC4_BASE 0xA3100000
606static struct resource resources_sdc1[] = {
607 {
608 .start = MSM_SDC1_BASE,
609 .end = MSM_SDC1_BASE + SZ_4K - 1,
610 .flags = IORESOURCE_MEM,
611 },
612 {
613 .start = INT_SDC1_0,
614 .end = INT_SDC1_1,
615 .flags = IORESOURCE_IRQ,
616 },
617 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700618 .name = "sdcc_dma_chnl",
619 .start = DMOV_SDC1_CHAN,
620 .end = DMOV_SDC1_CHAN,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700621 .flags = IORESOURCE_DMA,
622 },
Krishna Konda25786ec2011-07-25 16:21:36 -0700623 {
624 .name = "sdcc_dma_crci",
625 .start = DMOV_SDC1_CRCI,
626 .end = DMOV_SDC1_CRCI,
627 .flags = IORESOURCE_DMA,
628 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700629};
630
631static struct resource resources_sdc2[] = {
632 {
633 .start = MSM_SDC2_BASE,
634 .end = MSM_SDC2_BASE + SZ_4K - 1,
635 .flags = IORESOURCE_MEM,
636 },
637 {
638 .start = INT_SDC2_0,
639 .end = INT_SDC2_1,
640 .flags = IORESOURCE_IRQ,
641 },
642 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700643 .name = "sdcc_dma_chnl",
644 .start = DMOV_SDC2_CHAN,
645 .end = DMOV_SDC2_CHAN,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700646 .flags = IORESOURCE_DMA,
647 },
Krishna Konda25786ec2011-07-25 16:21:36 -0700648 {
649 .name = "sdcc_dma_crci",
650 .start = DMOV_SDC2_CRCI,
651 .end = DMOV_SDC2_CRCI,
652 .flags = IORESOURCE_DMA,
653 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700654};
655
656static struct resource resources_sdc3[] = {
657 {
658 .start = MSM_SDC3_BASE,
659 .end = MSM_SDC3_BASE + SZ_4K - 1,
660 .flags = IORESOURCE_MEM,
661 },
662 {
663 .start = INT_SDC3_0,
664 .end = INT_SDC3_1,
665 .flags = IORESOURCE_IRQ,
666 },
667 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700668 .name = "sdcc_dma_chnl",
669 .start = DMOV_SDC4_CHAN,
670 .end = DMOV_SDC4_CHAN,
671 .flags = IORESOURCE_DMA,
672 },
673 {
674 .name = "sdcc_dma_crci",
675 .start = DMOV_SDC4_CRCI,
676 .end = DMOV_SDC4_CRCI,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700677 .flags = IORESOURCE_DMA,
678 },
679};
680
681static struct resource resources_sdc4[] = {
682 {
683 .start = MSM_SDC4_BASE,
684 .end = MSM_SDC4_BASE + SZ_4K - 1,
685 .flags = IORESOURCE_MEM,
686 },
687 {
688 .start = INT_SDC4_0,
689 .end = INT_SDC4_1,
690 .flags = IORESOURCE_IRQ,
691 },
692 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700693 .name = "sdcc_dma_chnl",
694 .start = DMOV_SDC3_CHAN,
695 .end = DMOV_SDC3_CHAN,
696 .flags = IORESOURCE_DMA,
697 },
698 {
699 .name = "sdcc_dma_crci",
700 .start = DMOV_SDC3_CRCI,
701 .end = DMOV_SDC3_CRCI,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700702 .flags = IORESOURCE_DMA,
703 },
704};
705
706struct platform_device msm_device_sdc1 = {
707 .name = "msm_sdcc",
708 .id = 1,
709 .num_resources = ARRAY_SIZE(resources_sdc1),
710 .resource = resources_sdc1,
711 .dev = {
712 .coherent_dma_mask = 0xffffffff,
713 },
714};
715
716struct platform_device msm_device_sdc2 = {
717 .name = "msm_sdcc",
718 .id = 2,
719 .num_resources = ARRAY_SIZE(resources_sdc2),
720 .resource = resources_sdc2,
721 .dev = {
722 .coherent_dma_mask = 0xffffffff,
723 },
724};
725
726struct platform_device msm_device_sdc3 = {
727 .name = "msm_sdcc",
728 .id = 3,
729 .num_resources = ARRAY_SIZE(resources_sdc3),
730 .resource = resources_sdc3,
731 .dev = {
732 .coherent_dma_mask = 0xffffffff,
733 },
734};
735
736struct platform_device msm_device_sdc4 = {
737 .name = "msm_sdcc",
738 .id = 4,
739 .num_resources = ARRAY_SIZE(resources_sdc4),
740 .resource = resources_sdc4,
741 .dev = {
742 .coherent_dma_mask = 0xffffffff,
743 },
744};
745
746static struct platform_device *msm_sdcc_devices[] __initdata = {
747 &msm_device_sdc1,
748 &msm_device_sdc2,
749 &msm_device_sdc3,
750 &msm_device_sdc4,
751};
752
753int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
754{
755 struct platform_device *pdev;
756
757 if (controller < 1 || controller > 4)
758 return -EINVAL;
759
760 pdev = msm_sdcc_devices[controller-1];
761 pdev->dev.platform_data = plat;
762 return platform_device_register(pdev);
763}
764
765static struct resource msm_vidc_720p_resources[] = {
766 {
767 .start = 0xA3B00000,
768 .end = 0xA3B00000 + SZ_4K - 1,
769 .flags = IORESOURCE_MEM,
770 },
771 {
772 .start = INT_MFC720,
773 .end = INT_MFC720,
774 .flags = IORESOURCE_IRQ,
775 },
776};
777
778struct msm_vidc_platform_data vidc_platform_data = {
779 .memtype = MEMTYPE_EBI0
780};
781
782struct platform_device msm_device_vidc_720p = {
783 .name = "msm_vidc",
784 .id = 0,
785 .num_resources = ARRAY_SIZE(msm_vidc_720p_resources),
786 .resource = msm_vidc_720p_resources,
787 .dev = {
788 .platform_data = &vidc_platform_data,
789 },
790};
791
792#if defined(CONFIG_FB_MSM_MDP40)
793#define MDP_BASE 0xA3F00000
794#define PMDH_BASE 0xAD600000
795#define EMDH_BASE 0xAD700000
796#define TVENC_BASE 0xAD400000
797#else
798#define MDP_BASE 0xAA200000
799#define PMDH_BASE 0xAA600000
800#define EMDH_BASE 0xAA700000
801#define TVENC_BASE 0xAA400000
802#endif
803
804static struct resource msm_mdp_resources[] = {
805 {
806 .name = "mdp",
807 .start = MDP_BASE,
808 .end = MDP_BASE + 0x000F0000 - 1,
809 .flags = IORESOURCE_MEM,
810 },
811 {
812 .start = INT_MDP,
813 .end = INT_MDP,
814 .flags = IORESOURCE_IRQ,
815 },
816};
817
818static struct resource msm_mddi_resources[] = {
819 {
820 .name = "pmdh",
821 .start = PMDH_BASE,
822 .end = PMDH_BASE + PAGE_SIZE - 1,
823 .flags = IORESOURCE_MEM,
824 }
825};
826
827static struct resource msm_mddi_ext_resources[] = {
828 {
829 .name = "emdh",
830 .start = EMDH_BASE,
831 .end = EMDH_BASE + PAGE_SIZE - 1,
832 .flags = IORESOURCE_MEM,
833 }
834};
835
836static struct resource msm_ebi2_lcd_resources[] = {
837 {
838 .name = "base",
839 .start = 0xa0d00000,
840 .end = 0xa0d00000 + PAGE_SIZE - 1,
841 .flags = IORESOURCE_MEM,
842 },
843 {
844 .name = "lcd01",
845 .start = 0x98000000,
846 .end = 0x98000000 + 0x80000 - 1,
847 .flags = IORESOURCE_MEM,
848 },
849 {
850 .name = "lcd02",
851 .start = 0x9c000000,
852 .end = 0x9c000000 + 0x80000 - 1,
853 .flags = IORESOURCE_MEM,
854 },
855};
856
857static struct resource msm_tvenc_resources[] = {
858 {
859 .name = "tvenc",
860 .start = TVENC_BASE,
861 .end = TVENC_BASE + PAGE_SIZE - 1,
862 .flags = IORESOURCE_MEM,
863 }
864};
865
866#ifdef CONFIG_FB_MSM_TVOUT
867static struct resource tvout_device_resources[] = {
868 {
869 .name = "tvout_device_irq",
870 .start = INT_TV_ENC,
871 .end = INT_TV_ENC,
872 .flags = IORESOURCE_IRQ,
873 },
874};
875#endif
876
877static struct platform_device msm_mdp_device = {
878 .name = "mdp",
879 .id = 0,
880 .num_resources = ARRAY_SIZE(msm_mdp_resources),
881 .resource = msm_mdp_resources,
882};
883
884static struct platform_device msm_mddi_device = {
885 .name = "mddi",
886 .id = 0,
887 .num_resources = ARRAY_SIZE(msm_mddi_resources),
888 .resource = msm_mddi_resources,
889};
890
891static struct platform_device msm_mddi_ext_device = {
892 .name = "mddi_ext",
893 .id = 0,
894 .num_resources = ARRAY_SIZE(msm_mddi_ext_resources),
895 .resource = msm_mddi_ext_resources,
896};
897
898static struct platform_device msm_ebi2_lcd_device = {
899 .name = "ebi2_lcd",
900 .id = 0,
901 .num_resources = ARRAY_SIZE(msm_ebi2_lcd_resources),
902 .resource = msm_ebi2_lcd_resources,
903};
904
905static struct platform_device msm_lcdc_device = {
906 .name = "lcdc",
907 .id = 0,
908};
909
910static struct platform_device msm_dtv_device = {
911 .name = "dtv",
912 .id = 0,
913};
914
915static struct platform_device msm_tvenc_device = {
916 .name = "tvenc",
917 .id = 0,
918 .num_resources = ARRAY_SIZE(msm_tvenc_resources),
919 .resource = msm_tvenc_resources,
920};
921
922#ifdef CONFIG_FB_MSM_TVOUT
923static struct platform_device tvout_msm_device = {
924 .name = "tvout_device",
925 .id = 0,
926 .num_resources = ARRAY_SIZE(tvout_device_resources),
927 .resource = tvout_device_resources,
928};
929#endif
930
931/* TSIF begin */
932#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
933
934#define MSM_TSIF_PHYS (0xa3400000)
935#define MSM_TSIF_SIZE (0x200)
936
937static struct resource tsif_resources[] = {
938 [0] = {
939 .flags = IORESOURCE_IRQ,
940 .start = INT_TSIF,
941 .end = INT_TSIF,
942 },
943 [1] = {
944 .flags = IORESOURCE_MEM,
945 .start = MSM_TSIF_PHYS,
946 .end = MSM_TSIF_PHYS + MSM_TSIF_SIZE - 1,
947 },
948 [2] = {
949 .flags = IORESOURCE_DMA,
950 .start = DMOV_TSIF_CHAN,
951 .end = DMOV_TSIF_CRCI,
952 },
953};
954
955static void tsif_release(struct device *dev)
956{
957 dev_info(dev, "release\n");
958}
959
960struct platform_device msm_device_tsif = {
961 .name = "msm_tsif",
962 .id = 0,
963 .num_resources = ARRAY_SIZE(tsif_resources),
964 .resource = tsif_resources,
965 .dev = {
966 .release = tsif_release,
967 },
968};
969#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
970/* TSIF end */
971
972
973
974#ifdef CONFIG_MSM_ROTATOR
975static struct resource resources_msm_rotator[] = {
976 {
977 .start = 0xA3E00000,
978 .end = 0xA3F00000 - 1,
979 .flags = IORESOURCE_MEM,
980 },
981 {
982 .start = INT_ROTATOR,
983 .end = INT_ROTATOR,
984 .flags = IORESOURCE_IRQ,
985 },
986};
987
988static struct msm_rot_clocks rotator_clocks[] = {
989 {
990 .clk_name = "rotator_clk",
991 .clk_type = ROTATOR_CORE_CLK,
992 .clk_rate = 0,
993 },
994 {
995 .clk_name = "rotator_pclk",
996 .clk_type = ROTATOR_PCLK,
997 .clk_rate = 0,
998 },
999 {
1000 .clk_name = "rotator_imem_clk",
1001 .clk_type = ROTATOR_IMEM_CLK,
1002 .clk_rate = 0,
1003 },
1004};
1005
1006static struct msm_rotator_platform_data rotator_pdata = {
1007 .number_of_clocks = ARRAY_SIZE(rotator_clocks),
1008 .hardware_version_number = 0x1000303,
1009 .rotator_clks = rotator_clocks,
1010 .regulator_name = "fs_rot",
1011};
1012
1013struct platform_device msm_rotator_device = {
1014 .name = "msm_rotator",
1015 .id = 0,
1016 .num_resources = ARRAY_SIZE(resources_msm_rotator),
1017 .resource = resources_msm_rotator,
1018 .dev = {
1019 .platform_data = &rotator_pdata,
1020 },
1021};
1022#endif
1023
1024static void __init msm_register_device(struct platform_device *pdev, void *data)
1025{
1026 int ret;
1027
1028 pdev->dev.platform_data = data;
1029
1030 ret = platform_device_register(pdev);
1031 if (ret)
1032 dev_err(&pdev->dev,
1033 "%s: platform_device_register() failed = %d\n",
1034 __func__, ret);
1035}
1036
1037void __init msm_fb_register_device(char *name, void *data)
1038{
1039 if (!strncmp(name, "mdp", 3))
1040 msm_register_device(&msm_mdp_device, data);
1041 else if (!strncmp(name, "pmdh", 4))
1042 msm_register_device(&msm_mddi_device, data);
1043 else if (!strncmp(name, "emdh", 4))
1044 msm_register_device(&msm_mddi_ext_device, data);
1045 else if (!strncmp(name, "ebi2", 4))
1046 msm_register_device(&msm_ebi2_lcd_device, data);
1047 else if (!strncmp(name, "tvenc", 5))
1048 msm_register_device(&msm_tvenc_device, data);
1049 else if (!strncmp(name, "lcdc", 4))
1050 msm_register_device(&msm_lcdc_device, data);
1051 else if (!strncmp(name, "dtv", 3))
1052 msm_register_device(&msm_dtv_device, data);
1053#ifdef CONFIG_FB_MSM_TVOUT
1054 else if (!strncmp(name, "tvout_device", 12))
1055 msm_register_device(&tvout_msm_device, data);
1056#endif
1057 else
1058 printk(KERN_ERR "%s: unknown device! %s\n", __func__, name);
1059}
1060
1061static struct platform_device msm_camera_device = {
1062 .name = "msm_camera",
1063 .id = 0,
1064};
1065
1066void __init msm_camera_register_device(void *res, uint32_t num,
1067 void *data)
1068{
1069 msm_camera_device.num_resources = num;
1070 msm_camera_device.resource = res;
1071
1072 msm_register_device(&msm_camera_device, data);
1073}
1074
1075struct resource kgsl_3d0_resources[] = {
1076 {
1077 .name = KGSL_3D0_REG_MEMORY,
1078 .start = 0xA3500000, /* 3D GRP address */
1079 .end = 0xA351ffff,
1080 .flags = IORESOURCE_MEM,
1081 },
1082 {
1083 .name = KGSL_3D0_IRQ,
1084 .start = INT_GRP_3D,
1085 .end = INT_GRP_3D,
1086 .flags = IORESOURCE_IRQ,
1087 },
1088};
1089
1090static struct kgsl_device_platform_data kgsl_3d0_pdata = {
1091 .pwr_data = {
1092 .pwrlevel = {
1093 {
1094 .gpu_freq = 245760000,
1095 .bus_freq = 192000000,
1096 },
1097 {
1098 .gpu_freq = 192000000,
1099 .bus_freq = 152000000,
1100 },
1101 {
1102 .gpu_freq = 192000000,
1103 .bus_freq = 0,
1104 },
1105 },
1106 .init_level = 0,
1107 .num_levels = 3,
1108 .set_grp_async = set_grp3d_async,
1109 .idle_timeout = HZ/20,
1110 .nap_allowed = true,
1111 },
1112 .clk = {
1113 .name = {
1114 .clk = "grp_clk",
1115 .pclk = "grp_pclk",
1116 },
1117 },
1118 .imem_clk_name = {
1119 .clk = "imem_clk",
1120 .pclk = NULL,
1121 },
1122};
1123
1124struct platform_device msm_kgsl_3d0 = {
1125 .name = "kgsl-3d0",
1126 .id = 0,
1127 .num_resources = ARRAY_SIZE(kgsl_3d0_resources),
1128 .resource = kgsl_3d0_resources,
1129 .dev = {
1130 .platform_data = &kgsl_3d0_pdata,
1131 },
1132};
1133
1134static struct resource kgsl_2d0_resources[] = {
1135 {
1136 .name = KGSL_2D0_REG_MEMORY,
1137 .start = 0xA3900000, /* Z180 base address */
1138 .end = 0xA3900FFF,
1139 .flags = IORESOURCE_MEM,
1140 },
1141 {
1142 .name = KGSL_2D0_IRQ,
1143 .start = INT_GRP_2D,
1144 .end = INT_GRP_2D,
1145 .flags = IORESOURCE_IRQ,
1146 },
1147};
1148
1149static struct kgsl_device_platform_data kgsl_2d0_pdata = {
1150 .pwr_data = {
1151 .pwrlevel = {
1152 {
1153 .gpu_freq = 0,
1154 .bus_freq = 192000000,
1155 },
1156 },
1157 .init_level = 0,
1158 .num_levels = 1,
1159 /* HW workaround, run Z180 SYNC @ 192 MHZ */
1160 .set_grp_async = NULL,
1161 .idle_timeout = HZ/10,
1162 .nap_allowed = true,
1163 },
1164 .clk = {
1165 .name = {
1166 .clk = "grp_2d_clk",
1167 .pclk = "grp_2d_pclk",
1168 },
1169 },
1170};
1171
1172struct platform_device msm_kgsl_2d0 = {
1173 .name = "kgsl-2d0",
1174 .id = 0,
1175 .num_resources = ARRAY_SIZE(kgsl_2d0_resources),
1176 .resource = kgsl_2d0_resources,
1177 .dev = {
1178 .platform_data = &kgsl_2d0_pdata,
1179 },
1180};
1181
1182struct platform_device *msm_footswitch_devices[] = {
1183 FS_PCOM(FS_GFX2D0, "fs_gfx2d0"),
1184 FS_PCOM(FS_GFX3D, "fs_gfx3d"),
1185 FS_PCOM(FS_MDP, "fs_mdp"),
1186 FS_PCOM(FS_MFC, "fs_mfc"),
1187 FS_PCOM(FS_ROT, "fs_rot"),
1188 FS_PCOM(FS_VFE, "fs_vfe"),
1189 FS_PCOM(FS_VPE, "fs_vpe"),
1190};
1191unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);