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review.evervolv.com / android_kernel_htc_msm8960 / 25d83cbfaa44e1b9170c0941c3ef52ca39f54ccc / . / arch / s390 / kernel / reipl64.S
blob: de7435054f7ccd4c45754824d8808d7ee83cfb8e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * arch/s390/kernel/reipl.S
3 *
4 * S390 version
5 * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]7 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]8 */
9
10#include <asm/lowcore.h>
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]11 .globl do_reipl_asm
12do_reipl_asm: basr %r13,0
13
14 # do store status of all registers
15
16.Lpg0: stg %r1,.Lregsave-.Lpg0(%r13)
17 lghi %r1,0x1000
18 stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1)
19 lg %r0,.Lregsave-.Lpg0(%r13)
20 stg %r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1)
21 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1)
22 stam %a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1)
23 stpx __LC_PREFIX_SAVE_AREA-0x1000(%r1)
24 stfpc __LC_FP_CREG_SAVE_AREA-0x1000(%r1)
25 stckc .Lclkcmp-.Lpg0(%r13)
26 mvc __LC_CLOCK_COMP_SAVE_AREA-0x1000(8,%r1),.Lclkcmp-.Lpg0(%r13)
27 stpt __LC_CPU_TIMER_SAVE_AREA-0x1000(%r1)
28 stg %r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1)
29
30 lpswe .Lnewpsw-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]31.Lpg1: lctlg %c6,%c6,.Lall-.Lpg0(%r13)
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]32 stctg %c0,%c0,.Lregsave-.Lpg0(%r13)
33 ni .Lregsave+4-.Lpg0(%r13),0xef
34 lctlg %c0,%c0,.Lregsave-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]35 lgr %r1,%r2
36 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
37 stsch .Lschib-.Lpg0(%r13)
38 oi .Lschib+5-.Lpg0(%r13),0x84
39.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
40 msch .Lschib-.Lpg0(%r13)
41 lghi %r0,5
42.Lssch: ssch .Liplorb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]43 jz .L001
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]44 brct %r0,.Lssch
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]45 bas %r14,.Ldisab-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]46.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
47.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]48.Lcont: c %r1,__LC_SUBCHANNEL_ID
49 jnz .Ltpi
50 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
51 jnz .Ltpi
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]52 tsch .Liplirb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]53 tm .Liplirb+9-.Lpg0(%r13),0xbf
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]54 jz .L002
55 bas %r14,.Ldisab-.Lpg0(%r13)
56.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
57 jz .L003
58 bas %r14,.Ldisab-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]59.L003: spx .Lnull-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]60 st %r1,__LC_SUBCHANNEL_ID
61 lhi %r1,0 # mode 0 = esa
62 slr %r0,%r0 # set cpuid to zero
63 sigp %r1,%r0,0x12 # switch to esa mode
64 lpsw 0
65.Ldisab: sll %r14,1
66 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
67 st %r14,.Ldispsw+12-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]68 lpswe .Ldispsw-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]69 .align 8
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]70.Lclkcmp: .quad 0x0000000000000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]71.Lall: .quad 0x00000000ff000000
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]72.Lregsave: .quad 0x0000000000000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]73.Lnull: .long 0x0000000000000000
74 .align 16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]75/*
76 * These addresses have to be 31 bit otherwise
77 * the sigp will throw a specifcation exception
78 * when switching to ESA mode as bit 31 be set
79 * in the ESA psw.
80 * Bit 31 of the addresses has to be 0 for the
81 * 31bit lpswe instruction a fact they appear to have
82 * ommited from the pop.
83 */
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]84.Lnewpsw: .quad 0x0000000080000000
85 .quad .Lpg1
86.Lpcnew: .quad 0x0000000080000000
87 .quad .Lecs
88.Lionew: .quad 0x0000000080000000
89 .quad .Lcont
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]90.Lwaitpsw: .quad 0x0202000080000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]91 .quad .Ltpi
92.Ldispsw: .quad 0x0002000080000000
93 .quad 0x0000000000000000
94.Liplccws: .long 0x02000000,0x60000018
95 .long 0x08000008,0x20000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]96.Liplorb: .long 0x0049504c,0x0040ff80
97 .long 0x00000000+.Liplccws
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame^]98.Lschib: .long 0x00000000,0x00000000
99 .long 0x00000000,0x00000000
100 .long 0x00000000,0x00000000
101 .long 0x00000000,0x00000000
102 .long 0x00000000,0x00000000
103 .long 0x00000000,0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]104.Liplirb: .long 0x00000000,0x00000000
105 .long 0x00000000,0x00000000
106 .long 0x00000000,0x00000000
107 .long 0x00000000,0x00000000
108 .long 0x00000000,0x00000000
109 .long 0x00000000,0x00000000
110 .long 0x00000000,0x00000000
111 .long 0x00000000,0x00000000