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review.evervolv.com / android_kernel_htc_msm8960 / 2637d5b498b979b46a01690d22ecca1e5b79b903 / . / drivers / media / common / tuners / mxl5005s.c
blob: 3c4330614faf2b6b9172102602a28352cb172011 [file] [log] [blame]
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]1/*
2 * For the Realtek RTL chip RTL2831U
3 * Realtek Release Date: 2008-03-14, ver 080314
4 * Realtek version RTL2831 Linux driver version 080314
5 * ver 080314
6 *
7 * for linux kernel version 2.6.21.4 - 2.6.22-14
8 * support MXL5005s and MT2060 tuners (support tuner auto-detecting)
9 * support two IR types -- RC5 and NEC
10 *
11 * Known boards with Realtek RTL chip RTL2821U
12 * Freecom USB stick 14aa:0160 (version 4)
13 * Conceptronic CTVDIGRCU
14 *
15 * Copyright (c) 2008 Realtek
16 * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
17 * This code is placed under the terms of the GNU General Public License
18 *
19 * Released by Realtek under GPLv2.
20 * Thanks to Realtek for a lot of support we received !
21 *
22 * Revision: 080314 - original version
23 */
24
25
26/**
27
28@file
29
30@brief MxL5005S tuner module definition
31
32One can manipulate MxL5005S tuner through MxL5005S module.
33MxL5005S module is derived from tuner module.
34
35*/
36
37
Steven Toth2637d5b2008-05-01 05:01:31 -0300[diff] [blame^]38#include "mxl5005s.h"
Steven Toth52c99bd2008-05-01 04:57:01 -0300[diff] [blame]39
40/**
41
42@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module
43
44MxL5005S tuner module is drived from tuner base module.
45
46@see TUNER_BASE_MODULE
47
48*/
49
50
51
52
53
54/**
55
56@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder
57@ingroup MXL5005S_TUNER_MODULE
58
59One should call MxL5005S module builder before using MxL5005S module.
60
61*/
62/// @{
63
64
65
66
67
68/**
69
70@brief MxL5005S tuner module builder
71
72Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions,
73and initialize module private variables.
74
75
76@param [in] ppTuner Pointer to MxL5005S tuner module pointer
77@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory
78@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory
79@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory
80@param [in] DeviceAddr MxL5005S I2C device address
81@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz
82
83
84@note \n
85 -# One should call BuildMxl5005sModule() to build MxL5005S module before using it.
86
87*/
88void
89BuildMxl5005sModule(
90 TUNER_MODULE **ppTuner,
91 TUNER_MODULE *pTunerModuleMemory,
92 MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory,
93 BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory,
94 I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory,
95 unsigned char DeviceAddr,
96 int StandardMode
97 )
98{
99 MXL5005S_EXTRA_MODULE *pExtra;
100
101 int MxlModMode;
102 int MxlIfMode;
103 unsigned long MxlBandwitdh;
104 unsigned long MxlIfFreqHz;
105 unsigned long MxlCrystalFreqHz;
106 int MxlAgcMode;
107 unsigned short MxlTop;
108 unsigned short MxlIfOutputLoad;
109 int MxlClockOut;
110 int MxlDivOut;
111 int MxlCapSel;
112 int MxlRssiOnOff;
113 unsigned char MxlStandard;
114 unsigned char MxlTfType;
115
116
117
118 // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer.
119 *ppTuner = pTunerModuleMemory;
120 (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory;
121 (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory;
122 (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory;
123
124 // Get tuner extra module pointer.
125 pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra;
126
127
128 // Set I2C bridge tuner arguments.
129 mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner);
130
131
132 // Set tuner module manipulating function pointers.
133 (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr;
134
135 (*ppTuner)->GetTunerType = mxl5005s_GetTunerType;
136 (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr;
137
138 (*ppTuner)->Initialize = mxl5005s_Initialize;
139 (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz;
140 (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz;
141
142
143 // Set tuner extra module manipulating function pointers.
144 pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable;
145 pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits;
146 pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode;
147 pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz;
148
149
150 // Initialize tuner parameter setting status.
151 (*ppTuner)->IsDeviceAddrSet = NO;
152 (*ppTuner)->IsRfFreqHzSet = NO;
153
154
155 // Set MxL5005S parameters.
156 MxlModMode = MXL_DIGITAL_MODE;
157 MxlIfMode = MXL_ZERO_IF;
158 MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ;
159 MxlIfFreqHz = IF_FREQ_4570000HZ;
160 MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ;
161 MxlAgcMode = MXL_SINGLE_AGC;
162 MxlTop = MXL5005S_TOP_25P2;
163 MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM;
164 MxlClockOut = MXL_CLOCK_OUT_DISABLE;
165 MxlDivOut = MXL_DIV_OUT_4;
166 MxlCapSel = MXL_CAP_SEL_ENABLE;
167 MxlRssiOnOff = MXL_RSSI_ENABLE;
168 MxlTfType = MXL_TF_C_H;
169
170
171 // Set MxL5005S parameters according to standard mode
172 switch(StandardMode)
173 {
174 default:
175 case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break;
176 case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break;
177 }
178
179
180 // Set MxL5005S extra module.
181 pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0;
182
183 MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode,
184 MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad,
185 (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff,
186 MxlStandard, MxlTfType);
187
188
189
190 // Note: Need to set all module arguments before using module functions.
191
192
193 // Set tuner type.
194 (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S;
195
196 // Set tuner I2C device address.
197 (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr);
198
199
200 return;
201}
202
203
204
205
206
207/// @}
208
209
210
211
212
213/**
214
215@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module
216@ingroup MXL5005S_TUNER_MODULE
217
218One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to
219manipulate MxL5005S tuner.
220
221*/
222/// @{
223
224
225
226
227
228/**
229
230@brief Set MxL5005S tuner I2C device address.
231
232@note \n
233 -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr().
234
235@see TUNER_FP_SET_DEVICE_ADDR
236
237*/
238void
239mxl5005s_SetDeviceAddr(
240 TUNER_MODULE *pTuner,
241 unsigned char DeviceAddr
242 )
243{
244 // Set tuner I2C device address.
245 pTuner->DeviceAddr = DeviceAddr;
246 pTuner->IsDeviceAddrSet = YES;
247
248
249 return;
250}
251
252
253
254
255
256/**
257
258@brief Get MxL5005S tuner type.
259
260@note \n
261 -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType().
262
263@see TUNER_FP_GET_TUNER_TYPE
264
265*/
266void
267mxl5005s_GetTunerType(
268 TUNER_MODULE *pTuner,
269 int *pTunerType
270 )
271{
272 // Get tuner type from tuner module.
273 *pTunerType = pTuner->TunerType;
274
275
276 return;
277}
278
279
280
281
282
283/**
284
285@brief Get MxL5005S tuner I2C device address.
286
287@note \n
288 -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr().
289
290@see TUNER_FP_GET_DEVICE_ADDR
291
292*/
293int
294mxl5005s_GetDeviceAddr(
295 TUNER_MODULE *pTuner,
296 unsigned char *pDeviceAddr
297 )
298{
299 // Get tuner I2C device address from tuner module.
300 if(pTuner->IsDeviceAddrSet != YES)
301 goto error_status_get_tuner_i2c_device_addr;
302
303 *pDeviceAddr = pTuner->DeviceAddr;
304
305
306 return FUNCTION_SUCCESS;
307
308
309error_status_get_tuner_i2c_device_addr:
310 return FUNCTION_ERROR;
311}
312
313
314
315
316
317/**
318
319@brief Initialize MxL5005S tuner.
320
321@note \n
322 -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize().
323
324@see TUNER_FP_INITIALIZE
325
326*/
327int
328mxl5005s_Initialize(
329 struct dvb_usb_device* dib,
330 TUNER_MODULE *pTuner
331 )
332{
333 MXL5005S_EXTRA_MODULE *pExtra;
334
335 unsigned char AgcMasterByte;
336 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
337 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
338 int TableLen;
339
340
341
342 // Get tuner extra module.
343 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
344
345
346 // Get AGC master byte
347 AgcMasterByte = pExtra->AgcMasterByte;
348
349
350 // Initialize MxL5005S tuner according to MxL5005S tuner example code.
351
352 // Tuner initialization stage 0
353 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
354 AddrTable[0] = MASTER_CONTROL_ADDR;
355 ByteTable[0] |= AgcMasterByte;
356
357 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS)
358 goto error_status_set_tuner_registers;
359
360
361 // Tuner initialization stage 1
362 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen);
363
364 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
365 goto error_status_set_tuner_registers;
366
367
368 return FUNCTION_SUCCESS;
369
370
371error_status_set_tuner_registers:
372 return FUNCTION_ERROR;
373}
374
375
376
377
378
379/**
380
381@brief Set MxL5005S tuner RF frequency in Hz.
382
383@note \n
384 -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz().
385
386@see TUNER_FP_SET_RF_FREQ_HZ
387
388*/
389int
390mxl5005s_SetRfFreqHz(
391 struct dvb_usb_device* dib,
392 TUNER_MODULE *pTuner,
393 unsigned long RfFreqHz
394 )
395{
396 MXL5005S_EXTRA_MODULE *pExtra;
397 BASE_INTERFACE_MODULE *pBaseInterface;
398
399 unsigned char AgcMasterByte;
400 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
401 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
402 int TableLen;
403
404 unsigned long IfDivval;
405 unsigned char MasterControlByte;
406
407
408
409 // Get tuner extra module and base interface module.
410 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
411 pBaseInterface = pTuner->pBaseInterface;
412
413
414 // Get AGC master byte
415 AgcMasterByte = pExtra->AgcMasterByte;
416
417
418 // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code.
419
420 // Tuner RF frequency setting stage 0
421 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ;
422 AddrTable[0] = MASTER_CONTROL_ADDR;
423 ByteTable[0] |= AgcMasterByte;
424
425 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS)
426 goto error_status_set_tuner_registers;
427
428
429 // Tuner RF frequency setting stage 1
430 MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz);
431
432 MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval);
433
434 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0);
435 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1);
436 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8);
437
438 MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ;
439
440 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
441 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
442 ByteTable[TableLen] = MasterControlByte | AgcMasterByte;
443 TableLen += 1;
444
445 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
446 goto error_status_set_tuner_registers;
447
448
449 // Wait 30 ms.
450 pBaseInterface->WaitMs(pBaseInterface, 30);
451
452
453 // Tuner RF frequency setting stage 2
454 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ;
455 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ;
456 MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ;
457
458 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
459 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
460 ByteTable[TableLen] = MasterControlByte | AgcMasterByte ;
461 TableLen += 1;
462
463 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
464 goto error_status_set_tuner_registers;
465
466
467 // Set tuner RF frequency parameter.
468 pTuner->RfFreqHz = RfFreqHz;
469 pTuner->IsRfFreqHzSet = YES;
470
471
472 return FUNCTION_SUCCESS;
473
474
475error_status_set_tuner_registers:
476 return FUNCTION_ERROR;
477}
478
479
480
481
482
483/**
484
485@brief Get MxL5005S tuner RF frequency in Hz.
486
487@note \n
488 -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz().
489
490@see TUNER_FP_GET_RF_FREQ_HZ
491
492*/
493int
494mxl5005s_GetRfFreqHz(
495 struct dvb_usb_device* dib,
496 TUNER_MODULE *pTuner,
497 unsigned long *pRfFreqHz
498 )
499{
500 // Get tuner RF frequency in Hz from tuner module.
501 if(pTuner->IsRfFreqHzSet != YES)
502 goto error_status_get_tuner_rf_frequency;
503
504 *pRfFreqHz = pTuner->RfFreqHz;
505
506
507 return FUNCTION_SUCCESS;
508
509
510error_status_get_tuner_rf_frequency:
511 return FUNCTION_ERROR;
512}
513
514
515
516
517
518/**
519
520@brief Set MxL5005S tuner registers with table.
521
522*/
523/*
524int
525mxl5005s_SetRegsWithTable(
526 struct dvb_usb_device* dib,
527 TUNER_MODULE *pTuner,
528 unsigned char *pAddrTable,
529 unsigned char *pByteTable,
530 int TableLen
531 )
532{
533 BASE_INTERFACE_MODULE *pBaseInterface;
534 I2C_BRIDGE_MODULE *pI2cBridge;
535 unsigned char WritingByteNumMax;
536
537 int i;
538 unsigned char WritingBuffer[I2C_BUFFER_LEN];
539 unsigned char WritingIndex;
540
541
542
543 // Get base interface, I2C bridge, and maximum writing byte number.
544 pBaseInterface = pTuner->pBaseInterface;
545 pI2cBridge = pTuner->pI2cBridge;
546 WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax;
547
548
549 // Set registers with table.
550 // Note: 1. The I2C format of MxL5005S is described as follows:
551 // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit
552 // ...
553 // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit
554 // 2. The latch_byte is 0xfe.
555 // 3. The following writing byte separating scheme takes latch_byte as two byte data.
556 for(i = 0, WritingIndex = 0; i < TableLen; i++)
557 {
558 // Put register address and register byte value into writing buffer.
559 WritingBuffer[WritingIndex] = pAddrTable[i];
560 WritingBuffer[WritingIndex + 1] = pByteTable[i];
561 WritingIndex += 2;
562
563 // If writing buffer is full, send the I2C writing command with writing buffer.
564 if(WritingIndex > (WritingByteNumMax - 2))
565 {
566 if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS)
567 goto error_status_set_tuner_registers;
568
569 WritingIndex = 0;
570 }
571 }
572
573
574 // Send the last I2C writing command with writing buffer and latch byte.
575 WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE;
576 WritingIndex += 1;
577
578 if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS)
579 goto error_status_set_tuner_registers;
580
581
582 return FUNCTION_SUCCESS;
583
584
585error_status_set_tuner_registers:
586 return FUNCTION_ERROR;
587}
588*/
589
590
591int
592mxl5005s_SetRegsWithTable(
593 struct dvb_usb_device* dib,
594 TUNER_MODULE *pTuner,
595 unsigned char *pAddrTable,
596 unsigned char *pByteTable,
597 int TableLen
598 )
599{
600 int i;
601 u8 end_two_bytes_buf[]={ 0 , 0 };
602 u8 tuner_addr=0x00;
603
604 pTuner->GetDeviceAddr(pTuner , &tuner_addr);
605
606 for( i = 0 ; i < TableLen - 1 ; i++)
607 {
608 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) )
609 return FUNCTION_ERROR;
610 }
611
612 end_two_bytes_buf[0] = pByteTable[i];
613 end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE;
614
615 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) )
616 return FUNCTION_ERROR;
617
618 return FUNCTION_SUCCESS;
619}
620
621
622
623
624
625/**
626
627@brief Set MxL5005S tuner register bits.
628
629*/
630int
631mxl5005s_SetRegMaskBits(
632 struct dvb_usb_device* dib,
633 TUNER_MODULE *pTuner,
634 unsigned char RegAddr,
635 unsigned char Msb,
636 unsigned char Lsb,
637 const unsigned char WritingValue
638 )
639{
640 MXL5005S_EXTRA_MODULE *pExtra;
641
642 int i;
643
644 unsigned char Mask;
645 unsigned char Shift;
646
647 unsigned char RegByte;
648
649
650
651 // Get tuner extra module.
652 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
653
654
655 // Generate mask and shift according to MSB and LSB.
656 Mask = 0;
657 for(i = Lsb; i < (unsigned char)(Msb + 1); i++)
658 Mask |= 0x1 << i;
659
660 Shift = Lsb;
661
662
663 // Get tuner register byte according to register adddress.
664 MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte);
665
666
667 // Reserve register byte unmask bit with mask and inlay writing value into it.
668 RegByte &= ~Mask;
669 RegByte |= (WritingValue << Shift) & Mask;
670
671
672 // Update tuner register byte table.
673 MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte);
674
675
676 // Write tuner register byte with writing byte.
677 if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS)
678 goto error_status_set_tuner_registers;
679
680
681 return FUNCTION_SUCCESS;
682
683
684error_status_set_tuner_registers:
685 return FUNCTION_ERROR;
686}
687
688
689
690
691
692/**
693
694@brief Set MxL5005S tuner spectrum mode.
695
696*/
697int
698mxl5005s_SetSpectrumMode(
699 struct dvb_usb_device* dib,
700 TUNER_MODULE *pTuner,
701 int SpectrumMode
702 )
703{
704 static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] =
705 {
706 // BB_IQSWAP
707 0, // Normal spectrum
708 1, // Inverse spectrum
709 };
710
711
712 MXL5005S_EXTRA_MODULE *pExtra;
713
714
715
716 // Get tuner extra module.
717 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
718
719
720 // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode.
721 if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB,
722 MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS)
723 goto error_status_set_tuner_registers;
724
725
726 return FUNCTION_SUCCESS;
727
728
729error_status_set_tuner_registers:
730 return FUNCTION_ERROR;
731}
732
733
734
735
736
737/**
738
739@brief Set MxL5005S tuner bandwidth in Hz.
740
741*/
742int
743mxl5005s_SetBandwidthHz(
744 struct dvb_usb_device* dib,
745 TUNER_MODULE *pTuner,
746 unsigned long BandwidthHz
747 )
748{
749 MXL5005S_EXTRA_MODULE *pExtra;
750
751 unsigned char BbDlpfBandsel;
752
753
754
755 // Get tuner extra module.
756 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
757
758
759 // Set BB_DLPF_BANDSEL according to bandwidth.
760 switch(BandwidthHz)
761 {
762 default:
763 case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break;
764 case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break;
765 case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break;
766 }
767
768 if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB,
769 MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS)
770 goto error_status_set_tuner_registers;
771
772
773 return FUNCTION_SUCCESS;
774
775
776error_status_set_tuner_registers:
777 return FUNCTION_ERROR;
778}
779
780
781
782
783
784/// @}
785
786
787
788
789
790/**
791
792@defgroup MXL5005S_DEPENDENCE MxL5005S dependence
793@ingroup MXL5005S_TUNER_MODULE
794
795MxL5005S dependence is the related functions for MxL5005S tuner module interface.
796One should not use MxL5005S dependence directly.
797
798*/
799/// @{
800
801
802
803
804
805/**
806
807@brief Set I2C bridge module tuner arguments.
808
809MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments.
810
811
812@param [in] pTuner The tuner module pointer
813
814
815@see BuildMxl5005sModule()
816
817*/
818void
819mxl5005s_SetI2cBridgeModuleTunerArg(
820 TUNER_MODULE *pTuner
821 )
822{
823 I2C_BRIDGE_MODULE *pI2cBridge;
824
825
826
827 // Get I2C bridge module.
828 pI2cBridge = pTuner->pI2cBridge;
829
830 // Set I2C bridge module tuner arguments.
831 pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr;
832
833
834 return;
835}
836
837
838
839
840
841/// @}
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865// The following context is source code provided by MaxLinear.
866
867
868
869
870
871// MaxLinear source code - MXL5005_Initialize.cpp
872
873
874
875//#ifdef _MXL_HEADER
876//#include "stdafx.h"
877//#endif
878//#include "MXL5005_c.h"
879
880_u16 MXL5005_RegisterInit (Tuner_struct * Tuner)
881{
882 Tuner->TunerRegs_Num = TUNER_REGS_NUM ;
883// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
884
885 Tuner->TunerRegs[0].Reg_Num = 9 ;
886 Tuner->TunerRegs[0].Reg_Val = 0x40 ;
887
888 Tuner->TunerRegs[1].Reg_Num = 11 ;
889 Tuner->TunerRegs[1].Reg_Val = 0x19 ;
890
891 Tuner->TunerRegs[2].Reg_Num = 12 ;
892 Tuner->TunerRegs[2].Reg_Val = 0x60 ;
893
894 Tuner->TunerRegs[3].Reg_Num = 13 ;
895 Tuner->TunerRegs[3].Reg_Val = 0x00 ;
896
897 Tuner->TunerRegs[4].Reg_Num = 14 ;
898 Tuner->TunerRegs[4].Reg_Val = 0x00 ;
899
900 Tuner->TunerRegs[5].Reg_Num = 15 ;
901 Tuner->TunerRegs[5].Reg_Val = 0xC0 ;
902
903 Tuner->TunerRegs[6].Reg_Num = 16 ;
904 Tuner->TunerRegs[6].Reg_Val = 0x00 ;
905
906 Tuner->TunerRegs[7].Reg_Num = 17 ;
907 Tuner->TunerRegs[7].Reg_Val = 0x00 ;
908
909 Tuner->TunerRegs[8].Reg_Num = 18 ;
910 Tuner->TunerRegs[8].Reg_Val = 0x00 ;
911
912 Tuner->TunerRegs[9].Reg_Num = 19 ;
913 Tuner->TunerRegs[9].Reg_Val = 0x34 ;
914
915 Tuner->TunerRegs[10].Reg_Num = 21 ;
916 Tuner->TunerRegs[10].Reg_Val = 0x00 ;
917
918 Tuner->TunerRegs[11].Reg_Num = 22 ;
919 Tuner->TunerRegs[11].Reg_Val = 0x6B ;
920
921 Tuner->TunerRegs[12].Reg_Num = 23 ;
922 Tuner->TunerRegs[12].Reg_Val = 0x35 ;
923
924 Tuner->TunerRegs[13].Reg_Num = 24 ;
925 Tuner->TunerRegs[13].Reg_Val = 0x70 ;
926
927 Tuner->TunerRegs[14].Reg_Num = 25 ;
928 Tuner->TunerRegs[14].Reg_Val = 0x3E ;
929
930 Tuner->TunerRegs[15].Reg_Num = 26 ;
931 Tuner->TunerRegs[15].Reg_Val = 0x82 ;
932
933 Tuner->TunerRegs[16].Reg_Num = 31 ;
934 Tuner->TunerRegs[16].Reg_Val = 0x00 ;
935
936 Tuner->TunerRegs[17].Reg_Num = 32 ;
937 Tuner->TunerRegs[17].Reg_Val = 0x40 ;
938
939 Tuner->TunerRegs[18].Reg_Num = 33 ;
940 Tuner->TunerRegs[18].Reg_Val = 0x53 ;
941
942 Tuner->TunerRegs[19].Reg_Num = 34 ;
943 Tuner->TunerRegs[19].Reg_Val = 0x81 ;
944
945 Tuner->TunerRegs[20].Reg_Num = 35 ;
946 Tuner->TunerRegs[20].Reg_Val = 0xC9 ;
947
948 Tuner->TunerRegs[21].Reg_Num = 36 ;
949 Tuner->TunerRegs[21].Reg_Val = 0x01 ;
950
951 Tuner->TunerRegs[22].Reg_Num = 37 ;
952 Tuner->TunerRegs[22].Reg_Val = 0x00 ;
953
954 Tuner->TunerRegs[23].Reg_Num = 41 ;
955 Tuner->TunerRegs[23].Reg_Val = 0x00 ;
956
957 Tuner->TunerRegs[24].Reg_Num = 42 ;
958 Tuner->TunerRegs[24].Reg_Val = 0xF8 ;
959
960 Tuner->TunerRegs[25].Reg_Num = 43 ;
961 Tuner->TunerRegs[25].Reg_Val = 0x43 ;
962
963 Tuner->TunerRegs[26].Reg_Num = 44 ;
964 Tuner->TunerRegs[26].Reg_Val = 0x20 ;
965
966 Tuner->TunerRegs[27].Reg_Num = 45 ;
967 Tuner->TunerRegs[27].Reg_Val = 0x80 ;
968
969 Tuner->TunerRegs[28].Reg_Num = 46 ;
970 Tuner->TunerRegs[28].Reg_Val = 0x88 ;
971
972 Tuner->TunerRegs[29].Reg_Num = 47 ;
973 Tuner->TunerRegs[29].Reg_Val = 0x86 ;
974
975 Tuner->TunerRegs[30].Reg_Num = 48 ;
976 Tuner->TunerRegs[30].Reg_Val = 0x00 ;
977
978 Tuner->TunerRegs[31].Reg_Num = 49 ;
979 Tuner->TunerRegs[31].Reg_Val = 0x00 ;
980
981 Tuner->TunerRegs[32].Reg_Num = 53 ;
982 Tuner->TunerRegs[32].Reg_Val = 0x94 ;
983
984 Tuner->TunerRegs[33].Reg_Num = 54 ;
985 Tuner->TunerRegs[33].Reg_Val = 0xFA ;
986
987 Tuner->TunerRegs[34].Reg_Num = 55 ;
988 Tuner->TunerRegs[34].Reg_Val = 0x92 ;
989
990 Tuner->TunerRegs[35].Reg_Num = 56 ;
991 Tuner->TunerRegs[35].Reg_Val = 0x80 ;
992
993 Tuner->TunerRegs[36].Reg_Num = 57 ;
994 Tuner->TunerRegs[36].Reg_Val = 0x41 ;
995
996 Tuner->TunerRegs[37].Reg_Num = 58 ;
997 Tuner->TunerRegs[37].Reg_Val = 0xDB ;
998
999 Tuner->TunerRegs[38].Reg_Num = 59 ;
1000 Tuner->TunerRegs[38].Reg_Val = 0x00 ;
1001
1002 Tuner->TunerRegs[39].Reg_Num = 60 ;
1003 Tuner->TunerRegs[39].Reg_Val = 0x00 ;
1004
1005 Tuner->TunerRegs[40].Reg_Num = 61 ;
1006 Tuner->TunerRegs[40].Reg_Val = 0x00 ;
1007
1008 Tuner->TunerRegs[41].Reg_Num = 62 ;
1009 Tuner->TunerRegs[41].Reg_Val = 0x00 ;
1010
1011 Tuner->TunerRegs[42].Reg_Num = 65 ;
1012 Tuner->TunerRegs[42].Reg_Val = 0xF8 ;
1013
1014 Tuner->TunerRegs[43].Reg_Num = 66 ;
1015 Tuner->TunerRegs[43].Reg_Val = 0xE4 ;
1016
1017 Tuner->TunerRegs[44].Reg_Num = 67 ;
1018 Tuner->TunerRegs[44].Reg_Val = 0x90 ;
1019
1020 Tuner->TunerRegs[45].Reg_Num = 68 ;
1021 Tuner->TunerRegs[45].Reg_Val = 0xC0 ;
1022
1023 Tuner->TunerRegs[46].Reg_Num = 69 ;
1024 Tuner->TunerRegs[46].Reg_Val = 0x01 ;
1025
1026 Tuner->TunerRegs[47].Reg_Num = 70 ;
1027 Tuner->TunerRegs[47].Reg_Val = 0x50 ;
1028
1029 Tuner->TunerRegs[48].Reg_Num = 71 ;
1030 Tuner->TunerRegs[48].Reg_Val = 0x06 ;
1031
1032 Tuner->TunerRegs[49].Reg_Num = 72 ;
1033 Tuner->TunerRegs[49].Reg_Val = 0x00 ;
1034
1035 Tuner->TunerRegs[50].Reg_Num = 73 ;
1036 Tuner->TunerRegs[50].Reg_Val = 0x20 ;
1037
1038 Tuner->TunerRegs[51].Reg_Num = 76 ;
1039 Tuner->TunerRegs[51].Reg_Val = 0xBB ;
1040
1041 Tuner->TunerRegs[52].Reg_Num = 77 ;
1042 Tuner->TunerRegs[52].Reg_Val = 0x13 ;
1043
1044 Tuner->TunerRegs[53].Reg_Num = 81 ;
1045 Tuner->TunerRegs[53].Reg_Val = 0x04 ;
1046
1047 Tuner->TunerRegs[54].Reg_Num = 82 ;
1048 Tuner->TunerRegs[54].Reg_Val = 0x75 ;
1049
1050 Tuner->TunerRegs[55].Reg_Num = 83 ;
1051 Tuner->TunerRegs[55].Reg_Val = 0x00 ;
1052
1053 Tuner->TunerRegs[56].Reg_Num = 84 ;
1054 Tuner->TunerRegs[56].Reg_Val = 0x00 ;
1055
1056 Tuner->TunerRegs[57].Reg_Num = 85 ;
1057 Tuner->TunerRegs[57].Reg_Val = 0x00 ;
1058
1059 Tuner->TunerRegs[58].Reg_Num = 91 ;
1060 Tuner->TunerRegs[58].Reg_Val = 0x70 ;
1061
1062 Tuner->TunerRegs[59].Reg_Num = 92 ;
1063 Tuner->TunerRegs[59].Reg_Val = 0x00 ;
1064
1065 Tuner->TunerRegs[60].Reg_Num = 93 ;
1066 Tuner->TunerRegs[60].Reg_Val = 0x00 ;
1067
1068 Tuner->TunerRegs[61].Reg_Num = 94 ;
1069 Tuner->TunerRegs[61].Reg_Val = 0x00 ;
1070
1071 Tuner->TunerRegs[62].Reg_Num = 95 ;
1072 Tuner->TunerRegs[62].Reg_Val = 0x0C ;
1073
1074 Tuner->TunerRegs[63].Reg_Num = 96 ;
1075 Tuner->TunerRegs[63].Reg_Val = 0x00 ;
1076
1077 Tuner->TunerRegs[64].Reg_Num = 97 ;
1078 Tuner->TunerRegs[64].Reg_Val = 0x00 ;
1079
1080 Tuner->TunerRegs[65].Reg_Num = 98 ;
1081 Tuner->TunerRegs[65].Reg_Val = 0xE2 ;
1082
1083 Tuner->TunerRegs[66].Reg_Num = 99 ;
1084 Tuner->TunerRegs[66].Reg_Val = 0x00 ;
1085
1086 Tuner->TunerRegs[67].Reg_Num = 100 ;
1087 Tuner->TunerRegs[67].Reg_Val = 0x00 ;
1088
1089 Tuner->TunerRegs[68].Reg_Num = 101 ;
1090 Tuner->TunerRegs[68].Reg_Val = 0x12 ;
1091
1092 Tuner->TunerRegs[69].Reg_Num = 102 ;
1093 Tuner->TunerRegs[69].Reg_Val = 0x80 ;
1094
1095 Tuner->TunerRegs[70].Reg_Num = 103 ;
1096 Tuner->TunerRegs[70].Reg_Val = 0x32 ;
1097
1098 Tuner->TunerRegs[71].Reg_Num = 104 ;
1099 Tuner->TunerRegs[71].Reg_Val = 0xB4 ;
1100
1101 Tuner->TunerRegs[72].Reg_Num = 105 ;
1102 Tuner->TunerRegs[72].Reg_Val = 0x60 ;
1103
1104 Tuner->TunerRegs[73].Reg_Num = 106 ;
1105 Tuner->TunerRegs[73].Reg_Val = 0x83 ;
1106
1107 Tuner->TunerRegs[74].Reg_Num = 107 ;
1108 Tuner->TunerRegs[74].Reg_Val = 0x84 ;
1109
1110 Tuner->TunerRegs[75].Reg_Num = 108 ;
1111 Tuner->TunerRegs[75].Reg_Val = 0x9C ;
1112
1113 Tuner->TunerRegs[76].Reg_Num = 109 ;
1114 Tuner->TunerRegs[76].Reg_Val = 0x02 ;
1115
1116 Tuner->TunerRegs[77].Reg_Num = 110 ;
1117 Tuner->TunerRegs[77].Reg_Val = 0x81 ;
1118
1119 Tuner->TunerRegs[78].Reg_Num = 111 ;
1120 Tuner->TunerRegs[78].Reg_Val = 0xC0 ;
1121
1122 Tuner->TunerRegs[79].Reg_Num = 112 ;
1123 Tuner->TunerRegs[79].Reg_Val = 0x10 ;
1124
1125 Tuner->TunerRegs[80].Reg_Num = 131 ;
1126 Tuner->TunerRegs[80].Reg_Val = 0x8A ;
1127
1128 Tuner->TunerRegs[81].Reg_Num = 132 ;
1129 Tuner->TunerRegs[81].Reg_Val = 0x10 ;
1130
1131 Tuner->TunerRegs[82].Reg_Num = 133 ;
1132 Tuner->TunerRegs[82].Reg_Val = 0x24 ;
1133
1134 Tuner->TunerRegs[83].Reg_Num = 134 ;
1135 Tuner->TunerRegs[83].Reg_Val = 0x00 ;
1136
1137 Tuner->TunerRegs[84].Reg_Num = 135 ;
1138 Tuner->TunerRegs[84].Reg_Val = 0x00 ;
1139
1140 Tuner->TunerRegs[85].Reg_Num = 136 ;
1141 Tuner->TunerRegs[85].Reg_Val = 0x7E ;
1142
1143 Tuner->TunerRegs[86].Reg_Num = 137 ;
1144 Tuner->TunerRegs[86].Reg_Val = 0x40 ;
1145
1146 Tuner->TunerRegs[87].Reg_Num = 138 ;
1147 Tuner->TunerRegs[87].Reg_Val = 0x38 ;
1148
1149 Tuner->TunerRegs[88].Reg_Num = 146 ;
1150 Tuner->TunerRegs[88].Reg_Val = 0xF6 ;
1151
1152 Tuner->TunerRegs[89].Reg_Num = 147 ;
1153 Tuner->TunerRegs[89].Reg_Val = 0x1A ;
1154
1155 Tuner->TunerRegs[90].Reg_Num = 148 ;
1156 Tuner->TunerRegs[90].Reg_Val = 0x62 ;
1157
1158 Tuner->TunerRegs[91].Reg_Num = 149 ;
1159 Tuner->TunerRegs[91].Reg_Val = 0x33 ;
1160
1161 Tuner->TunerRegs[92].Reg_Num = 150 ;
1162 Tuner->TunerRegs[92].Reg_Val = 0x80 ;
1163
1164 Tuner->TunerRegs[93].Reg_Num = 156 ;
1165 Tuner->TunerRegs[93].Reg_Val = 0x56 ;
1166
1167 Tuner->TunerRegs[94].Reg_Num = 157 ;
1168 Tuner->TunerRegs[94].Reg_Val = 0x17 ;
1169
1170 Tuner->TunerRegs[95].Reg_Num = 158 ;
1171 Tuner->TunerRegs[95].Reg_Val = 0xA9 ;
1172
1173 Tuner->TunerRegs[96].Reg_Num = 159 ;
1174 Tuner->TunerRegs[96].Reg_Val = 0x00 ;
1175
1176 Tuner->TunerRegs[97].Reg_Num = 160 ;
1177 Tuner->TunerRegs[97].Reg_Val = 0x00 ;
1178
1179 Tuner->TunerRegs[98].Reg_Num = 161 ;
1180 Tuner->TunerRegs[98].Reg_Val = 0x00 ;
1181
1182 Tuner->TunerRegs[99].Reg_Num = 162 ;
1183 Tuner->TunerRegs[99].Reg_Val = 0x40 ;
1184
1185 Tuner->TunerRegs[100].Reg_Num = 166 ;
1186 Tuner->TunerRegs[100].Reg_Val = 0xAE ;
1187
1188 Tuner->TunerRegs[101].Reg_Num = 167 ;
1189 Tuner->TunerRegs[101].Reg_Val = 0x1B ;
1190
1191 Tuner->TunerRegs[102].Reg_Num = 168 ;
1192 Tuner->TunerRegs[102].Reg_Val = 0xF2 ;
1193
1194 Tuner->TunerRegs[103].Reg_Num = 195 ;
1195 Tuner->TunerRegs[103].Reg_Val = 0x00 ;
1196
1197 return 0 ;
1198}
1199
1200_u16 MXL5005_ControlInit (Tuner_struct *Tuner)
1201{
1202 Tuner->Init_Ctrl_Num = INITCTRL_NUM ;
1203
1204 Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
1205 Tuner->Init_Ctrl[0].size = 1 ;
1206 Tuner->Init_Ctrl[0].addr[0] = 73;
1207 Tuner->Init_Ctrl[0].bit[0] = 7;
1208 Tuner->Init_Ctrl[0].val[0] = 0;
1209
1210 Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
1211 Tuner->Init_Ctrl[1].size = 1 ;
1212 Tuner->Init_Ctrl[1].addr[0] = 53;
1213 Tuner->Init_Ctrl[1].bit[0] = 2;
1214 Tuner->Init_Ctrl[1].val[0] = 1;
1215
1216 Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
1217 Tuner->Init_Ctrl[2].size = 2 ;
1218 Tuner->Init_Ctrl[2].addr[0] = 53;
1219 Tuner->Init_Ctrl[2].bit[0] = 1;
1220 Tuner->Init_Ctrl[2].val[0] = 0;
1221 Tuner->Init_Ctrl[2].addr[1] = 57;
1222 Tuner->Init_Ctrl[2].bit[1] = 0;
1223 Tuner->Init_Ctrl[2].val[1] = 1;
1224
1225 Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
1226 Tuner->Init_Ctrl[3].size = 1 ;
1227 Tuner->Init_Ctrl[3].addr[0] = 53;
1228 Tuner->Init_Ctrl[3].bit[0] = 0;
1229 Tuner->Init_Ctrl[3].val[0] = 0;
1230
1231 Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
1232 Tuner->Init_Ctrl[4].size = 3 ;
1233 Tuner->Init_Ctrl[4].addr[0] = 53;
1234 Tuner->Init_Ctrl[4].bit[0] = 5;
1235 Tuner->Init_Ctrl[4].val[0] = 0;
1236 Tuner->Init_Ctrl[4].addr[1] = 53;
1237 Tuner->Init_Ctrl[4].bit[1] = 6;
1238 Tuner->Init_Ctrl[4].val[1] = 0;
1239 Tuner->Init_Ctrl[4].addr[2] = 53;
1240 Tuner->Init_Ctrl[4].bit[2] = 7;
1241 Tuner->Init_Ctrl[4].val[2] = 1;
1242
1243 Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
1244 Tuner->Init_Ctrl[5].size = 1 ;
1245 Tuner->Init_Ctrl[5].addr[0] = 59;
1246 Tuner->Init_Ctrl[5].bit[0] = 0;
1247 Tuner->Init_Ctrl[5].val[0] = 0;
1248
1249 Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
1250 Tuner->Init_Ctrl[6].size = 2 ;
1251 Tuner->Init_Ctrl[6].addr[0] = 53;
1252 Tuner->Init_Ctrl[6].bit[0] = 3;
1253 Tuner->Init_Ctrl[6].val[0] = 0;
1254 Tuner->Init_Ctrl[6].addr[1] = 53;
1255 Tuner->Init_Ctrl[6].bit[1] = 4;
1256 Tuner->Init_Ctrl[6].val[1] = 1;
1257
1258 Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
1259 Tuner->Init_Ctrl[7].size = 4 ;
1260 Tuner->Init_Ctrl[7].addr[0] = 22;
1261 Tuner->Init_Ctrl[7].bit[0] = 4;
1262 Tuner->Init_Ctrl[7].val[0] = 0;
1263 Tuner->Init_Ctrl[7].addr[1] = 22;
1264 Tuner->Init_Ctrl[7].bit[1] = 5;
1265 Tuner->Init_Ctrl[7].val[1] = 1;
1266 Tuner->Init_Ctrl[7].addr[2] = 22;
1267 Tuner->Init_Ctrl[7].bit[2] = 6;
1268 Tuner->Init_Ctrl[7].val[2] = 1;
1269 Tuner->Init_Ctrl[7].addr[3] = 22;
1270 Tuner->Init_Ctrl[7].bit[3] = 7;
1271 Tuner->Init_Ctrl[7].val[3] = 0;
1272
1273 Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
1274 Tuner->Init_Ctrl[8].size = 1 ;
1275 Tuner->Init_Ctrl[8].addr[0] = 22;
1276 Tuner->Init_Ctrl[8].bit[0] = 2;
1277 Tuner->Init_Ctrl[8].val[0] = 0;
1278
1279 Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
1280 Tuner->Init_Ctrl[9].size = 4 ;
1281 Tuner->Init_Ctrl[9].addr[0] = 76;
1282 Tuner->Init_Ctrl[9].bit[0] = 0;
1283 Tuner->Init_Ctrl[9].val[0] = 1;
1284 Tuner->Init_Ctrl[9].addr[1] = 76;
1285 Tuner->Init_Ctrl[9].bit[1] = 1;
1286 Tuner->Init_Ctrl[9].val[1] = 1;
1287 Tuner->Init_Ctrl[9].addr[2] = 76;
1288 Tuner->Init_Ctrl[9].bit[2] = 2;
1289 Tuner->Init_Ctrl[9].val[2] = 0;
1290 Tuner->Init_Ctrl[9].addr[3] = 76;
1291 Tuner->Init_Ctrl[9].bit[3] = 3;
1292 Tuner->Init_Ctrl[9].val[3] = 1;
1293
1294 Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
1295 Tuner->Init_Ctrl[10].size = 4 ;
1296 Tuner->Init_Ctrl[10].addr[0] = 76;
1297 Tuner->Init_Ctrl[10].bit[0] = 4;
1298 Tuner->Init_Ctrl[10].val[0] = 1;
1299 Tuner->Init_Ctrl[10].addr[1] = 76;
1300 Tuner->Init_Ctrl[10].bit[1] = 5;
1301 Tuner->Init_Ctrl[10].val[1] = 1;
1302 Tuner->Init_Ctrl[10].addr[2] = 76;
1303 Tuner->Init_Ctrl[10].bit[2] = 6;
1304 Tuner->Init_Ctrl[10].val[2] = 0;
1305 Tuner->Init_Ctrl[10].addr[3] = 76;
1306 Tuner->Init_Ctrl[10].bit[3] = 7;
1307 Tuner->Init_Ctrl[10].val[3] = 1;
1308
1309 Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
1310 Tuner->Init_Ctrl[11].size = 5 ;
1311 Tuner->Init_Ctrl[11].addr[0] = 43;
1312 Tuner->Init_Ctrl[11].bit[0] = 3;
1313 Tuner->Init_Ctrl[11].val[0] = 0;
1314 Tuner->Init_Ctrl[11].addr[1] = 43;
1315 Tuner->Init_Ctrl[11].bit[1] = 4;
1316 Tuner->Init_Ctrl[11].val[1] = 0;
1317 Tuner->Init_Ctrl[11].addr[2] = 43;
1318 Tuner->Init_Ctrl[11].bit[2] = 5;
1319 Tuner->Init_Ctrl[11].val[2] = 0;
1320 Tuner->Init_Ctrl[11].addr[3] = 43;
1321 Tuner->Init_Ctrl[11].bit[3] = 6;
1322 Tuner->Init_Ctrl[11].val[3] = 1;
1323 Tuner->Init_Ctrl[11].addr[4] = 43;
1324 Tuner->Init_Ctrl[11].bit[4] = 7;
1325 Tuner->Init_Ctrl[11].val[4] = 0;
1326
1327 Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
1328 Tuner->Init_Ctrl[12].size = 6 ;
1329 Tuner->Init_Ctrl[12].addr[0] = 44;
1330 Tuner->Init_Ctrl[12].bit[0] = 2;
1331 Tuner->Init_Ctrl[12].val[0] = 0;
1332 Tuner->Init_Ctrl[12].addr[1] = 44;
1333 Tuner->Init_Ctrl[12].bit[1] = 3;
1334 Tuner->Init_Ctrl[12].val[1] = 0;
1335 Tuner->Init_Ctrl[12].addr[2] = 44;
1336 Tuner->Init_Ctrl[12].bit[2] = 4;
1337 Tuner->Init_Ctrl[12].val[2] = 0;
1338 Tuner->Init_Ctrl[12].addr[3] = 44;
1339 Tuner->Init_Ctrl[12].bit[3] = 5;
1340 Tuner->Init_Ctrl[12].val[3] = 1;
1341 Tuner->Init_Ctrl[12].addr[4] = 44;
1342 Tuner->Init_Ctrl[12].bit[4] = 6;
1343 Tuner->Init_Ctrl[12].val[4] = 0;
1344 Tuner->Init_Ctrl[12].addr[5] = 44;
1345 Tuner->Init_Ctrl[12].bit[5] = 7;
1346 Tuner->Init_Ctrl[12].val[5] = 0;
1347
1348 Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
1349 Tuner->Init_Ctrl[13].size = 7 ;
1350 Tuner->Init_Ctrl[13].addr[0] = 11;
1351 Tuner->Init_Ctrl[13].bit[0] = 0;
1352 Tuner->Init_Ctrl[13].val[0] = 1;
1353 Tuner->Init_Ctrl[13].addr[1] = 11;
1354 Tuner->Init_Ctrl[13].bit[1] = 1;
1355 Tuner->Init_Ctrl[13].val[1] = 0;
1356 Tuner->Init_Ctrl[13].addr[2] = 11;
1357 Tuner->Init_Ctrl[13].bit[2] = 2;
1358 Tuner->Init_Ctrl[13].val[2] = 0;
1359 Tuner->Init_Ctrl[13].addr[3] = 11;
1360 Tuner->Init_Ctrl[13].bit[3] = 3;
1361 Tuner->Init_Ctrl[13].val[3] = 1;
1362 Tuner->Init_Ctrl[13].addr[4] = 11;
1363 Tuner->Init_Ctrl[13].bit[4] = 4;
1364 Tuner->Init_Ctrl[13].val[4] = 1;
1365 Tuner->Init_Ctrl[13].addr[5] = 11;
1366 Tuner->Init_Ctrl[13].bit[5] = 5;
1367 Tuner->Init_Ctrl[13].val[5] = 0;
1368 Tuner->Init_Ctrl[13].addr[6] = 11;
1369 Tuner->Init_Ctrl[13].bit[6] = 6;
1370 Tuner->Init_Ctrl[13].val[6] = 0;
1371
1372 Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
1373 Tuner->Init_Ctrl[14].size = 16 ;
1374 Tuner->Init_Ctrl[14].addr[0] = 13;
1375 Tuner->Init_Ctrl[14].bit[0] = 0;
1376 Tuner->Init_Ctrl[14].val[0] = 0;
1377 Tuner->Init_Ctrl[14].addr[1] = 13;
1378 Tuner->Init_Ctrl[14].bit[1] = 1;
1379 Tuner->Init_Ctrl[14].val[1] = 0;
1380 Tuner->Init_Ctrl[14].addr[2] = 13;
1381 Tuner->Init_Ctrl[14].bit[2] = 2;
1382 Tuner->Init_Ctrl[14].val[2] = 0;
1383 Tuner->Init_Ctrl[14].addr[3] = 13;
1384 Tuner->Init_Ctrl[14].bit[3] = 3;
1385 Tuner->Init_Ctrl[14].val[3] = 0;
1386 Tuner->Init_Ctrl[14].addr[4] = 13;
1387 Tuner->Init_Ctrl[14].bit[4] = 4;
1388 Tuner->Init_Ctrl[14].val[4] = 0;
1389 Tuner->Init_Ctrl[14].addr[5] = 13;
1390 Tuner->Init_Ctrl[14].bit[5] = 5;
1391 Tuner->Init_Ctrl[14].val[5] = 0;
1392 Tuner->Init_Ctrl[14].addr[6] = 13;
1393 Tuner->Init_Ctrl[14].bit[6] = 6;
1394 Tuner->Init_Ctrl[14].val[6] = 0;
1395 Tuner->Init_Ctrl[14].addr[7] = 13;
1396 Tuner->Init_Ctrl[14].bit[7] = 7;
1397 Tuner->Init_Ctrl[14].val[7] = 0;
1398 Tuner->Init_Ctrl[14].addr[8] = 12;
1399 Tuner->Init_Ctrl[14].bit[8] = 0;
1400 Tuner->Init_Ctrl[14].val[8] = 0;
1401 Tuner->Init_Ctrl[14].addr[9] = 12;
1402 Tuner->Init_Ctrl[14].bit[9] = 1;
1403 Tuner->Init_Ctrl[14].val[9] = 0;
1404 Tuner->Init_Ctrl[14].addr[10] = 12;
1405 Tuner->Init_Ctrl[14].bit[10] = 2;
1406 Tuner->Init_Ctrl[14].val[10] = 0;
1407 Tuner->Init_Ctrl[14].addr[11] = 12;
1408 Tuner->Init_Ctrl[14].bit[11] = 3;
1409 Tuner->Init_Ctrl[14].val[11] = 0;
1410 Tuner->Init_Ctrl[14].addr[12] = 12;
1411 Tuner->Init_Ctrl[14].bit[12] = 4;
1412 Tuner->Init_Ctrl[14].val[12] = 0;
1413 Tuner->Init_Ctrl[14].addr[13] = 12;
1414 Tuner->Init_Ctrl[14].bit[13] = 5;
1415 Tuner->Init_Ctrl[14].val[13] = 1;
1416 Tuner->Init_Ctrl[14].addr[14] = 12;
1417 Tuner->Init_Ctrl[14].bit[14] = 6;
1418 Tuner->Init_Ctrl[14].val[14] = 1;
1419 Tuner->Init_Ctrl[14].addr[15] = 12;
1420 Tuner->Init_Ctrl[14].bit[15] = 7;
1421 Tuner->Init_Ctrl[14].val[15] = 0;
1422
1423 Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
1424 Tuner->Init_Ctrl[15].size = 3 ;
1425 Tuner->Init_Ctrl[15].addr[0] = 147;
1426 Tuner->Init_Ctrl[15].bit[0] = 2;
1427 Tuner->Init_Ctrl[15].val[0] = 0;
1428 Tuner->Init_Ctrl[15].addr[1] = 147;
1429 Tuner->Init_Ctrl[15].bit[1] = 3;
1430 Tuner->Init_Ctrl[15].val[1] = 1;
1431 Tuner->Init_Ctrl[15].addr[2] = 147;
1432 Tuner->Init_Ctrl[15].bit[2] = 4;
1433 Tuner->Init_Ctrl[15].val[2] = 1;
1434
1435 Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
1436 Tuner->Init_Ctrl[16].size = 2 ;
1437 Tuner->Init_Ctrl[16].addr[0] = 147;
1438 Tuner->Init_Ctrl[16].bit[0] = 0;
1439 Tuner->Init_Ctrl[16].val[0] = 0;
1440 Tuner->Init_Ctrl[16].addr[1] = 147;
1441 Tuner->Init_Ctrl[16].bit[1] = 1;
1442 Tuner->Init_Ctrl[16].val[1] = 1;
1443
1444 Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
1445 Tuner->Init_Ctrl[17].size = 1 ;
1446 Tuner->Init_Ctrl[17].addr[0] = 147;
1447 Tuner->Init_Ctrl[17].bit[0] = 7;
1448 Tuner->Init_Ctrl[17].val[0] = 0;
1449
1450 Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ;
1451 Tuner->Init_Ctrl[18].size = 1 ;
1452 Tuner->Init_Ctrl[18].addr[0] = 147;
1453 Tuner->Init_Ctrl[18].bit[0] = 6;
1454 Tuner->Init_Ctrl[18].val[0] = 0;
1455
1456 Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
1457 Tuner->Init_Ctrl[19].size = 1 ;
1458 Tuner->Init_Ctrl[19].addr[0] = 156;
1459 Tuner->Init_Ctrl[19].bit[0] = 0;
1460 Tuner->Init_Ctrl[19].val[0] = 0;
1461
1462 Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
1463 Tuner->Init_Ctrl[20].size = 1 ;
1464 Tuner->Init_Ctrl[20].addr[0] = 147;
1465 Tuner->Init_Ctrl[20].bit[0] = 5;
1466 Tuner->Init_Ctrl[20].val[0] = 0;
1467
1468 Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
1469 Tuner->Init_Ctrl[21].size = 1 ;
1470 Tuner->Init_Ctrl[21].addr[0] = 137;
1471 Tuner->Init_Ctrl[21].bit[0] = 4;
1472 Tuner->Init_Ctrl[21].val[0] = 0;
1473
1474 Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
1475 Tuner->Init_Ctrl[22].size = 1 ;
1476 Tuner->Init_Ctrl[22].addr[0] = 137;
1477 Tuner->Init_Ctrl[22].bit[0] = 7;
1478 Tuner->Init_Ctrl[22].val[0] = 0;
1479
1480 Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1481 Tuner->Init_Ctrl[23].size = 1 ;
1482 Tuner->Init_Ctrl[23].addr[0] = 91;
1483 Tuner->Init_Ctrl[23].bit[0] = 5;
1484 Tuner->Init_Ctrl[23].val[0] = 1;
1485
1486 Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1487 Tuner->Init_Ctrl[24].size = 1 ;
1488 Tuner->Init_Ctrl[24].addr[0] = 43;
1489 Tuner->Init_Ctrl[24].bit[0] = 0;
1490 Tuner->Init_Ctrl[24].val[0] = 1;
1491
1492 Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1493 Tuner->Init_Ctrl[25].size = 2 ;
1494 Tuner->Init_Ctrl[25].addr[0] = 22;
1495 Tuner->Init_Ctrl[25].bit[0] = 0;
1496 Tuner->Init_Ctrl[25].val[0] = 1;
1497 Tuner->Init_Ctrl[25].addr[1] = 22;
1498 Tuner->Init_Ctrl[25].bit[1] = 1;
1499 Tuner->Init_Ctrl[25].val[1] = 1;
1500
1501 Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1502 Tuner->Init_Ctrl[26].size = 1 ;
1503 Tuner->Init_Ctrl[26].addr[0] = 134;
1504 Tuner->Init_Ctrl[26].bit[0] = 2;
1505 Tuner->Init_Ctrl[26].val[0] = 0;
1506
1507 Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1508 Tuner->Init_Ctrl[27].size = 1 ;
1509 Tuner->Init_Ctrl[27].addr[0] = 137;
1510 Tuner->Init_Ctrl[27].bit[0] = 3;
1511 Tuner->Init_Ctrl[27].val[0] = 0;
1512
1513 Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1514 Tuner->Init_Ctrl[28].size = 1 ;
1515 Tuner->Init_Ctrl[28].addr[0] = 77;
1516 Tuner->Init_Ctrl[28].bit[0] = 7;
1517 Tuner->Init_Ctrl[28].val[0] = 0;
1518
1519 Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1520 Tuner->Init_Ctrl[29].size = 1 ;
1521 Tuner->Init_Ctrl[29].addr[0] = 166;
1522 Tuner->Init_Ctrl[29].bit[0] = 7;
1523 Tuner->Init_Ctrl[29].val[0] = 1;
1524
1525 Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1526 Tuner->Init_Ctrl[30].size = 3 ;
1527 Tuner->Init_Ctrl[30].addr[0] = 166;
1528 Tuner->Init_Ctrl[30].bit[0] = 0;
1529 Tuner->Init_Ctrl[30].val[0] = 0;
1530 Tuner->Init_Ctrl[30].addr[1] = 166;
1531 Tuner->Init_Ctrl[30].bit[1] = 1;
1532 Tuner->Init_Ctrl[30].val[1] = 1;
1533 Tuner->Init_Ctrl[30].addr[2] = 166;
1534 Tuner->Init_Ctrl[30].bit[2] = 2;
1535 Tuner->Init_Ctrl[30].val[2] = 1;
1536
1537 Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1538 Tuner->Init_Ctrl[31].size = 3 ;
1539 Tuner->Init_Ctrl[31].addr[0] = 166;
1540 Tuner->Init_Ctrl[31].bit[0] = 3;
1541 Tuner->Init_Ctrl[31].val[0] = 1;
1542 Tuner->Init_Ctrl[31].addr[1] = 166;
1543 Tuner->Init_Ctrl[31].bit[1] = 4;
1544 Tuner->Init_Ctrl[31].val[1] = 0;
1545 Tuner->Init_Ctrl[31].addr[2] = 166;
1546 Tuner->Init_Ctrl[31].bit[2] = 5;
1547 Tuner->Init_Ctrl[31].val[2] = 1;
1548
1549 Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1550 Tuner->Init_Ctrl[32].size = 3 ;
1551 Tuner->Init_Ctrl[32].addr[0] = 167;
1552 Tuner->Init_Ctrl[32].bit[0] = 0;
1553 Tuner->Init_Ctrl[32].val[0] = 1;
1554 Tuner->Init_Ctrl[32].addr[1] = 167;
1555 Tuner->Init_Ctrl[32].bit[1] = 1;
1556 Tuner->Init_Ctrl[32].val[1] = 1;
1557 Tuner->Init_Ctrl[32].addr[2] = 167;
1558 Tuner->Init_Ctrl[32].bit[2] = 2;
1559 Tuner->Init_Ctrl[32].val[2] = 0;
1560
1561 Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1562 Tuner->Init_Ctrl[33].size = 4 ;
1563 Tuner->Init_Ctrl[33].addr[0] = 168;
1564 Tuner->Init_Ctrl[33].bit[0] = 0;
1565 Tuner->Init_Ctrl[33].val[0] = 0;
1566 Tuner->Init_Ctrl[33].addr[1] = 168;
1567 Tuner->Init_Ctrl[33].bit[1] = 1;
1568 Tuner->Init_Ctrl[33].val[1] = 1;
1569 Tuner->Init_Ctrl[33].addr[2] = 168;
1570 Tuner->Init_Ctrl[33].bit[2] = 2;
1571 Tuner->Init_Ctrl[33].val[2] = 0;
1572 Tuner->Init_Ctrl[33].addr[3] = 168;
1573 Tuner->Init_Ctrl[33].bit[3] = 3;
1574 Tuner->Init_Ctrl[33].val[3] = 0;
1575
1576 Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1577 Tuner->Init_Ctrl[34].size = 4 ;
1578 Tuner->Init_Ctrl[34].addr[0] = 168;
1579 Tuner->Init_Ctrl[34].bit[0] = 4;
1580 Tuner->Init_Ctrl[34].val[0] = 1;
1581 Tuner->Init_Ctrl[34].addr[1] = 168;
1582 Tuner->Init_Ctrl[34].bit[1] = 5;
1583 Tuner->Init_Ctrl[34].val[1] = 1;
1584 Tuner->Init_Ctrl[34].addr[2] = 168;
1585 Tuner->Init_Ctrl[34].bit[2] = 6;
1586 Tuner->Init_Ctrl[34].val[2] = 1;
1587 Tuner->Init_Ctrl[34].addr[3] = 168;
1588 Tuner->Init_Ctrl[34].bit[3] = 7;
1589 Tuner->Init_Ctrl[34].val[3] = 1;
1590
1591 Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1592 Tuner->Init_Ctrl[35].size = 1 ;
1593 Tuner->Init_Ctrl[35].addr[0] = 135;
1594 Tuner->Init_Ctrl[35].bit[0] = 0;
1595 Tuner->Init_Ctrl[35].val[0] = 0;
1596
1597 Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1598 Tuner->Init_Ctrl[36].size = 1 ;
1599 Tuner->Init_Ctrl[36].addr[0] = 56;
1600 Tuner->Init_Ctrl[36].bit[0] = 3;
1601 Tuner->Init_Ctrl[36].val[0] = 0;
1602
1603 Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1604 Tuner->Init_Ctrl[37].size = 7 ;
1605 Tuner->Init_Ctrl[37].addr[0] = 59;
1606 Tuner->Init_Ctrl[37].bit[0] = 1;
1607 Tuner->Init_Ctrl[37].val[0] = 0;
1608 Tuner->Init_Ctrl[37].addr[1] = 59;
1609 Tuner->Init_Ctrl[37].bit[1] = 2;
1610 Tuner->Init_Ctrl[37].val[1] = 0;
1611 Tuner->Init_Ctrl[37].addr[2] = 59;
1612 Tuner->Init_Ctrl[37].bit[2] = 3;
1613 Tuner->Init_Ctrl[37].val[2] = 0;
1614 Tuner->Init_Ctrl[37].addr[3] = 59;
1615 Tuner->Init_Ctrl[37].bit[3] = 4;
1616 Tuner->Init_Ctrl[37].val[3] = 0;
1617 Tuner->Init_Ctrl[37].addr[4] = 59;
1618 Tuner->Init_Ctrl[37].bit[4] = 5;
1619 Tuner->Init_Ctrl[37].val[4] = 0;
1620 Tuner->Init_Ctrl[37].addr[5] = 59;
1621 Tuner->Init_Ctrl[37].bit[5] = 6;
1622 Tuner->Init_Ctrl[37].val[5] = 0;
1623 Tuner->Init_Ctrl[37].addr[6] = 59;
1624 Tuner->Init_Ctrl[37].bit[6] = 7;
1625 Tuner->Init_Ctrl[37].val[6] = 0;
1626
1627 Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1628 Tuner->Init_Ctrl[38].size = 6 ;
1629 Tuner->Init_Ctrl[38].addr[0] = 32;
1630 Tuner->Init_Ctrl[38].bit[0] = 2;
1631 Tuner->Init_Ctrl[38].val[0] = 0;
1632 Tuner->Init_Ctrl[38].addr[1] = 32;
1633 Tuner->Init_Ctrl[38].bit[1] = 3;
1634 Tuner->Init_Ctrl[38].val[1] = 0;
1635 Tuner->Init_Ctrl[38].addr[2] = 32;
1636 Tuner->Init_Ctrl[38].bit[2] = 4;
1637 Tuner->Init_Ctrl[38].val[2] = 0;
1638 Tuner->Init_Ctrl[38].addr[3] = 32;
1639 Tuner->Init_Ctrl[38].bit[3] = 5;
1640 Tuner->Init_Ctrl[38].val[3] = 0;
1641 Tuner->Init_Ctrl[38].addr[4] = 32;
1642 Tuner->Init_Ctrl[38].bit[4] = 6;
1643 Tuner->Init_Ctrl[38].val[4] = 1;
1644 Tuner->Init_Ctrl[38].addr[5] = 32;
1645 Tuner->Init_Ctrl[38].bit[5] = 7;
1646 Tuner->Init_Ctrl[38].val[5] = 0;
1647
1648 Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1649 Tuner->Init_Ctrl[39].size = 1 ;
1650 Tuner->Init_Ctrl[39].addr[0] = 25;
1651 Tuner->Init_Ctrl[39].bit[0] = 3;
1652 Tuner->Init_Ctrl[39].val[0] = 1;
1653
1654
1655 Tuner->CH_Ctrl_Num = CHCTRL_NUM ;
1656
1657 Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1658 Tuner->CH_Ctrl[0].size = 2 ;
1659 Tuner->CH_Ctrl[0].addr[0] = 68;
1660 Tuner->CH_Ctrl[0].bit[0] = 6;
1661 Tuner->CH_Ctrl[0].val[0] = 1;
1662 Tuner->CH_Ctrl[0].addr[1] = 68;
1663 Tuner->CH_Ctrl[0].bit[1] = 7;
1664 Tuner->CH_Ctrl[0].val[1] = 1;
1665
1666 Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1667 Tuner->CH_Ctrl[1].size = 2 ;
1668 Tuner->CH_Ctrl[1].addr[0] = 70;
1669 Tuner->CH_Ctrl[1].bit[0] = 6;
1670 Tuner->CH_Ctrl[1].val[0] = 1;
1671 Tuner->CH_Ctrl[1].addr[1] = 70;
1672 Tuner->CH_Ctrl[1].bit[1] = 7;
1673 Tuner->CH_Ctrl[1].val[1] = 0;
1674
1675 Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1676 Tuner->CH_Ctrl[2].size = 9 ;
1677 Tuner->CH_Ctrl[2].addr[0] = 69;
1678 Tuner->CH_Ctrl[2].bit[0] = 5;
1679 Tuner->CH_Ctrl[2].val[0] = 0;
1680 Tuner->CH_Ctrl[2].addr[1] = 69;
1681 Tuner->CH_Ctrl[2].bit[1] = 6;
1682 Tuner->CH_Ctrl[2].val[1] = 0;
1683 Tuner->CH_Ctrl[2].addr[2] = 69;
1684 Tuner->CH_Ctrl[2].bit[2] = 7;
1685 Tuner->CH_Ctrl[2].val[2] = 0;
1686 Tuner->CH_Ctrl[2].addr[3] = 68;
1687 Tuner->CH_Ctrl[2].bit[3] = 0;
1688 Tuner->CH_Ctrl[2].val[3] = 0;
1689 Tuner->CH_Ctrl[2].addr[4] = 68;
1690 Tuner->CH_Ctrl[2].bit[4] = 1;
1691 Tuner->CH_Ctrl[2].val[4] = 0;
1692 Tuner->CH_Ctrl[2].addr[5] = 68;
1693 Tuner->CH_Ctrl[2].bit[5] = 2;
1694 Tuner->CH_Ctrl[2].val[5] = 0;
1695 Tuner->CH_Ctrl[2].addr[6] = 68;
1696 Tuner->CH_Ctrl[2].bit[6] = 3;
1697 Tuner->CH_Ctrl[2].val[6] = 0;
1698 Tuner->CH_Ctrl[2].addr[7] = 68;
1699 Tuner->CH_Ctrl[2].bit[7] = 4;
1700 Tuner->CH_Ctrl[2].val[7] = 0;
1701 Tuner->CH_Ctrl[2].addr[8] = 68;
1702 Tuner->CH_Ctrl[2].bit[8] = 5;
1703 Tuner->CH_Ctrl[2].val[8] = 0;
1704
1705 Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1706 Tuner->CH_Ctrl[3].size = 1 ;
1707 Tuner->CH_Ctrl[3].addr[0] = 70;
1708 Tuner->CH_Ctrl[3].bit[0] = 5;
1709 Tuner->CH_Ctrl[3].val[0] = 0;
1710
1711 Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1712 Tuner->CH_Ctrl[4].size = 3 ;
1713 Tuner->CH_Ctrl[4].addr[0] = 73;
1714 Tuner->CH_Ctrl[4].bit[0] = 4;
1715 Tuner->CH_Ctrl[4].val[0] = 0;
1716 Tuner->CH_Ctrl[4].addr[1] = 73;
1717 Tuner->CH_Ctrl[4].bit[1] = 5;
1718 Tuner->CH_Ctrl[4].val[1] = 1;
1719 Tuner->CH_Ctrl[4].addr[2] = 73;
1720 Tuner->CH_Ctrl[4].bit[2] = 6;
1721 Tuner->CH_Ctrl[4].val[2] = 0;
1722
1723 Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1724 Tuner->CH_Ctrl[5].size = 4 ;
1725 Tuner->CH_Ctrl[5].addr[0] = 70;
1726 Tuner->CH_Ctrl[5].bit[0] = 0;
1727 Tuner->CH_Ctrl[5].val[0] = 0;
1728 Tuner->CH_Ctrl[5].addr[1] = 70;
1729 Tuner->CH_Ctrl[5].bit[1] = 1;
1730 Tuner->CH_Ctrl[5].val[1] = 0;
1731 Tuner->CH_Ctrl[5].addr[2] = 70;
1732 Tuner->CH_Ctrl[5].bit[2] = 2;
1733 Tuner->CH_Ctrl[5].val[2] = 0;
1734 Tuner->CH_Ctrl[5].addr[3] = 70;
1735 Tuner->CH_Ctrl[5].bit[3] = 3;
1736 Tuner->CH_Ctrl[5].val[3] = 0;
1737
1738 Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1739 Tuner->CH_Ctrl[6].size = 1 ;
1740 Tuner->CH_Ctrl[6].addr[0] = 70;
1741 Tuner->CH_Ctrl[6].bit[0] = 4;
1742 Tuner->CH_Ctrl[6].val[0] = 1;
1743
1744 Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1745 Tuner->CH_Ctrl[7].size = 1 ;
1746 Tuner->CH_Ctrl[7].addr[0] = 111;
1747 Tuner->CH_Ctrl[7].bit[0] = 4;
1748 Tuner->CH_Ctrl[7].val[0] = 0;
1749
1750 Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1751 Tuner->CH_Ctrl[8].size = 1 ;
1752 Tuner->CH_Ctrl[8].addr[0] = 111;
1753 Tuner->CH_Ctrl[8].bit[0] = 7;
1754 Tuner->CH_Ctrl[8].val[0] = 1;
1755
1756 Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1757 Tuner->CH_Ctrl[9].size = 1 ;
1758 Tuner->CH_Ctrl[9].addr[0] = 111;
1759 Tuner->CH_Ctrl[9].bit[0] = 6;
1760 Tuner->CH_Ctrl[9].val[0] = 1;
1761
1762 Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1763 Tuner->CH_Ctrl[10].size = 1 ;
1764 Tuner->CH_Ctrl[10].addr[0] = 111;
1765 Tuner->CH_Ctrl[10].bit[0] = 5;
1766 Tuner->CH_Ctrl[10].val[0] = 0;
1767
1768 Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1769 Tuner->CH_Ctrl[11].size = 2 ;
1770 Tuner->CH_Ctrl[11].addr[0] = 110;
1771 Tuner->CH_Ctrl[11].bit[0] = 0;
1772 Tuner->CH_Ctrl[11].val[0] = 1;
1773 Tuner->CH_Ctrl[11].addr[1] = 110;
1774 Tuner->CH_Ctrl[11].bit[1] = 1;
1775 Tuner->CH_Ctrl[11].val[1] = 0;
1776
1777 Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1778 Tuner->CH_Ctrl[12].size = 3 ;
1779 Tuner->CH_Ctrl[12].addr[0] = 69;
1780 Tuner->CH_Ctrl[12].bit[0] = 2;
1781 Tuner->CH_Ctrl[12].val[0] = 0;
1782 Tuner->CH_Ctrl[12].addr[1] = 69;
1783 Tuner->CH_Ctrl[12].bit[1] = 3;
1784 Tuner->CH_Ctrl[12].val[1] = 0;
1785 Tuner->CH_Ctrl[12].addr[2] = 69;
1786 Tuner->CH_Ctrl[12].bit[2] = 4;
1787 Tuner->CH_Ctrl[12].val[2] = 0;
1788
1789 Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1790 Tuner->CH_Ctrl[13].size = 6 ;
1791 Tuner->CH_Ctrl[13].addr[0] = 110;
1792 Tuner->CH_Ctrl[13].bit[0] = 2;
1793 Tuner->CH_Ctrl[13].val[0] = 0;
1794 Tuner->CH_Ctrl[13].addr[1] = 110;
1795 Tuner->CH_Ctrl[13].bit[1] = 3;
1796 Tuner->CH_Ctrl[13].val[1] = 0;
1797 Tuner->CH_Ctrl[13].addr[2] = 110;
1798 Tuner->CH_Ctrl[13].bit[2] = 4;
1799 Tuner->CH_Ctrl[13].val[2] = 0;
1800 Tuner->CH_Ctrl[13].addr[3] = 110;
1801 Tuner->CH_Ctrl[13].bit[3] = 5;
1802 Tuner->CH_Ctrl[13].val[3] = 0;
1803 Tuner->CH_Ctrl[13].addr[4] = 110;
1804 Tuner->CH_Ctrl[13].bit[4] = 6;
1805 Tuner->CH_Ctrl[13].val[4] = 0;
1806 Tuner->CH_Ctrl[13].addr[5] = 110;
1807 Tuner->CH_Ctrl[13].bit[5] = 7;
1808 Tuner->CH_Ctrl[13].val[5] = 1;
1809
1810 Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1811 Tuner->CH_Ctrl[14].size = 7 ;
1812 Tuner->CH_Ctrl[14].addr[0] = 14;
1813 Tuner->CH_Ctrl[14].bit[0] = 0;
1814 Tuner->CH_Ctrl[14].val[0] = 0;
1815 Tuner->CH_Ctrl[14].addr[1] = 14;
1816 Tuner->CH_Ctrl[14].bit[1] = 1;
1817 Tuner->CH_Ctrl[14].val[1] = 0;
1818 Tuner->CH_Ctrl[14].addr[2] = 14;
1819 Tuner->CH_Ctrl[14].bit[2] = 2;
1820 Tuner->CH_Ctrl[14].val[2] = 0;
1821 Tuner->CH_Ctrl[14].addr[3] = 14;
1822 Tuner->CH_Ctrl[14].bit[3] = 3;
1823 Tuner->CH_Ctrl[14].val[3] = 0;
1824 Tuner->CH_Ctrl[14].addr[4] = 14;
1825 Tuner->CH_Ctrl[14].bit[4] = 4;
1826 Tuner->CH_Ctrl[14].val[4] = 0;
1827 Tuner->CH_Ctrl[14].addr[5] = 14;
1828 Tuner->CH_Ctrl[14].bit[5] = 5;
1829 Tuner->CH_Ctrl[14].val[5] = 0;
1830 Tuner->CH_Ctrl[14].addr[6] = 14;
1831 Tuner->CH_Ctrl[14].bit[6] = 6;
1832 Tuner->CH_Ctrl[14].val[6] = 0;
1833
1834 Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1835 Tuner->CH_Ctrl[15].size = 18 ;
1836 Tuner->CH_Ctrl[15].addr[0] = 17;
1837 Tuner->CH_Ctrl[15].bit[0] = 6;
1838 Tuner->CH_Ctrl[15].val[0] = 0;
1839 Tuner->CH_Ctrl[15].addr[1] = 17;
1840 Tuner->CH_Ctrl[15].bit[1] = 7;
1841 Tuner->CH_Ctrl[15].val[1] = 0;
1842 Tuner->CH_Ctrl[15].addr[2] = 16;
1843 Tuner->CH_Ctrl[15].bit[2] = 0;
1844 Tuner->CH_Ctrl[15].val[2] = 0;
1845 Tuner->CH_Ctrl[15].addr[3] = 16;
1846 Tuner->CH_Ctrl[15].bit[3] = 1;
1847 Tuner->CH_Ctrl[15].val[3] = 0;
1848 Tuner->CH_Ctrl[15].addr[4] = 16;
1849 Tuner->CH_Ctrl[15].bit[4] = 2;
1850 Tuner->CH_Ctrl[15].val[4] = 0;
1851 Tuner->CH_Ctrl[15].addr[5] = 16;
1852 Tuner->CH_Ctrl[15].bit[5] = 3;
1853 Tuner->CH_Ctrl[15].val[5] = 0;
1854 Tuner->CH_Ctrl[15].addr[6] = 16;
1855 Tuner->CH_Ctrl[15].bit[6] = 4;
1856 Tuner->CH_Ctrl[15].val[6] = 0;
1857 Tuner->CH_Ctrl[15].addr[7] = 16;
1858 Tuner->CH_Ctrl[15].bit[7] = 5;
1859 Tuner->CH_Ctrl[15].val[7] = 0;
1860 Tuner->CH_Ctrl[15].addr[8] = 16;
1861 Tuner->CH_Ctrl[15].bit[8] = 6;
1862 Tuner->CH_Ctrl[15].val[8] = 0;
1863 Tuner->CH_Ctrl[15].addr[9] = 16;
1864 Tuner->CH_Ctrl[15].bit[9] = 7;
1865 Tuner->CH_Ctrl[15].val[9] = 0;
1866 Tuner->CH_Ctrl[15].addr[10] = 15;
1867 Tuner->CH_Ctrl[15].bit[10] = 0;
1868 Tuner->CH_Ctrl[15].val[10] = 0;
1869 Tuner->CH_Ctrl[15].addr[11] = 15;
1870 Tuner->CH_Ctrl[15].bit[11] = 1;
1871 Tuner->CH_Ctrl[15].val[11] = 0;
1872 Tuner->CH_Ctrl[15].addr[12] = 15;
1873 Tuner->CH_Ctrl[15].bit[12] = 2;
1874 Tuner->CH_Ctrl[15].val[12] = 0;
1875 Tuner->CH_Ctrl[15].addr[13] = 15;
1876 Tuner->CH_Ctrl[15].bit[13] = 3;
1877 Tuner->CH_Ctrl[15].val[13] = 0;
1878 Tuner->CH_Ctrl[15].addr[14] = 15;
1879 Tuner->CH_Ctrl[15].bit[14] = 4;
1880 Tuner->CH_Ctrl[15].val[14] = 0;
1881 Tuner->CH_Ctrl[15].addr[15] = 15;
1882 Tuner->CH_Ctrl[15].bit[15] = 5;
1883 Tuner->CH_Ctrl[15].val[15] = 0;
1884 Tuner->CH_Ctrl[15].addr[16] = 15;
1885 Tuner->CH_Ctrl[15].bit[16] = 6;
1886 Tuner->CH_Ctrl[15].val[16] = 1;
1887 Tuner->CH_Ctrl[15].addr[17] = 15;
1888 Tuner->CH_Ctrl[15].bit[17] = 7;
1889 Tuner->CH_Ctrl[15].val[17] = 1;
1890
1891 Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1892 Tuner->CH_Ctrl[16].size = 5 ;
1893 Tuner->CH_Ctrl[16].addr[0] = 112;
1894 Tuner->CH_Ctrl[16].bit[0] = 0;
1895 Tuner->CH_Ctrl[16].val[0] = 0;
1896 Tuner->CH_Ctrl[16].addr[1] = 112;
1897 Tuner->CH_Ctrl[16].bit[1] = 1;
1898 Tuner->CH_Ctrl[16].val[1] = 0;
1899 Tuner->CH_Ctrl[16].addr[2] = 112;
1900 Tuner->CH_Ctrl[16].bit[2] = 2;
1901 Tuner->CH_Ctrl[16].val[2] = 0;
1902 Tuner->CH_Ctrl[16].addr[3] = 112;
1903 Tuner->CH_Ctrl[16].bit[3] = 3;
1904 Tuner->CH_Ctrl[16].val[3] = 0;
1905 Tuner->CH_Ctrl[16].addr[4] = 112;
1906 Tuner->CH_Ctrl[16].bit[4] = 4;
1907 Tuner->CH_Ctrl[16].val[4] = 1;
1908
1909 Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1910 Tuner->CH_Ctrl[17].size = 1 ;
1911 Tuner->CH_Ctrl[17].addr[0] = 14;
1912 Tuner->CH_Ctrl[17].bit[0] = 7;
1913 Tuner->CH_Ctrl[17].val[0] = 0;
1914
1915 Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1916 Tuner->CH_Ctrl[18].size = 4 ;
1917 Tuner->CH_Ctrl[18].addr[0] = 107;
1918 Tuner->CH_Ctrl[18].bit[0] = 3;
1919 Tuner->CH_Ctrl[18].val[0] = 0;
1920 Tuner->CH_Ctrl[18].addr[1] = 107;
1921 Tuner->CH_Ctrl[18].bit[1] = 4;
1922 Tuner->CH_Ctrl[18].val[1] = 0;
1923 Tuner->CH_Ctrl[18].addr[2] = 107;
1924 Tuner->CH_Ctrl[18].bit[2] = 5;
1925 Tuner->CH_Ctrl[18].val[2] = 0;
1926 Tuner->CH_Ctrl[18].addr[3] = 107;
1927 Tuner->CH_Ctrl[18].bit[3] = 6;
1928 Tuner->CH_Ctrl[18].val[3] = 0;
1929
1930 Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1931 Tuner->CH_Ctrl[19].size = 3 ;
1932 Tuner->CH_Ctrl[19].addr[0] = 107;
1933 Tuner->CH_Ctrl[19].bit[0] = 7;
1934 Tuner->CH_Ctrl[19].val[0] = 1;
1935 Tuner->CH_Ctrl[19].addr[1] = 106;
1936 Tuner->CH_Ctrl[19].bit[1] = 0;
1937 Tuner->CH_Ctrl[19].val[1] = 1;
1938 Tuner->CH_Ctrl[19].addr[2] = 106;
1939 Tuner->CH_Ctrl[19].bit[2] = 1;
1940 Tuner->CH_Ctrl[19].val[2] = 1;
1941
1942 Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1943 Tuner->CH_Ctrl[20].size = 11 ;
1944 Tuner->CH_Ctrl[20].addr[0] = 109;
1945 Tuner->CH_Ctrl[20].bit[0] = 2;
1946 Tuner->CH_Ctrl[20].val[0] = 0;
1947 Tuner->CH_Ctrl[20].addr[1] = 109;
1948 Tuner->CH_Ctrl[20].bit[1] = 3;
1949 Tuner->CH_Ctrl[20].val[1] = 0;
1950 Tuner->CH_Ctrl[20].addr[2] = 109;
1951 Tuner->CH_Ctrl[20].bit[2] = 4;
1952 Tuner->CH_Ctrl[20].val[2] = 0;
1953 Tuner->CH_Ctrl[20].addr[3] = 109;
1954 Tuner->CH_Ctrl[20].bit[3] = 5;
1955 Tuner->CH_Ctrl[20].val[3] = 0;
1956 Tuner->CH_Ctrl[20].addr[4] = 109;
1957 Tuner->CH_Ctrl[20].bit[4] = 6;
1958 Tuner->CH_Ctrl[20].val[4] = 0;
1959 Tuner->CH_Ctrl[20].addr[5] = 109;
1960 Tuner->CH_Ctrl[20].bit[5] = 7;
1961 Tuner->CH_Ctrl[20].val[5] = 0;
1962 Tuner->CH_Ctrl[20].addr[6] = 108;
1963 Tuner->CH_Ctrl[20].bit[6] = 0;
1964 Tuner->CH_Ctrl[20].val[6] = 0;
1965 Tuner->CH_Ctrl[20].addr[7] = 108;
1966 Tuner->CH_Ctrl[20].bit[7] = 1;
1967 Tuner->CH_Ctrl[20].val[7] = 0;
1968 Tuner->CH_Ctrl[20].addr[8] = 108;
1969 Tuner->CH_Ctrl[20].bit[8] = 2;
1970 Tuner->CH_Ctrl[20].val[8] = 1;
1971 Tuner->CH_Ctrl[20].addr[9] = 108;
1972 Tuner->CH_Ctrl[20].bit[9] = 3;
1973 Tuner->CH_Ctrl[20].val[9] = 1;
1974 Tuner->CH_Ctrl[20].addr[10] = 108;
1975 Tuner->CH_Ctrl[20].bit[10] = 4;
1976 Tuner->CH_Ctrl[20].val[10] = 1;
1977
1978 Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1979 Tuner->CH_Ctrl[21].size = 6 ;
1980 Tuner->CH_Ctrl[21].addr[0] = 106;
1981 Tuner->CH_Ctrl[21].bit[0] = 2;
1982 Tuner->CH_Ctrl[21].val[0] = 0;
1983 Tuner->CH_Ctrl[21].addr[1] = 106;
1984 Tuner->CH_Ctrl[21].bit[1] = 3;
1985 Tuner->CH_Ctrl[21].val[1] = 0;
1986 Tuner->CH_Ctrl[21].addr[2] = 106;
1987 Tuner->CH_Ctrl[21].bit[2] = 4;
1988 Tuner->CH_Ctrl[21].val[2] = 0;
1989 Tuner->CH_Ctrl[21].addr[3] = 106;
1990 Tuner->CH_Ctrl[21].bit[3] = 5;
1991 Tuner->CH_Ctrl[21].val[3] = 0;
1992 Tuner->CH_Ctrl[21].addr[4] = 106;
1993 Tuner->CH_Ctrl[21].bit[4] = 6;
1994 Tuner->CH_Ctrl[21].val[4] = 0;
1995 Tuner->CH_Ctrl[21].addr[5] = 106;
1996 Tuner->CH_Ctrl[21].bit[5] = 7;
1997 Tuner->CH_Ctrl[21].val[5] = 1;
1998
1999 Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
2000 Tuner->CH_Ctrl[22].size = 1 ;
2001 Tuner->CH_Ctrl[22].addr[0] = 138;
2002 Tuner->CH_Ctrl[22].bit[0] = 4;
2003 Tuner->CH_Ctrl[22].val[0] = 1;
2004
2005 Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
2006 Tuner->CH_Ctrl[23].size = 1 ;
2007 Tuner->CH_Ctrl[23].addr[0] = 17;
2008 Tuner->CH_Ctrl[23].bit[0] = 5;
2009 Tuner->CH_Ctrl[23].val[0] = 0;
2010
2011 Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
2012 Tuner->CH_Ctrl[24].size = 1 ;
2013 Tuner->CH_Ctrl[24].addr[0] = 111;
2014 Tuner->CH_Ctrl[24].bit[0] = 3;
2015 Tuner->CH_Ctrl[24].val[0] = 0;
2016
2017 Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
2018 Tuner->CH_Ctrl[25].size = 1 ;
2019 Tuner->CH_Ctrl[25].addr[0] = 112;
2020 Tuner->CH_Ctrl[25].bit[0] = 7;
2021 Tuner->CH_Ctrl[25].val[0] = 0;
2022
2023 Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
2024 Tuner->CH_Ctrl[26].size = 1 ;
2025 Tuner->CH_Ctrl[26].addr[0] = 136;
2026 Tuner->CH_Ctrl[26].bit[0] = 7;
2027 Tuner->CH_Ctrl[26].val[0] = 0;
2028
2029 Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
2030 Tuner->CH_Ctrl[27].size = 1 ;
2031 Tuner->CH_Ctrl[27].addr[0] = 149;
2032 Tuner->CH_Ctrl[27].bit[0] = 7;
2033 Tuner->CH_Ctrl[27].val[0] = 0;
2034
2035 Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
2036 Tuner->CH_Ctrl[28].size = 1 ;
2037 Tuner->CH_Ctrl[28].addr[0] = 149;
2038 Tuner->CH_Ctrl[28].bit[0] = 6;
2039 Tuner->CH_Ctrl[28].val[0] = 0;
2040
2041 Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
2042 Tuner->CH_Ctrl[29].size = 1 ;
2043 Tuner->CH_Ctrl[29].addr[0] = 149;
2044 Tuner->CH_Ctrl[29].bit[0] = 5;
2045 Tuner->CH_Ctrl[29].val[0] = 1;
2046
2047 Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
2048 Tuner->CH_Ctrl[30].size = 1 ;
2049 Tuner->CH_Ctrl[30].addr[0] = 149;
2050 Tuner->CH_Ctrl[30].bit[0] = 4;
2051 Tuner->CH_Ctrl[30].val[0] = 1;
2052
2053 Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
2054 Tuner->CH_Ctrl[31].size = 1 ;
2055 Tuner->CH_Ctrl[31].addr[0] = 149;
2056 Tuner->CH_Ctrl[31].bit[0] = 3;
2057 Tuner->CH_Ctrl[31].val[0] = 0;
2058
2059 Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
2060 Tuner->CH_Ctrl[32].size = 1 ;
2061 Tuner->CH_Ctrl[32].addr[0] = 93;
2062 Tuner->CH_Ctrl[32].bit[0] = 1;
2063 Tuner->CH_Ctrl[32].val[0] = 0;
2064
2065 Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
2066 Tuner->CH_Ctrl[33].size = 1 ;
2067 Tuner->CH_Ctrl[33].addr[0] = 93;
2068 Tuner->CH_Ctrl[33].bit[0] = 0;
2069 Tuner->CH_Ctrl[33].val[0] = 0;
2070
2071 Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
2072 Tuner->CH_Ctrl[34].size = 6 ;
2073 Tuner->CH_Ctrl[34].addr[0] = 92;
2074 Tuner->CH_Ctrl[34].bit[0] = 2;
2075 Tuner->CH_Ctrl[34].val[0] = 0;
2076 Tuner->CH_Ctrl[34].addr[1] = 92;
2077 Tuner->CH_Ctrl[34].bit[1] = 3;
2078 Tuner->CH_Ctrl[34].val[1] = 0;
2079 Tuner->CH_Ctrl[34].addr[2] = 92;
2080 Tuner->CH_Ctrl[34].bit[2] = 4;
2081 Tuner->CH_Ctrl[34].val[2] = 0;
2082 Tuner->CH_Ctrl[34].addr[3] = 92;
2083 Tuner->CH_Ctrl[34].bit[3] = 5;
2084 Tuner->CH_Ctrl[34].val[3] = 0;
2085 Tuner->CH_Ctrl[34].addr[4] = 92;
2086 Tuner->CH_Ctrl[34].bit[4] = 6;
2087 Tuner->CH_Ctrl[34].val[4] = 0;
2088 Tuner->CH_Ctrl[34].addr[5] = 92;
2089 Tuner->CH_Ctrl[34].bit[5] = 7;
2090 Tuner->CH_Ctrl[34].val[5] = 0;
2091
2092 Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
2093 Tuner->CH_Ctrl[35].size = 6 ;
2094 Tuner->CH_Ctrl[35].addr[0] = 93;
2095 Tuner->CH_Ctrl[35].bit[0] = 2;
2096 Tuner->CH_Ctrl[35].val[0] = 0;
2097 Tuner->CH_Ctrl[35].addr[1] = 93;
2098 Tuner->CH_Ctrl[35].bit[1] = 3;
2099 Tuner->CH_Ctrl[35].val[1] = 0;
2100 Tuner->CH_Ctrl[35].addr[2] = 93;
2101 Tuner->CH_Ctrl[35].bit[2] = 4;
2102 Tuner->CH_Ctrl[35].val[2] = 0;
2103 Tuner->CH_Ctrl[35].addr[3] = 93;
2104 Tuner->CH_Ctrl[35].bit[3] = 5;
2105 Tuner->CH_Ctrl[35].val[3] = 0;
2106 Tuner->CH_Ctrl[35].addr[4] = 93;
2107 Tuner->CH_Ctrl[35].bit[4] = 6;
2108 Tuner->CH_Ctrl[35].val[4] = 0;
2109 Tuner->CH_Ctrl[35].addr[5] = 93;
2110 Tuner->CH_Ctrl[35].bit[5] = 7;
2111 Tuner->CH_Ctrl[35].val[5] = 0;
2112
2113#ifdef _MXL_PRODUCTION
2114 Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
2115 Tuner->CH_Ctrl[36].size = 1 ;
2116 Tuner->CH_Ctrl[36].addr[0] = 109;
2117 Tuner->CH_Ctrl[36].bit[0] = 1;
2118 Tuner->CH_Ctrl[36].val[0] = 1;
2119
2120 Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
2121 Tuner->CH_Ctrl[37].size = 2 ;
2122 Tuner->CH_Ctrl[37].addr[0] = 112;
2123 Tuner->CH_Ctrl[37].bit[0] = 5;
2124 Tuner->CH_Ctrl[37].val[0] = 0;
2125 Tuner->CH_Ctrl[37].addr[1] = 112;
2126 Tuner->CH_Ctrl[37].bit[1] = 6;
2127 Tuner->CH_Ctrl[37].val[1] = 0;
2128
2129 Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
2130 Tuner->CH_Ctrl[38].size = 1 ;
2131 Tuner->CH_Ctrl[38].addr[0] = 65;
2132 Tuner->CH_Ctrl[38].bit[0] = 1;
2133 Tuner->CH_Ctrl[38].val[0] = 0;
2134#endif
2135
2136 return 0 ;
2137}
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153// MaxLinear source code - MXL5005_c.cpp
2154
2155
2156
2157// MXL5005.cpp : Defines the initialization routines for the DLL.
2158// 2.6.12
2159
2160
2161//#ifdef _MXL_HEADER
2162//#include "stdafx.h"
2163//#endif
2164//#include "MXL5005_c.h"
2165
2166
2167void InitTunerControls(Tuner_struct *Tuner)
2168{
2169 MXL5005_RegisterInit(Tuner) ;
2170 MXL5005_ControlInit(Tuner) ;
2171#ifdef _MXL_INTERNAL
2172 MXL5005_MXLControlInit(Tuner) ;
2173#endif
2174}
2175
2176
2177
2178///////////////////////////////////////////////////////////////////////////////
2179// //
2180// Function: MXL_ConfigTuner //
2181// //
2182// Description: Configure MXL5005Tuner structure for desired //
2183// Channel Bandwidth/Channel Frequency //
2184// //
2185// //
2186// Functions used: //
2187// MXL_SynthIFLO_Calc //
2188// //
2189// Inputs: //
2190// Tuner_struct: structure defined at higher level //
2191// Mode: Tuner Mode (Analog/Digital) //
2192// IF_Mode: IF Mode ( Zero/Low ) //
2193// Bandwidth: Filter Channel Bandwidth (in Hz) //
2194// IF_out: Desired IF out Frequency (in Hz) //
2195// Fxtal: Crystal Frerquency (in Hz) //
2196// TOP: 0: Dual AGC; Value: take over point //
2197// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) //
2198// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out //
2199// DIV_OUT: 0: Div-1; 1: Div-4 //
2200// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable //
2201// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI //
2202// //
2203// Outputs: //
2204// Tuner //
2205// //
2206// Return: //
2207// 0 : Successful //
2208// > 0 : Failed //
2209// //
2210///////////////////////////////////////////////////////////////////////////////
2211_u16 MXL5005_TunerConfig(Tuner_struct *Tuner,
2212 _u8 Mode, // 0: Analog Mode ; 1: Digital Mode
2213 _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF
2214 _u32 Bandwidth, // filter channel bandwidth (6, 7, 8)
2215 _u32 IF_out, // Desired IF Out Frequency
2216 _u32 Fxtal, // XTAL Frequency
2217 _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1
2218 _u16 TOP, // 0: Dual AGC; Value: take over point
2219 _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms)
2220 _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out
2221 _u8 DIV_OUT, // 0: Div-1; 1: Div-4
2222 _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable
2223 _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI
2224 _u8 Mod_Type, // Modulation Type;
2225 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable
2226 _u8 TF_Type // Tracking Filter
2227 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H
2228 )
2229{
2230 _u16 status = 0 ;
2231
2232 Tuner->Mode = Mode ;
2233 Tuner->IF_Mode = IF_mode ;
2234 Tuner->Chan_Bandwidth = Bandwidth ;
2235 Tuner->IF_OUT = IF_out ;
2236 Tuner->Fxtal = Fxtal ;
2237 Tuner->AGC_Mode = AGC_Mode ;
2238 Tuner->TOP = TOP ;
2239 Tuner->IF_OUT_LOAD = IF_OUT_LOAD ;
2240 Tuner->CLOCK_OUT = CLOCK_OUT ;
2241 Tuner->DIV_OUT = DIV_OUT ;
2242 Tuner->CAPSELECT = CAPSELECT ;
2243 Tuner->EN_RSSI = EN_RSSI ;
2244 Tuner->Mod_Type = Mod_Type ;
2245 Tuner->TF_Type = TF_Type ;
2246
2247
2248
2249 //
2250 // Initialize all the controls and registers
2251 //
2252 InitTunerControls (Tuner) ;
2253 //
2254 // Synthesizer LO frequency calculation
2255 //
2256 MXL_SynthIFLO_Calc( Tuner ) ;
2257
2258 return status ;
2259}
2260
2261///////////////////////////////////////////////////////////////////////////////
2262// //
2263// Function: MXL_SynthIFLO_Calc //
2264// //
2265// Description: Calculate Internal IF-LO Frequency //
2266// //
2267// Globals: //
2268// NONE //
2269// //
2270// Functions used: //
2271// NONE //
2272// //
2273// Inputs: //
2274// Tuner_struct: structure defined at higher level //
2275// //
2276// Outputs: //
2277// Tuner //
2278// //
2279// Return: //
2280// 0 : Successful //
2281// > 0 : Failed //
2282// //
2283///////////////////////////////////////////////////////////////////////////////
2284void MXL_SynthIFLO_Calc(Tuner_struct *Tuner)
2285{
2286 if (Tuner->Mode == 1) // Digital Mode
2287 {
2288 Tuner->IF_LO = Tuner->IF_OUT ;
2289 }
2290 else // Analog Mode
2291 {
2292 if(Tuner->IF_Mode == 0) // Analog Zero IF mode
2293 {
2294 Tuner->IF_LO = Tuner->IF_OUT + 400000 ;
2295 }
2296 else // Analog Low IF mode
2297 {
2298 Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ;
2299 }
2300 }
2301}
2302
2303///////////////////////////////////////////////////////////////////////////////
2304// //
2305// Function: MXL_SynthRFTGLO_Calc //
2306// //
2307// Description: Calculate Internal RF-LO frequency and //
2308// internal Tone-Gen(TG)-LO frequency //
2309// //
2310// Globals: //
2311// NONE //
2312// //
2313// Functions used: //
2314// NONE //
2315// //
2316// Inputs: //
2317// Tuner_struct: structure defined at higher level //
2318// //
2319// Outputs: //
2320// Tuner //
2321// //
2322// Return: //
2323// 0 : Successful //
2324// > 0 : Failed //
2325// //
2326///////////////////////////////////////////////////////////////////////////////
2327void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner)
2328{
2329 if (Tuner->Mode == 1) // Digital Mode
2330 {
2331 //remove 20.48MHz setting for 2.6.10
2332 Tuner->RF_LO = Tuner->RF_IN ;
2333 Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6
2334 }
2335 else // Analog Mode
2336 {
2337 if(Tuner->IF_Mode == 0) // Analog Zero IF mode
2338 {
2339 Tuner->RF_LO = Tuner->RF_IN - 400000 ;
2340 Tuner->TG_LO = Tuner->RF_IN - 1750000 ;
2341 }
2342 else // Analog Low IF mode
2343 {
2344 Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ;
2345 Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ;
2346 }
2347 }
2348}
2349
2350///////////////////////////////////////////////////////////////////////////////
2351// //
2352// Function: MXL_OverwriteICDefault //
2353// //
2354// Description: Overwrite the Default Register Setting //
2355// //
2356// //
2357// Functions used: //
2358// //
2359// Inputs: //
2360// Tuner_struct: structure defined at higher level //
2361// Outputs: //
2362// Tuner //
2363// //
2364// Return: //
2365// 0 : Successful //
2366// > 0 : Failed //
2367// //
2368///////////////////////////////////////////////////////////////////////////////
2369_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner)
2370{
2371 _u16 status = 0 ;
2372
2373 status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ;
2374 status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ;
2375 status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ;
2376 status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ;
2377
2378 return status ;
2379}
2380
2381///////////////////////////////////////////////////////////////////////////////
2382// //
2383// Function: MXL_BlockInit //
2384// //
2385// Description: Tuner Initialization as a function of 'User Settings' //
2386// * User settings in Tuner strcuture must be assigned //
2387// first //
2388// //
2389// Globals: //
2390// NONE //
2391// //
2392// Functions used: //
2393// Tuner_struct: structure defined at higher level //
2394// //
2395// Inputs: //
2396// Tuner : Tuner structure defined at higher level //
2397// //
2398// Outputs: //
2399// Tuner //
2400// //
2401// Return: //
2402// 0 : Successful //
2403// > 0 : Failed //
2404// //
2405///////////////////////////////////////////////////////////////////////////////
2406_u16 MXL_BlockInit( Tuner_struct *Tuner )
2407{
2408 _u16 status = 0 ;
2409
2410 status += MXL_OverwriteICDefault(Tuner) ;
2411
2412 //
2413 // Downconverter Control
2414 // Dig Ana
2415 status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ;
2416
2417 //
2418 // Filter Control
2419 // Dig Ana
2420 status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ;
2421 status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ;
2422 status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ;
2423
2424 status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ;
2425 status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ;
2426
2427 // Initialize Low-Pass Filter
2428 if (Tuner->Mode) { // Digital Mode
2429 switch (Tuner->Chan_Bandwidth) {
2430 case 8000000:
2431 status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ;
2432 break ;
2433 case 7000000:
2434 status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ;
2435 break ;
2436 case 6000000:
2437 status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ;
2438 break ;
2439 }
2440 } else { // Analog Mode
2441 switch (Tuner->Chan_Bandwidth) {
2442 case 8000000: // Low Zero
2443 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ;
2444 break ;
2445 case 7000000:
2446 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ;
2447 break ;
2448 case 6000000:
2449 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ;
2450 break ;
2451 }
2452 }
2453
2454 //
2455 // Charge Pump Control
2456 // Dig Ana
2457 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ;
2458 status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ;
2459 status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ;
2460
2461 //
2462 // AGC TOP Control
2463 //
2464 if (Tuner->AGC_Mode == 0) // Dual AGC
2465 {
2466 status += MXL_ControlWrite(Tuner, AGC_IF, 15) ;
2467 status += MXL_ControlWrite(Tuner, AGC_RF, 15) ;
2468 }
2469 else // Single AGC Mode Dig Ana
2470 status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ;
2471
2472
2473 if (Tuner->TOP == 55) // TOP == 5.5
2474 status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ;
2475
2476 if (Tuner->TOP == 72) // TOP == 7.2
2477 status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ;
2478
2479 if (Tuner->TOP == 92) // TOP == 9.2
2480 status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ;
2481
2482 if (Tuner->TOP == 110) // TOP == 11.0
2483 status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ;
2484
2485 if (Tuner->TOP == 129) // TOP == 12.9
2486 status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ;
2487
2488 if (Tuner->TOP == 147) // TOP == 14.7
2489 status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ;
2490
2491 if (Tuner->TOP == 168) // TOP == 16.8
2492 status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ;
2493
2494 if (Tuner->TOP == 194) // TOP == 19.4
2495 status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ;
2496
2497 if (Tuner->TOP == 212) // TOP == 21.2
2498 status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ;
2499
2500 if (Tuner->TOP == 232) // TOP == 23.2
2501 status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ;
2502
2503 if (Tuner->TOP == 252) // TOP == 25.2
2504 status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ;
2505
2506 if (Tuner->TOP == 271) // TOP == 27.1
2507 status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ;
2508
2509 if (Tuner->TOP == 292) // TOP == 29.2
2510 status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ;
2511
2512 if (Tuner->TOP == 317) // TOP == 31.7
2513 status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ;
2514
2515 if (Tuner->TOP == 349) // TOP == 34.9
2516 status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ;
2517
2518 //
2519 // IF Synthesizer Control
2520 //
2521 status += MXL_IFSynthInit( Tuner ) ;
2522
2523 //
2524 // IF UpConverter Control
2525 if (Tuner->IF_OUT_LOAD == 200)
2526 {
2527 status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ;
2528 status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ;
2529 }
2530 if (Tuner->IF_OUT_LOAD == 300)
2531 {
2532 status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ;
2533 status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ;
2534 }
2535
2536 //
2537 // Anti-Alias Filtering Control
2538 //
2539 // initialise Anti-Aliasing Filter
2540 if (Tuner->Mode) {// Digital Mode
2541 if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) {
2542 status += MXL_ControlWrite(Tuner, EN_AAF, 1) ;
2543 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2544 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2545 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ;
2546 }
2547 if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) {
2548 status += MXL_ControlWrite(Tuner, EN_AAF, 1) ;
2549 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2550 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2551 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ;
2552 }
2553 if (Tuner->IF_OUT > 36150000UL) {
2554 status += MXL_ControlWrite(Tuner, EN_AAF, 0) ;
2555 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2556 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2557 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ;
2558 }
2559 } else { // Analog Mode
2560 if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL)
2561 {
2562 status += MXL_ControlWrite(Tuner, EN_AAF, 1) ;
2563 status += MXL_ControlWrite(Tuner, EN_3P, 1) ;
2564 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ;
2565 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ;
2566 }
2567 if (Tuner->IF_OUT > 5000000UL)
2568 {
2569 status += MXL_ControlWrite(Tuner, EN_AAF, 0) ;
2570 status += MXL_ControlWrite(Tuner, EN_3P, 0) ;
2571 status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ;
2572 status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ;
2573 }
2574 }
2575
2576 //
2577 // Demod Clock Out
2578 //
2579 if (Tuner->CLOCK_OUT)
2580 status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ;
2581 else
2582 status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ;
2583
2584 if (Tuner->DIV_OUT == 1)
2585 status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ;
2586 if (Tuner->DIV_OUT == 0)
2587 status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ;
2588
2589 //
2590 // Crystal Control
2591 //
2592 if (Tuner->CAPSELECT)
2593 status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ;
2594 else
2595 status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ;
2596
2597 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL)
2598 status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ;
2599 if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL)
2600 status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ;
2601
2602 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL)
2603 status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ;
2604 if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL)
2605 status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ;
2606
2607 //
2608 // Misc Controls
2609 //
2610 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode
2611 status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0);
2612 else
2613 status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1);
2614
2615// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ;
2616
2617 // Set TG_R_DIV
2618 status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ;
2619
2620 //
2621 // Apply Default value to BB_INITSTATE_DLPF_TUNE
2622 //
2623
2624
2625
2626 //
2627 // RSSI Control
2628 //
2629 if(Tuner->EN_RSSI)
2630 {
2631 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2632 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2633 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2634 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2635 // RSSI reference point
2636 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ;
2637 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ;
2638 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ;
2639 // TOP point
2640 status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ;
2641 status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ;
2642 }
2643
2644 //
2645 // Modulation type bit settings
2646 // Override the control values preset
2647 //
2648 if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode
2649 {
2650 Tuner->AGC_Mode = 1 ; // Single AGC Mode
2651
2652 // Enable RSSI
2653 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2654 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2655 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2656 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2657 // RSSI reference point
2658 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
2659 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
2660 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ;
2661 // TOP point
2662 status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ;
2663 status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ;
2664 if (Tuner->IF_OUT <= 6280000UL) // Low IF
2665 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ;
2666 else // High IF
2667 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2668
2669 }
2670 if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode
2671 {
2672 Tuner->AGC_Mode = 1 ; // Single AGC Mode
2673
2674 // Enable RSSI
2675 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2676 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2677 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2678 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2679 // RSSI reference point
2680 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ;
2681 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ;
2682 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ;
2683 // TOP point
2684 status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ;
2685 status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ;
2686
2687 status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ;
2688 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero
2689 if (Tuner->IF_OUT <= 6280000UL) // Low IF
2690 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ;
2691 else // High IF
2692 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2693 }
2694 if (Tuner->Mod_Type == MXL_QAM) // QAM Mode
2695 {
2696 Tuner->Mode = MXL_DIGITAL_MODE;
2697
2698 //Tuner->AGC_Mode = 1 ; // Single AGC Mode
2699
2700 // Disable RSSI //change here for v2.6.5
2701 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2702 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2703 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
2704 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2705
2706 // RSSI reference point
2707 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
2708 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
2709 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ;
2710
2711 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5
2712
2713 if (Tuner->IF_OUT <= 6280000UL) // Low IF
2714 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ;
2715 else // High IF
2716 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2717 }
2718 if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode
2719 {
2720 //Tuner->Mode = MXL_DIGITAL_MODE ;
2721 Tuner->AGC_Mode = 1 ; // Single AGC Mode
2722
2723 // Disable RSSI
2724 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2725 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2726 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
2727 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2728
2729 status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3
2730 status += MXL_ControlWrite(Tuner, AGC_RF, 15) ;
2731
2732 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2733 }
2734
2735 if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7
2736 {
2737 //Tuner->Mode = MXL_ANALOG_MODE;
2738
2739 // Enable RSSI
2740 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2741 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2742 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
2743 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2744
2745 // RSSI reference point
2746 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
2747 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
2748 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ;
2749
2750 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ;
2751
2752 status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ;
2753 }
2754
2755 // RSSI disable
2756 if(Tuner->EN_RSSI==0)
2757 {
2758 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2759 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2760 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
2761 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
2762 }
2763
2764 return status ;
2765}
2766
2767///////////////////////////////////////////////////////////////////////////////
2768// //
2769// Function: MXL_IFSynthInit //
2770// //
2771// Description: Tuner IF Synthesizer related register initialization //
2772// //
2773// Globals: //
2774// NONE //
2775// //
2776// Functions used: //
2777// Tuner_struct: structure defined at higher level //
2778// //
2779// Inputs: //
2780// Tuner : Tuner structure defined at higher level //
2781// //
2782// Outputs: //
2783// Tuner //
2784// //
2785// Return: //
2786// 0 : Successful //
2787// > 0 : Failed //
2788// //
2789///////////////////////////////////////////////////////////////////////////////
2790_u16 MXL_IFSynthInit( Tuner_struct * Tuner )
2791{
2792 _u16 status = 0 ;
2793 // Declare Local Variables
2794 _u32 Fref = 0 ;
2795 _u32 Kdbl, intModVal ;
2796 _u32 fracModVal ;
2797 Kdbl = 2 ;
2798
2799 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL)
2800 Kdbl = 2 ;
2801 if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL)
2802 Kdbl = 1 ;
2803
2804 //
2805 // IF Synthesizer Control
2806 //
2807 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode
2808 {
2809 if (Tuner->IF_LO == 41000000UL) {
2810 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2811 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2812 Fref = 328000000UL ;
2813 }
2814 if (Tuner->IF_LO == 47000000UL) {
2815 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2816 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2817 Fref = 376000000UL ;
2818 }
2819 if (Tuner->IF_LO == 54000000UL) {
2820 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2821 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2822 Fref = 324000000UL ;
2823 }
2824 if (Tuner->IF_LO == 60000000UL) {
2825 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2826 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2827 Fref = 360000000UL ;
2828 }
2829 if (Tuner->IF_LO == 39250000UL) {
2830 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2831 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2832 Fref = 314000000UL ;
2833 }
2834 if (Tuner->IF_LO == 39650000UL) {
2835 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2836 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2837 Fref = 317200000UL ;
2838 }
2839 if (Tuner->IF_LO == 40150000UL) {
2840 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2841 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2842 Fref = 321200000UL ;
2843 }
2844 if (Tuner->IF_LO == 40650000UL) {
2845 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2846 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2847 Fref = 325200000UL ;
2848 }
2849 }
2850
2851 if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0))
2852 {
2853 if (Tuner->IF_LO == 57000000UL) {
2854 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2855 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2856 Fref = 342000000UL ;
2857 }
2858 if (Tuner->IF_LO == 44000000UL) {
2859 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2860 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2861 Fref = 352000000UL ;
2862 }
2863 if (Tuner->IF_LO == 43750000UL) {
2864 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2865 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2866 Fref = 350000000UL ;
2867 }
2868 if (Tuner->IF_LO == 36650000UL) {
2869 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2870 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2871 Fref = 366500000UL ;
2872 }
2873 if (Tuner->IF_LO == 36150000UL) {
2874 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2875 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2876 Fref = 361500000UL ;
2877 }
2878 if (Tuner->IF_LO == 36000000UL) {
2879 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2880 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2881 Fref = 360000000UL ;
2882 }
2883 if (Tuner->IF_LO == 35250000UL) {
2884 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2885 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2886 Fref = 352500000UL ;
2887 }
2888 if (Tuner->IF_LO == 34750000UL) {
2889 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2890 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2891 Fref = 347500000UL ;
2892 }
2893 if (Tuner->IF_LO == 6280000UL) {
2894 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2895 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2896 Fref = 376800000UL ;
2897 }
2898 if (Tuner->IF_LO == 5000000UL) {
2899 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ;
2900 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2901 Fref = 360000000UL ;
2902 }
2903 if (Tuner->IF_LO == 4500000UL) {
2904 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ;
2905 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2906 Fref = 360000000UL ;
2907 }
2908 if (Tuner->IF_LO == 4570000UL) {
2909 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ;
2910 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2911 Fref = 365600000UL ;
2912 }
2913 if (Tuner->IF_LO == 4000000UL) {
2914 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ;
2915 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2916 Fref = 360000000UL ;
2917 }
2918 if (Tuner->IF_LO == 57400000UL)
2919 {
2920 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ;
2921 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2922 Fref = 344400000UL ;
2923 }
2924 if (Tuner->IF_LO == 44400000UL)
2925 {
2926 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2927 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2928 Fref = 355200000UL ;
2929 }
2930 if (Tuner->IF_LO == 44150000UL)
2931 {
2932 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ;
2933 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2934 Fref = 353200000UL ;
2935 }
2936 if (Tuner->IF_LO == 37050000UL)
2937 {
2938 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2939 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2940 Fref = 370500000UL ;
2941 }
2942 if (Tuner->IF_LO == 36550000UL)
2943 {
2944 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2945 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2946 Fref = 365500000UL ;
2947 }
2948 if (Tuner->IF_LO == 36125000UL) {
2949 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ;
2950 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2951 Fref = 361250000UL ;
2952 }
2953 if (Tuner->IF_LO == 6000000UL) {
2954 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2955 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2956 Fref = 360000000UL ;
2957 }
2958 if (Tuner->IF_LO == 5400000UL)
2959 {
2960 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2961 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2962 Fref = 324000000UL ;
2963 }
2964 if (Tuner->IF_LO == 5380000UL) {
2965 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ;
2966 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ;
2967 Fref = 322800000UL ;
2968 }
2969 if (Tuner->IF_LO == 5200000UL) {
2970 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ;
2971 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2972 Fref = 374400000UL ;
2973 }
2974 if (Tuner->IF_LO == 4900000UL)
2975 {
2976 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ;
2977 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2978 Fref = 352800000UL ;
2979 }
2980 if (Tuner->IF_LO == 4400000UL)
2981 {
2982 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ;
2983 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2984 Fref = 352000000UL ;
2985 }
2986 if (Tuner->IF_LO == 4063000UL) //add for 2.6.8
2987 {
2988 status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ;
2989 status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ;
2990 Fref = 365670000UL ;
2991 }
2992 }
2993 // CHCAL_INT_MOD_IF
2994 // CHCAL_FRAC_MOD_IF
2995 intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ;
2996 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ;
2997
2998 fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal);
2999 fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ;
3000 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ;
3001
3002
3003
3004 return status ;
3005}
3006
3007///////////////////////////////////////////////////////////////////////////////
3008// //
3009// Function: MXL_GetXtalInt //
3010// //
3011// Description: return the Crystal Integration Value for //
3012// TG_VCO_BIAS calculation //
3013// //
3014// Globals: //
3015// NONE //
3016// //
3017// Functions used: //
3018// NONE //
3019// //
3020// Inputs: //
3021// Crystal Frequency Value in Hz //
3022// //
3023// Outputs: //
3024// Calculated Crystal Frequency Integration Value //
3025// //
3026// Return: //
3027// 0 : Successful //
3028// > 0 : Failed //
3029// //
3030///////////////////////////////////////////////////////////////////////////////
3031_u32 MXL_GetXtalInt(_u32 Xtal_Freq)
3032{
3033 if ((Xtal_Freq % 1000000) == 0)
3034 return (Xtal_Freq / 10000) ;
3035 else
3036 return (((Xtal_Freq / 1000000) + 1)*100) ;
3037}
3038
3039///////////////////////////////////////////////////////////////////////////////
3040// //
3041// Function: MXL5005_TuneRF //
3042// //
3043// Description: Set control names to tune to requested RF_IN frequency //
3044// //
3045// Globals: //
3046// None //
3047// //
3048// Functions used: //
3049// MXL_SynthRFTGLO_Calc //
3050// MXL5005_ControlWrite //
3051// MXL_GetXtalInt //
3052// //
3053// Inputs: //
3054// Tuner : Tuner structure defined at higher level //
3055// //
3056// Outputs: //
3057// Tuner //
3058// //
3059// Return: //
3060// 0 : Successful //
3061// 1 : Unsuccessful //
3062///////////////////////////////////////////////////////////////////////////////
3063_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq)
3064{
3065 // Declare Local Variables
3066 _u16 status = 0 ;
3067 _u32 divider_val, E3, E4, E5, E5A ;
3068 _u32 Fmax, Fmin, FmaxBin, FminBin ;
3069 _u32 Kdbl_RF = 2;
3070 _u32 tg_divval ;
3071 _u32 tg_lo ;
3072 _u32 Xtal_Int ;
3073
3074 _u32 Fref_TG;
3075 _u32 Fvco;
3076// _u32 temp;
3077
3078
3079 Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ;
3080
3081 Tuner->RF_IN = RF_Freq ;
3082
3083 MXL_SynthRFTGLO_Calc( Tuner ) ;
3084
3085 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL)
3086 Kdbl_RF = 2 ;
3087 if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000)
3088 Kdbl_RF = 1 ;
3089
3090 //
3091 // Downconverter Controls
3092 //
3093 // Look-Up Table Implementation for:
3094 // DN_POLY
3095 // DN_RFGAIN
3096 // DN_CAP_RFLPF
3097 // DN_EN_VHFUHFBAR
3098 // DN_GAIN_ADJUST
3099 // Change the boundary reference from RF_IN to RF_LO
3100 if (Tuner->RF_LO < 40000000UL) {
3101 return -1;
3102 }
3103 if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) {
3104 // Look-Up Table implementation
3105 status += MXL_ControlWrite(Tuner, DN_POLY, 2) ;
3106 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
3107 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ;
3108 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
3109 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ;
3110 }
3111 if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) {
3112 // Look-Up Table implementation
3113 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
3114 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
3115 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ;
3116 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
3117 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ;
3118 }
3119 if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) {
3120 // Look-Up Table implementation
3121 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
3122 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
3123 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ;
3124 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
3125 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ;
3126 }
3127 if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) {
3128 // Look-Up Table implementation
3129 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
3130 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
3131 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ;
3132 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
3133 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ;
3134 }
3135 if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) {
3136 // Look-Up Table implementation
3137 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
3138 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ;
3139 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
3140 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ;
3141 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
3142 }
3143 if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) {
3144 // Look-Up Table implementation
3145 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
3146 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ;
3147 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
3148 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ;
3149 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
3150 }
3151 if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) {
3152 // Look-Up Table implementation
3153 status += MXL_ControlWrite(Tuner, DN_POLY, 3) ;
3154 status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ;
3155 status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ;
3156 status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ;
3157 status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ;
3158 }
3159 if (Tuner->RF_LO > 900000000UL) {
3160 return -1;
3161 }
3162 // DN_IQTNBUF_AMP
3163 // DN_IQTNGNBFBIAS_BST
3164 if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) {
3165 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3166 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3167 }
3168 if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) {
3169 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3170 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3171 }
3172 if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) {
3173 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3174 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3175 }
3176 if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) {
3177 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3178 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3179 }
3180 if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) {
3181 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3182 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3183 }
3184 if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) {
3185 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3186 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3187 }
3188 if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) {
3189 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3190 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3191 }
3192 if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) {
3193 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3194 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3195 }
3196 if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) {
3197 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3198 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3199 }
3200 if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) {
3201 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3202 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3203 }
3204 if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) {
3205 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3206 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3207 }
3208 if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) {
3209 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3210 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3211 }
3212 if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) {
3213 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3214 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3215 }
3216 if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) {
3217 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ;
3218 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ;
3219 }
3220 if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) {
3221 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ;
3222 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ;
3223 }
3224 if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) {
3225 status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ;
3226 status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ;
3227 }
3228
3229 //
3230 // Set RF Synth and LO Path Control
3231 //
3232 // Look-Up table implementation for:
3233 // RFSYN_EN_OUTMUX
3234 // RFSYN_SEL_VCO_OUT
3235 // RFSYN_SEL_VCO_HI
3236 // RFSYN_SEL_DIVM
3237 // RFSYN_RF_DIV_BIAS
3238 // DN_SEL_FREQ
3239 //
3240 // Set divider_val, Fmax, Fmix to use in Equations
3241 FminBin = 28000000UL ;
3242 FmaxBin = 42500000UL ;
3243 if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) {
3244 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
3245 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
3246 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
3247 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3248 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3249 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
3250 divider_val = 64 ;
3251 Fmax = FmaxBin ;
3252 Fmin = FminBin ;
3253 }
3254 FminBin = 42500000UL ;
3255 FmaxBin = 56000000UL ;
3256 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3257 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
3258 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
3259 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
3260 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3261 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3262 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
3263 divider_val = 64 ;
3264 Fmax = FmaxBin ;
3265 Fmin = FminBin ;
3266 }
3267 FminBin = 56000000UL ;
3268 FmaxBin = 85000000UL ;
3269 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3270 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3271 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3272 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
3273 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3274 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3275 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
3276 divider_val = 32 ;
3277 Fmax = FmaxBin ;
3278 Fmin = FminBin ;
3279 }
3280 FminBin = 85000000UL ;
3281 FmaxBin = 112000000UL ;
3282 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3283 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3284 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3285 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
3286 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3287 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3288 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ;
3289 divider_val = 32 ;
3290 Fmax = FmaxBin ;
3291 Fmin = FminBin ;
3292 }
3293 FminBin = 112000000UL ;
3294 FmaxBin = 170000000UL ;
3295 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3296 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3297 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3298 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
3299 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3300 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3301 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ;
3302 divider_val = 16 ;
3303 Fmax = FmaxBin ;
3304 Fmin = FminBin ;
3305 }
3306 FminBin = 170000000UL ;
3307 FmaxBin = 225000000UL ;
3308 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3309 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3310 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3311 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
3312 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3313 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3314 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ;
3315 divider_val = 16 ;
3316 Fmax = FmaxBin ;
3317 Fmin = FminBin ;
3318 }
3319 FminBin = 225000000UL ;
3320 FmaxBin = 300000000UL ;
3321 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3322 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3323 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3324 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
3325 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3326 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3327 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ;
3328 divider_val = 8 ;
3329 Fmax = 340000000UL ;
3330 Fmin = FminBin ;
3331 }
3332 FminBin = 300000000UL ;
3333 FmaxBin = 340000000UL ;
3334 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3335 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
3336 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
3337 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
3338 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3339 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3340 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
3341 divider_val = 8 ;
3342 Fmax = FmaxBin ;
3343 Fmin = 225000000UL ;
3344 }
3345 FminBin = 340000000UL ;
3346 FmaxBin = 450000000UL ;
3347 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3348 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ;
3349 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ;
3350 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
3351 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ;
3352 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ;
3353 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
3354 divider_val = 8 ;
3355 Fmax = FmaxBin ;
3356 Fmin = FminBin ;
3357 }
3358 FminBin = 450000000UL ;
3359 FmaxBin = 680000000UL ;
3360 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3361 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3362 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3363 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ;
3364 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ;
3365 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3366 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
3367 divider_val = 4 ;
3368 Fmax = FmaxBin ;
3369 Fmin = FminBin ;
3370 }
3371 FminBin = 680000000UL ;
3372 FmaxBin = 900000000UL ;
3373 if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) {
3374 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ;
3375 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ;
3376 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ;
3377 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ;
3378 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ;
3379 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ;
3380 divider_val = 4 ;
3381 Fmax = FmaxBin ;
3382 Fmin = FminBin ;
3383 }
3384
3385 // CHCAL_INT_MOD_RF
3386 // CHCAL_FRAC_MOD_RF
3387 // RFSYN_LPF_R
3388 // CHCAL_EN_INT_RF
3389
3390 // Equation E3
3391 // RFSYN_VCO_BIAS
3392 E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
3393 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ;
3394
3395 // Equation E4
3396 // CHCAL_INT_MOD_RF
3397 E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ;
3398 MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ;
3399
3400 // Equation E5
3401 // CHCAL_FRAC_MOD_RF
3402 // CHCAL_EN_INT_RF
3403 E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ;
3404 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ;
3405
3406 // Equation E5A
3407 // RFSYN_LPF_R
3408 E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
3409 status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ;
3410
3411 // Euqation E5B
3412 // CHCAL_EN_INIT_RF
3413 status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
3414 //if (E5 == 0)
3415 // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1);
3416 //else
3417 // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ;
3418
3419 //
3420 // Set TG Synth
3421 //
3422 // Look-Up table implementation for:
3423 // TG_LO_DIVVAL
3424 // TG_LO_SELVAL
3425 //
3426 // Set divider_val, Fmax, Fmix to use in Equations
3427 if (Tuner->TG_LO < 33000000UL) {
3428 return -1;
3429 }
3430 FminBin = 33000000UL ;
3431 FmaxBin = 50000000UL ;
3432 if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) {
3433 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ;
3434 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ;
3435 divider_val = 36 ;
3436 Fmax = FmaxBin ;
3437 Fmin = FminBin ;
3438 }
3439 FminBin = 50000000UL ;
3440 FmaxBin = 67000000UL ;
3441 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3442 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ;
3443 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ;
3444 divider_val = 24 ;
3445 Fmax = FmaxBin ;
3446 Fmin = FminBin ;
3447 }
3448 FminBin = 67000000UL ;
3449 FmaxBin = 100000000UL ;
3450 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3451 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ;
3452 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
3453 divider_val = 18 ;
3454 Fmax = FmaxBin ;
3455 Fmin = FminBin ;
3456 }
3457 FminBin = 100000000UL ;
3458 FmaxBin = 150000000UL ;
3459 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3460 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
3461 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
3462 divider_val = 12 ;
3463 Fmax = FmaxBin ;
3464 Fmin = FminBin ;
3465 }
3466 FminBin = 150000000UL ;
3467 FmaxBin = 200000000UL ;
3468 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3469 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
3470 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ;
3471 divider_val = 8 ;
3472 Fmax = FmaxBin ;
3473 Fmin = FminBin ;
3474 }
3475 FminBin = 200000000UL ;
3476 FmaxBin = 300000000UL ;
3477 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3478 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
3479 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ;
3480 divider_val = 6 ;
3481 Fmax = FmaxBin ;
3482 Fmin = FminBin ;
3483 }
3484 FminBin = 300000000UL ;
3485 FmaxBin = 400000000UL ;
3486 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3487 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
3488 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ;
3489 divider_val = 4 ;
3490 Fmax = FmaxBin ;
3491 Fmin = FminBin ;
3492 }
3493 FminBin = 400000000UL ;
3494 FmaxBin = 600000000UL ;
3495 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3496 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ;
3497 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ;
3498 divider_val = 3 ;
3499 Fmax = FmaxBin ;
3500 Fmin = FminBin ;
3501 }
3502 FminBin = 600000000UL ;
3503 FmaxBin = 900000000UL ;
3504 if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) {
3505 status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ;
3506 status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ;
3507 divider_val = 2 ;
3508 Fmax = FmaxBin ;
3509 Fmin = FminBin ;
3510 }
3511
3512 // TG_DIV_VAL
3513 tg_divval = (Tuner->TG_LO*divider_val/100000)
3514 *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ;
3515 status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ;
3516
3517 if (Tuner->TG_LO > 600000000UL)
3518 status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ;
3519
3520 Fmax = 1800000000UL ;
3521 Fmin = 1200000000UL ;
3522
3523
3524
3525 // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4
3526 Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000
3527
3528 Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10
3529
3530 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
3531
3532 //below equation is same as above but much harder to debug.
3533 //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ;
3534
3535
3536 status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ;
3537
3538
3539
3540 //add for 2.6.5
3541 //Special setting for QAM
3542 if(Tuner ->Mod_Type == MXL_QAM)
3543 {
3544 if(Tuner->RF_IN < 680000000)
3545 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ;
3546 else
3547 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ;
3548 }
3549
3550
3551 //remove 20.48MHz setting for 2.6.10
3552
3553 //
3554 // Off Chip Tracking Filter Control
3555 //
3556 if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks
3557 {
3558 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ;
3559 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ;
3560
3561 status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1
3562 status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2
3563 status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3
3564 }
3565
3566 if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C
3567 {
3568 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ;
3569 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
3570
3571 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000)
3572 {
3573
3574 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3575 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3576 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On
3577 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3578 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3579 }
3580 if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000)
3581 {
3582 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3583 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3584 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3585 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3586 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3587 }
3588 if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000)
3589 {
3590 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3591 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3592 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3593 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3594 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3595 }
3596 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000)
3597 {
3598 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3599 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3600 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3601 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3602 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3603 }
3604 if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000)
3605 {
3606 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3607 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ;
3608 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3609 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3610 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3611 }
3612 if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000)
3613 {
3614 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3615 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3616 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3617 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3618 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On
3619 }
3620 if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000)
3621 {
3622 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3623 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ;
3624 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3625 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3626 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3627 }
3628 if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000)
3629 {
3630 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3631 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ;
3632 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3633 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3634 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3635 }
3636 if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
3637 {
3638 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3639 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3640 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off
3641 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3642 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off
3643 }
3644 }
3645
3646 if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
3647 {
3648 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
3649
3650 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000)
3651 {
3652
3653 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3654 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3655 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3656 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3657 }
3658 if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000)
3659 {
3660 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3661 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3662 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On
3663 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3664 }
3665 if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000)
3666 {
3667 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3668 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3669 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On
3670 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3671 }
3672 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000)
3673 {
3674 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3675 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3676 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3677 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3678 }
3679 if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000)
3680 {
3681 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3682 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3683 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3684 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3685 }
3686 if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000)
3687 {
3688 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3689 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3690 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3691 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On
3692 }
3693 if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000)
3694 {
3695 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3696 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3697 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3698 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3699 }
3700 if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000)
3701 {
3702 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3703 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3704 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3705 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3706 }
3707 if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
3708 {
3709 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3710 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3711 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off
3712 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off
3713 }
3714 }
3715
3716 if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D
3717 {
3718 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3719
3720 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
3721 {
3722
3723 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3724 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3725 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3726 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3727 }
3728 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
3729 {
3730 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3731 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3732 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3733 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3734 }
3735 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000)
3736 {
3737 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3738 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3739 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3740 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3741 }
3742 if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000)
3743 {
3744 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3745 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3746 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3747 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3748 }
3749 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000)
3750 {
3751 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3752 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3753 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3754 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3755 }
3756 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000)
3757 {
3758 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3759 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3760 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3761 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3762 }
3763 if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000)
3764 {
3765 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3766 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3767 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3768 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3769 }
3770 }
3771
3772
3773 if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3
3774 {
3775 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
3776
3777 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter
3778 {
3779 // Turn off all the banks
3780 status += MXL_SetGPIO(Tuner, 3, 1) ;
3781 status += MXL_SetGPIO(Tuner, 1, 1) ;
3782 status += MXL_SetGPIO(Tuner, 4, 1) ;
3783 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ;
3784
3785 status += MXL_ControlWrite(Tuner, AGC_IF, 10) ;
3786 }
3787
3788 else // if VHF or cable => Turn on Tracking Filter
3789 {
3790 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000)
3791 {
3792
3793 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3794 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On
3795 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3796 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off
3797 }
3798 if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000)
3799 {
3800 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3801 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On
3802 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3803 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off
3804 }
3805 if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000)
3806 {
3807 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3808 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3809 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On
3810 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off
3811 }
3812 if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000)
3813 {
3814 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off
3815 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3816 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3817 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On
3818 }
3819 if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000)
3820 {
3821 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off
3822 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3823 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off
3824 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On
3825 }
3826 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000)
3827 {
3828 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3829 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3830 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off
3831 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On
3832 }
3833 if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000)
3834 {
3835 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On
3836 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3837 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3838 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq
3839 }
3840 if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000)
3841 {
3842 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3843 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off
3844 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3845 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3846 }
3847 if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000)
3848 {
3849 status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On
3850 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3851 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3852 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3853 }
3854 }
3855 }
3856
3857 if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E
3858 {
3859 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3860
3861 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
3862 {
3863
3864 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3865 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3866 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3867 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3868 }
3869 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
3870 {
3871 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3872 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3873 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3874 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3875 }
3876 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000)
3877 {
3878 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3879 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3880 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3881 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3882 }
3883 if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000)
3884 {
3885 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3886 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3887 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3888 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3889 }
3890 if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000)
3891 {
3892 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3893 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3894 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3895 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3896 }
3897 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000)
3898 {
3899 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3900 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3901 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3902 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3903 }
3904 if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000)
3905 {
3906 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3907 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3908 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3909 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3910 }
3911 }
3912
3913 if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F
3914 {
3915 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3916
3917 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000)
3918 {
3919
3920 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3921 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3922 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3923 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3924 }
3925 if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000)
3926 {
3927 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3928 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3929 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3930 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3931 }
3932 if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000)
3933 {
3934 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3935 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3936 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3937 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3938 }
3939 if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000)
3940 {
3941 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3942 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3943 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3944 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3945 }
3946 if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000)
3947 {
3948 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3949 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3950 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3951 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3952 }
3953 if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000)
3954 {
3955 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3956 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3957 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3958 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
3959 }
3960 if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000)
3961 {
3962 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
3963 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3964 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3965 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3966 }
3967 }
3968
3969 if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2
3970 {
3971 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
3972
3973 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
3974 {
3975
3976 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3977 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3978 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
3979 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3980 }
3981 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
3982 {
3983 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3984 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
3985 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3986 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3987 }
3988 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000)
3989 {
3990 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3991 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3992 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
3993 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
3994 }
3995 if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000)
3996 {
3997 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
3998 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
3999 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
4000 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4001 }
4002 if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000)
4003 {
4004 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4005 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4006 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4007 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4008 }
4009 if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000)
4010 {
4011 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
4012 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4013 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4014 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4015 }
4016 if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000)
4017 {
4018 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
4019 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4020 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4021 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4022 }
4023 }
4024
4025 if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8
4026 {
4027 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
4028
4029 if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000)
4030 {
4031
4032 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4033 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
4034 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4035 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4036 }
4037 if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000)
4038 {
4039 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4040 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
4041 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
4042 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4043 }
4044 if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000)
4045 {
4046 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4047 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4048 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
4049 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4050 }
4051 if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000)
4052 {
4053 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4054 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4055 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
4056 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4057 }
4058 if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11
4059 {
4060 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
4061 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On
4062 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off
4063 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4064 }
4065 if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000)
4066 {
4067 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4068 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4069 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4070 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4071 }
4072 if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000)
4073 {
4074 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
4075 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4076 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4077 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4078 }
4079 if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000)
4080 {
4081 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
4082 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4083 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4084 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4085 }
4086 }
4087
4088 if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8
4089 {
4090 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
4091
4092 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter
4093 {
4094 // Turn off all the banks
4095 status += MXL_SetGPIO(Tuner, 3, 1) ;
4096 status += MXL_SetGPIO(Tuner, 1, 1) ;
4097 status += MXL_SetGPIO(Tuner, 4, 1) ;
4098 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ;
4099
4100 //2.6.12
4101 //Turn on RSSI
4102 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
4103 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
4104 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ;
4105 status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ;
4106
4107 // RSSI reference point
4108 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ;
4109 status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ;
4110 status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ;
4111
4112
4113 //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on
4114
4115 //following parameter is from analog OTA mode, can be change to seek better performance
4116 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ;
4117 }
4118
4119 else //if VHF or Cable => Turn on Tracking Filter
4120 {
4121 //2.6.12
4122 //Turn off RSSI
4123 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
4124
4125 //change back from above condition
4126 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ;
4127
4128
4129 if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000)
4130 {
4131
4132 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4133 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
4134 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4135 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4136 }
4137 if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000)
4138 {
4139 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4140 status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On
4141 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
4142 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4143 }
4144 if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000)
4145 {
4146 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4147 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4148 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
4149 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4150 }
4151 if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000)
4152 {
4153 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4154 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4155 status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On
4156 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4157 }
4158 if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000)
4159 {
4160 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off
4161 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4162 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4163 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4164 }
4165 if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000)
4166 {
4167 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
4168 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4169 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4170 status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On
4171 }
4172 if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000)
4173 {
4174 status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On
4175 status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off
4176 status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off
4177 status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off
4178 }
4179 }
4180 }
4181 return status ;
4182}
4183
4184_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val)
4185{
4186 _u16 status = 0 ;
4187
4188 if (GPIO_Num == 1)
4189 status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ;
4190 // GPIO2 is not available
4191 if (GPIO_Num == 3)
4192 {
4193 if (GPIO_Val == 1) {
4194 status += MXL_ControlWrite(Tuner, GPIO_3, 0) ;
4195 status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ;
4196 }
4197 if (GPIO_Val == 0) {
4198 status += MXL_ControlWrite(Tuner, GPIO_3, 1) ;
4199 status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ;
4200 }
4201 if (GPIO_Val == 3) { // tri-state
4202 status += MXL_ControlWrite(Tuner, GPIO_3, 0) ;
4203 status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ;
4204 }
4205 }
4206 if (GPIO_Num == 4)
4207 {
4208 if (GPIO_Val == 1) {
4209 status += MXL_ControlWrite(Tuner, GPIO_4, 0) ;
4210 status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ;
4211 }
4212 if (GPIO_Val == 0) {
4213 status += MXL_ControlWrite(Tuner, GPIO_4, 1) ;
4214 status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ;
4215 }
4216 if (GPIO_Val == 3) { // tri-state
4217 status += MXL_ControlWrite(Tuner, GPIO_4, 0) ;
4218 status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ;
4219 }
4220 }
4221
4222 return status ;
4223}
4224
4225///////////////////////////////////////////////////////////////////////////////
4226// //
4227// Function: MXL_ControlWrite //
4228// //
4229// Description: Update control name value //
4230// //
4231// Globals: //
4232// NONE //
4233// //
4234// Functions used: //
4235// MXL_ControlWrite( Tuner, controlName, value, Group ) //
4236// //
4237// Inputs: //
4238// Tuner : Tuner structure //
4239// ControlName : Control name to be updated //
4240// value : Value to be written //
4241// //
4242// Outputs: //
4243// Tuner : Tuner structure defined at higher level //
4244// //
4245// Return: //
4246// 0 : Successful write //
4247// >0 : Value exceed maximum allowed for control number //
4248// //
4249///////////////////////////////////////////////////////////////////////////////
4250_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value)
4251{
4252 _u16 status = 0 ;
4253 // Will write ALL Matching Control Name
4254 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control
4255 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control
4256#ifdef _MXL_INTERNAL
4257 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control
4258#endif
4259
4260 return status ;
4261}
4262
4263///////////////////////////////////////////////////////////////////////////////
4264// //
4265// Function: MXL_ControlWrite //
4266// //
4267// Description: Update control name value //
4268// //
4269// Globals: //
4270// NONE //
4271// //
4272// Functions used: //
4273// strcmp //
4274// //
4275// Inputs: //
4276// Tuner_struct: structure defined at higher level //
4277// ControlName : Control Name //
4278// value : Value Assigned to Control Name //
4279// controlGroup : Control Register Group //
4280// //
4281// Outputs: //
4282// NONE //
4283// //
4284// Return: //
4285// 0 : Successful write //
4286// 1 : Value exceed maximum allowed for control name //
4287// 2 : Control name not found //
4288// //
4289///////////////////////////////////////////////////////////////////////////////
4290_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup)
4291{
4292 _u16 i, j, k ;
4293 _u32 highLimit ;
4294 _u32 ctrlVal ;
4295
4296 if( controlGroup == 1) // Initial Control
4297 {
4298 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
4299 {
4300 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num )
4301 { // find the control Name
4302 highLimit = 1 << Tuner->Init_Ctrl[i].size ;
4303 if ( value < highLimit)
4304 {
4305 for( j=0; j<Tuner->Init_Ctrl[i].size; j++)
4306 {
4307 Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ;
4308 // change the register map accordingly
4309 MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]),
4310 (_u8)(Tuner->Init_Ctrl[i].bit[j]),
4311 (_u8)((value>>j) & 0x01) ) ;
4312 }
4313 ctrlVal = 0 ;
4314 for(k=0; k<Tuner->Init_Ctrl[i].size; k++)
4315 {
4316 ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ;
4317 }
4318 }
4319 else
4320 {
4321 return -1 ;
4322 }
4323 }
4324 }
4325 }
4326 if ( controlGroup == 2) // Chan change Control
4327 {
4328 for (i=0; i<Tuner->CH_Ctrl_Num; i++)
4329 {
4330 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num )
4331 { // find the control Name
4332 highLimit = 1 << Tuner->CH_Ctrl[i].size ;
4333 if ( value < highLimit)
4334 {
4335 for( j=0; j<Tuner->CH_Ctrl[i].size; j++)
4336 {
4337 Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ;
4338 // change the register map accordingly
4339 MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]),
4340 (_u8)(Tuner->CH_Ctrl[i].bit[j]),
4341 (_u8)((value>>j) & 0x01) ) ;
4342 }
4343 ctrlVal = 0 ;
4344 for(k=0; k<Tuner->CH_Ctrl[i].size; k++)
4345 {
4346 ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ;
4347 }
4348 }
4349 else
4350 {
4351 return -1 ;
4352 }
4353 }
4354 }
4355 }
4356#ifdef _MXL_INTERNAL
4357 if ( controlGroup == 3) // Maxlinear Control
4358 {
4359 for (i=0; i<Tuner->MXL_Ctrl_Num; i++)
4360 {
4361 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num )
4362 { // find the control Name
4363 highLimit = (1 << Tuner->MXL_Ctrl[i].size) ;
4364 if ( value < highLimit)
4365 {
4366 for( j=0; j<Tuner->MXL_Ctrl[i].size; j++)
4367 {
4368 Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ;
4369 // change the register map accordingly
4370 MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]),
4371 (_u8)(Tuner->MXL_Ctrl[i].bit[j]),
4372 (_u8)((value>>j) & 0x01) ) ;
4373 }
4374 ctrlVal = 0 ;
4375 for(k=0; k<Tuner->MXL_Ctrl[i].size; k++)
4376 {
4377 ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ;
4378 }
4379 }
4380 else
4381 {
4382 return -1 ;
4383 }
4384 }
4385 }
4386 }
4387#endif
4388 return 0 ; // successful return
4389}
4390
4391///////////////////////////////////////////////////////////////////////////////
4392// //
4393// Function: MXL_RegWrite //
4394// //
4395// Description: Update tuner register value //
4396// //
4397// Globals: //
4398// NONE //
4399// //
4400// Functions used: //
4401// NONE //
4402// //
4403// Inputs: //
4404// Tuner_struct: structure defined at higher level //
4405// RegNum : Register address to be assigned a value //
4406// RegVal : Register value to write //
4407// //
4408// Outputs: //
4409// NONE //
4410// //
4411// Return: //
4412// 0 : Successful write //
4413// -1 : Invalid Register Address //
4414// //
4415///////////////////////////////////////////////////////////////////////////////
4416_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal)
4417{
4418 int i ;
4419
4420 for (i=0; i<104; i++)
4421 {
4422 if (RegNum == Tuner->TunerRegs[i].Reg_Num )
4423 {
4424 Tuner->TunerRegs[i].Reg_Val = RegVal ;
4425 return 0 ;
4426 }
4427 }
4428
4429 return 1 ;
4430}
4431
4432///////////////////////////////////////////////////////////////////////////////
4433// //
4434// Function: MXL_RegRead //
4435// //
4436// Description: Retrieve tuner register value //
4437// //
4438// Globals: //
4439// NONE //
4440// //
4441// Functions used: //
4442// NONE //
4443// //
4444// Inputs: //
4445// Tuner_struct: structure defined at higher level //
4446// RegNum : Register address to be assigned a value //
4447// //
4448// Outputs: //
4449// RegVal : Retrieved register value //
4450// //
4451// Return: //
4452// 0 : Successful read //
4453// -1 : Invalid Register Address //
4454// //
4455///////////////////////////////////////////////////////////////////////////////
4456_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal)
4457{
4458 int i ;
4459
4460 for (i=0; i<104; i++)
4461 {
4462 if (RegNum == Tuner->TunerRegs[i].Reg_Num )
4463 {
4464 *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ;
4465 return 0 ;
4466 }
4467 }
4468
4469 return 1 ;
4470}
4471
4472///////////////////////////////////////////////////////////////////////////////
4473// //
4474// Function: MXL_ControlRead //
4475// //
4476// Description: Retrieve the control value based on the control name //
4477// //
4478// Globals: //
4479// NONE //
4480// //
4481// Inputs: //
4482// Tuner_struct : structure defined at higher level //
4483// ControlName : Control Name //
4484// //
4485// Outputs: //
4486// value : returned control value //
4487// //
4488// Return: //
4489// 0 : Successful read //
4490// -1 : Invalid control name //
4491// //
4492///////////////////////////////////////////////////////////////////////////////
4493_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value)
4494{
4495 _u32 ctrlVal ;
4496 _u16 i, k ;
4497
4498 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
4499 {
4500 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num )
4501 {
4502 ctrlVal = 0 ;
4503 for(k=0; k<Tuner->Init_Ctrl[i].size; k++)
4504 ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ;
4505 *value = ctrlVal ;
4506 return 0 ;
4507 }
4508 }
4509 for (i=0; i<Tuner->CH_Ctrl_Num ; i++)
4510 {
4511 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num )
4512 {
4513 ctrlVal = 0 ;
4514 for(k=0; k<Tuner->CH_Ctrl[i].size; k++)
4515 ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ;
4516 *value = ctrlVal ;
4517 return 0 ;
4518 }
4519 }
4520
4521#ifdef _MXL_INTERNAL
4522 for (i=0; i<Tuner->MXL_Ctrl_Num ; i++)
4523 {
4524 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num )
4525 {
4526 ctrlVal = 0 ;
4527 for(k=0; k<Tuner->MXL_Ctrl[i].size; k++)
4528 ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<<k) ;
4529 *value = ctrlVal ;
4530 return 0 ;
4531 }
4532 }
4533#endif
4534 return 1 ;
4535}
4536
4537///////////////////////////////////////////////////////////////////////////////
4538// //
4539// Function: MXL_ControlRegRead //
4540// //
4541// Description: Retrieve the register addresses and count related to a //
4542// a specific control name //
4543// //
4544// Globals: //
4545// NONE //
4546// //
4547// Inputs: //
4548// Tuner_struct : structure defined at higher level //
4549// ControlName : Control Name //
4550// //
4551// Outputs: //
4552// RegNum : returned register address array //
4553// count : returned register count related to a control //
4554// //
4555// Return: //
4556// 0 : Successful read //
4557// -1 : Invalid control name //
4558// //
4559///////////////////////////////////////////////////////////////////////////////
4560_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * count)
4561{
4562 _u16 i, j, k ;
4563 _u16 Count ;
4564
4565 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
4566 {
4567 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num )
4568 {
4569 Count = 1 ;
4570 RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ;
4571
4572 for(k=1; k<Tuner->Init_Ctrl[i].size; k++)
4573 {
4574 for (j= 0; j<Count; j++)
4575 {
4576 if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j])
4577 {
4578 Count ++ ;
4579 RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ;
4580 }
4581 }
4582
4583 }
4584 *count = Count ;
4585 return 0 ;
4586 }
4587 }
4588 for (i=0; i<Tuner->CH_Ctrl_Num ; i++)
4589 {
4590 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num )
4591 {
4592 Count = 1 ;
4593 RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ;
4594
4595 for(k=1; k<Tuner->CH_Ctrl[i].size; k++)
4596 {
4597 for (j= 0; j<Count; j++)
4598 {
4599 if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j])
4600 {
4601 Count ++ ;
4602 RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ;
4603 }
4604 }
4605 }
4606 *count = Count ;
4607 return 0 ;
4608 }
4609 }
4610#ifdef _MXL_INTERNAL
4611 for (i=0; i<Tuner->MXL_Ctrl_Num ; i++)
4612 {
4613 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num )
4614 {
4615 Count = 1 ;
4616 RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ;
4617
4618 for(k=1; k<Tuner->MXL_Ctrl[i].size; k++)
4619 {
4620 for (j= 0; j<Count; j++)
4621 {
4622 if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j])
4623 {
4624 Count ++ ;
4625 RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ;
4626 }
4627 }
4628 }
4629 *count = Count ;
4630 return 0 ;
4631 }
4632 }
4633#endif
4634 *count = 0 ;
4635 return 1 ;
4636}
4637
4638///////////////////////////////////////////////////////////////////////////////
4639// //
4640// Function: MXL_RegWriteBit //
4641// //
4642// Description: Write a register for specified register address, //
4643// register bit and register bit value //
4644// //
4645// Globals: //
4646// NONE //
4647// //
4648// Inputs: //
4649// Tuner_struct : structure defined at higher level //
4650// address : register address //
4651// bit : register bit number //
4652// bitVal : register bit value //
4653// //
4654// Outputs: //
4655// NONE //
4656// //
4657// Return: //
4658// NONE //
4659// //
4660///////////////////////////////////////////////////////////////////////////////
4661
4662void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal)
4663{
4664 int i ;
4665
4666 // Declare Local Constants
4667 const _u8 AND_MAP[8] = {
4668 0xFE, 0xFD, 0xFB, 0xF7,
4669 0xEF, 0xDF, 0xBF, 0x7F } ;
4670
4671 const _u8 OR_MAP[8] = {
4672 0x01, 0x02, 0x04, 0x08,
4673 0x10, 0x20, 0x40, 0x80 } ;
4674
4675 for(i=0; i<Tuner->TunerRegs_Num; i++) {
4676 if ( Tuner->TunerRegs[i].Reg_Num == address ) {
4677 if (bitVal)
4678 Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ;
4679 else
4680 Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ;
4681 break ;
4682 }
4683 }
4684} ;
4685
4686
4687///////////////////////////////////////////////////////////////////////////////
4688// //
4689// Function: MXL_Ceiling //
4690// //
4691// Description: Complete to closest increment of resolution //
4692// //
4693// Globals: //
4694// NONE //
4695// //
4696// Functions used: //
4697// NONE //
4698// //
4699// Inputs: //
4700// value : Input number to compute //
4701// resolution : Increment step //
4702// //
4703// Outputs: //
4704// NONE //
4705// //
4706// Return: //
4707// Computed value //
4708// //
4709///////////////////////////////////////////////////////////////////////////////
4710_u32 MXL_Ceiling( _u32 value, _u32 resolution )
4711{
4712 return (value/resolution + (value%resolution > 0 ? 1 : 0)) ;
4713};
4714
4715//
4716// Retrieve the Initialzation Registers
4717//
4718_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count)
4719{
4720 _u16 status = 0;
4721 int i ;
4722
4723 _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
4724 76, 77, 91, 134, 135, 137, 147,
4725 156, 166, 167, 168, 25 } ;
4726 *count = sizeof(RegAddr) / sizeof(_u8) ;
4727
4728 status += MXL_BlockInit(Tuner) ;
4729
4730 for (i=0 ; i< *count; i++)
4731 {
4732 RegNum[i] = RegAddr[i] ;
4733 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4734 }
4735
4736 return status ;
4737}
4738
4739_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count)
4740{
4741 _u16 status = 0;
4742 int i ;
4743
4744//add 77, 166, 167, 168 register for 2.6.12
4745#ifdef _MXL_PRODUCTION
4746 _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
4747 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4748#else
4749 _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
4750 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4751 //_u8 RegAddr[171];
4752 //for (i=0; i<=170; i++)
4753 // RegAddr[i] = i;
4754#endif
4755
4756 *count = sizeof(RegAddr) / sizeof(_u8) ;
4757
4758 for (i=0 ; i< *count; i++)
4759 {
4760 RegNum[i] = RegAddr[i] ;
4761 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4762 }
4763
4764 return status ;
4765
4766}
4767
4768_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count)
4769{
4770 _u16 status = 0 ;
4771 int i ;
4772
4773 _u8 RegAddr[] = {43, 136} ;
4774
4775 *count = sizeof(RegAddr) / sizeof(_u8) ;
4776
4777 for (i=0; i<*count; i++)
4778 {
4779 RegNum[i] = RegAddr[i] ;
4780 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4781 }
4782 return status ;
4783
4784}
4785
4786_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count)
4787{
4788 _u16 status = 0 ;
4789 int i ;
4790
4791 _u8 RegAddr[] = {138} ;
4792
4793 *count = sizeof(RegAddr) / sizeof(_u8) ;
4794
4795 for (i=0; i<*count; i++)
4796 {
4797 RegNum[i] = RegAddr[i] ;
4798 status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ;
4799 }
4800 return status ;
4801
4802}
4803
4804_u16 MXL_GetMasterControl(_u8 *MasterReg, int state)
4805{
4806 if (state == 1) // Load_Start
4807 *MasterReg = 0xF3 ;
4808 if (state == 2) // Power_Down
4809 *MasterReg = 0x41 ;
4810 if (state == 3) // Synth_Reset
4811 *MasterReg = 0xB1 ;
4812 if (state == 4) // Seq_Off
4813 *MasterReg = 0xF1 ;
4814
4815 return 0 ;
4816}
4817
4818#ifdef _MXL_PRODUCTION
4819_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range)
4820{
4821 _u16 status = 0 ;
4822
4823 if (VCO_Range == 1) {
4824 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4825 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4826 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4827 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4828 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4829 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4830 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4831 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4832 {
4833 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4834 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4835 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4836 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ;
4837 }
4838 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4839 {
4840 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4841 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4842 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4843 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ;
4844 }
4845 if (Tuner->Mode == 1) // Digital Mode
4846 {
4847 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4848 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4849 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4850 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ;
4851 }
4852 }
4853
4854 if (VCO_Range == 2) {
4855 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4856 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4857 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4858 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4859 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4860 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4861 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4862 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4863 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4864 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ;
4865 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4866 {
4867 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4868 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4869 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4870 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4871 }
4872 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4873 {
4874 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4875 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4876 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4877 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4878 }
4879 if (Tuner->Mode == 1) // Digital Mode
4880 {
4881 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4882 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4883 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ;
4884 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ;
4885 }
4886 }
4887
4888 if (VCO_Range == 3) {
4889 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4890 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4891 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4892 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4893 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4894 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4895 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4896 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4897 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4898 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4899 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4900 {
4901 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4902 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4903 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ;
4904 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ;
4905 }
4906 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4907 {
4908 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4909 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4910 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ;
4911 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ;
4912 }
4913 if (Tuner->Mode == 1) // Digital Mode
4914 {
4915 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4916 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4917 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4918 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ;
4919 }
4920 }
4921
4922 if (VCO_Range == 4) {
4923 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4924 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4925 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4926 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4927 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4928 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4929 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4930 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4931 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4932 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4933 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4934 {
4935 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4936 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4937 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4938 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4939 }
4940 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4941 {
4942 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4943 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4944 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4945 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4946 }
4947 if (Tuner->Mode == 1) // Digital Mode
4948 {
4949 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4950 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4951 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4952 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ;
4953 }
4954 }
4955
4956 return status ;
4957}
4958
4959_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis)
4960{
4961 _u16 status = 0 ;
4962
4963 if (Hystersis == 1)
4964 status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ;
4965
4966 return status ;
4967}
4968#endif
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