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review.evervolv.com / android_kernel_htc_msm8960 / 26512dea431f8347a8bbce561982df939225e2c6 / . / arch / arm / mach-msm / board-fsm9xxx.c
blob: 2f90d78866a3ad485b4d9bd94de6631c59d88094 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/gpio.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/mfd/pmic8058.h>
20#include <linux/regulator/pmic8058-regulator.h>
21#include <linux/i2c.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmapool.h>
24#include <linux/regulator/pm8058-xo.h>
25
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/setup.h>
29
30#include <mach/mpp.h>
31#include <mach/board.h>
32#include <mach/memory.h>
33#include <mach/msm_iomap.h>
34#include <mach/dma.h>
35#include <mach/sirc.h>
36#include <mach/pmic.h>
37
38#include <mach/vreg.h>
39#include <mach/socinfo.h>
40#include "devices.h"
41#include "timer.h"
42#include "pm.h"
43#include "spm.h"
44#include <linux/regulator/consumer.h>
45#include <linux/regulator/machine.h>
46#include <linux/msm_adc.h>
47#include <linux/pmic8058-xoadc.h>
48#include <linux/m_adcproc.h>
49#include <linux/platform_data/qcom_crypto_device.h>
50
51#define PMIC_GPIO_INT 144
52#define PMIC_VREG_WLAN_LEVEL 2900
53#define PMIC_GPIO_SD_DET 165
54
55#define GPIO_EPHY_RST_N 37
56
57#define GPIO_GRFC_FTR0_0 136 /* GRFC 20 */
58#define GPIO_GRFC_FTR0_1 137 /* GRFC 21 */
59#define GPIO_GRFC_FTR1_0 145 /* GRFC 22 */
60#define GPIO_GRFC_FTR1_1 93 /* GRFC 19 */
61#define GPIO_GRFC_2 110
62#define GPIO_GRFC_3 109
63#define GPIO_GRFC_4 108
64#define GPIO_GRFC_5 107
65#define GPIO_GRFC_6 106
66#define GPIO_GRFC_7 105
67#define GPIO_GRFC_8 104
68#define GPIO_GRFC_9 103
69#define GPIO_GRFC_10 102
70#define GPIO_GRFC_11 101
71#define GPIO_GRFC_13 99
72#define GPIO_GRFC_14 98
73#define GPIO_GRFC_15 97
74#define GPIO_GRFC_16 96
75#define GPIO_GRFC_17 95
76#define GPIO_GRFC_18 94
77#define GPIO_GRFC_24 150
78#define GPIO_GRFC_25 151
79#define GPIO_GRFC_26 152
80#define GPIO_GRFC_27 153
81#define GPIO_GRFC_28 154
82#define GPIO_GRFC_29 155
83
Rohit Vaswani26512de2011-07-11 16:01:13 -0700[diff] [blame^]84#define GPIO_USER_FIRST 58
85#define GPIO_USER_LAST 63
86
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]87#define FPGA_SDCC_STATUS 0x8E0001A8
88
89/* Macros assume PMIC GPIOs start at 0 */
90#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_MSM_GPIOS)
91#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_MSM_GPIOS)
92
93#define PMIC_GPIO_5V_PA_PWR 21 /* PMIC GPIO Number 22 */
94#define PMIC_GPIO_4_2V_PA_PWR 22 /* PMIC GPIO Number 23 */
95#define PMIC_MPP_3 2 /* PMIC MPP Number 3 */
96#define PMIC_MPP_6 5 /* PMIC MPP Number 6 */
97#define PMIC_MPP_7 6 /* PMIC MPP Number 7 */
98#define PMIC_MPP_10 9 /* PMIC MPP Number 10 */
99
100/*
101 * PM8058
102 */
103
104static int pm8058_gpios_init(void)
105{
106 int i;
107 int rc;
108 struct pm8058_gpio_cfg {
109 int gpio;
110 struct pm8058_gpio cfg;
111 };
112
113 struct pm8058_gpio_cfg gpio_cfgs[] = {
114 { /* 5V PA Power */
115 PMIC_GPIO_5V_PA_PWR,
116 {
117 .vin_sel = 0,
118 .direction = PM_GPIO_DIR_BOTH,
119 .output_value = 1,
120 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
121 .pull = PM_GPIO_PULL_DN,
122 .out_strength = PM_GPIO_STRENGTH_HIGH,
123 .function = PM_GPIO_FUNC_NORMAL,
124 .inv_int_pol = 0,
125 },
126 },
127 { /* 4.2V PA Power */
128 PMIC_GPIO_4_2V_PA_PWR,
129 {
130 .vin_sel = 0,
131 .direction = PM_GPIO_DIR_BOTH,
132 .output_value = 1,
133 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
134 .pull = PM_GPIO_PULL_DN,
135 .out_strength = PM_GPIO_STRENGTH_HIGH,
136 .function = PM_GPIO_FUNC_NORMAL,
137 .inv_int_pol = 0,
138 },
139 },
140 };
141
142 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
143 rc = pm8058_gpio_config(gpio_cfgs[i].gpio, &gpio_cfgs[i].cfg);
144 if (rc < 0) {
145 pr_err("%s pmic gpio config failed\n", __func__);
146 return rc;
147 }
148 }
149
150 return 0;
151}
152
153static int pm8058_mpps_init(void)
154{
155 int rc;
156
157 /* Set up MPP 3 and 6 as analog outputs at 1.25V */
158 rc = pm8058_mpp_config_analog_output(PMIC_MPP_3,
159 PM_MPP_AOUT_LVL_1V25_2, PM_MPP_AOUT_CTL_ENABLE);
160 if (rc) {
161 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
162 return rc;
163 }
164
165 rc = pm8058_mpp_config_analog_output(PMIC_MPP_6,
166 PM_MPP_AOUT_LVL_1V25_2, PM_MPP_AOUT_CTL_ENABLE);
167 if (rc) {
168 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
169 return rc;
170 }
171 return 0;
172}
173
174static struct pm8058_gpio_platform_data pm8058_gpio_data = {
175 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
176 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
177 .init = pm8058_gpios_init,
178};
179
180static struct pm8058_gpio_platform_data pm8058_mpp_data = {
181 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
182 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
183 .init = pm8058_mpps_init,
184};
185
186static struct regulator_consumer_supply pm8058_vreg_supply[PM8058_VREG_MAX] = {
187 [PM8058_VREG_ID_L3] = REGULATOR_SUPPLY("8058_l3", NULL),
188 [PM8058_VREG_ID_L8] = REGULATOR_SUPPLY("8058_l8", NULL),
189 [PM8058_VREG_ID_L9] = REGULATOR_SUPPLY("8058_l9", NULL),
190 [PM8058_VREG_ID_L14] = REGULATOR_SUPPLY("8058_l14", NULL),
191 [PM8058_VREG_ID_L15] = REGULATOR_SUPPLY("8058_l15", NULL),
192 [PM8058_VREG_ID_L18] = REGULATOR_SUPPLY("8058_l18", NULL),
193 [PM8058_VREG_ID_S4] = REGULATOR_SUPPLY("8058_s4", NULL),
194
195 [PM8058_VREG_ID_LVS0] = REGULATOR_SUPPLY("8058_lvs0", NULL),
196};
197
198#define PM8058_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
199 _always_on, _pull_down) \
200 [_id] = { \
201 .init_data = { \
202 .constraints = { \
203 .valid_modes_mask = _modes, \
204 .valid_ops_mask = _ops, \
205 .min_uV = _min_uV, \
206 .max_uV = _max_uV, \
207 .apply_uV = _apply_uV, \
208 .always_on = _always_on, \
209 }, \
210 .num_consumer_supplies = 1, \
211 .consumer_supplies = &pm8058_vreg_supply[_id], \
212 }, \
213 .pull_down_enable = _pull_down, \
214 .pin_ctrl = 0, \
215 .pin_fn = PM8058_VREG_PIN_FN_ENABLE, \
216 }
217
218#define PM8058_VREG_INIT_LDO(_id, _min_uV, _max_uV) \
219 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \
220 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \
221 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \
222 REGULATOR_CHANGE_MODE, 1, 1, 1)
223
224#define PM8058_VREG_INIT_SMPS(_id, _min_uV, _max_uV) \
225 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \
226 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \
227 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \
228 REGULATOR_CHANGE_MODE, 1, 1, 1)
229
230#define PM8058_VREG_INIT_LVS(_id, _min_uV, _max_uV) \
231 PM8058_VREG_INIT(_id, _min_uV, _min_uV, REGULATOR_MODE_NORMAL, \
232 REGULATOR_CHANGE_STATUS, 0, 0, 1)
233
234static struct pm8058_vreg_pdata pm8058_vreg_init[PM8058_VREG_MAX] = {
235 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L3, 1800000, 1800000),
236 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L8, 2200000, 2200000),
237 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L9, 2050000, 2050000),
238 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L14, 2850000, 2850000),
239 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L15, 2200000, 2200000),
240 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L18, 2200000, 2200000),
241 PM8058_VREG_INIT_LVS(PM8058_VREG_ID_LVS0, 1800000, 1800000),
242 PM8058_VREG_INIT_SMPS(PM8058_VREG_ID_S4, 1300000, 1300000),
243};
244
245#define PM8058_VREG(_id) { \
246 .name = "pm8058-regulator", \
247 .id = _id, \
248 .platform_data = &pm8058_vreg_init[_id], \
249}
250
251#ifdef CONFIG_SENSORS_MSM_ADC
252static struct resource resources_adc[] = {
253 {
254 .start = PM8058_ADC_IRQ(PMIC8058_IRQ_BASE),
255 .end = PM8058_ADC_IRQ(PMIC8058_IRQ_BASE),
256 .flags = IORESOURCE_IRQ,
257 },
258};
259
260static struct adc_access_fn xoadc_fn = {
261 pm8058_xoadc_select_chan_and_start_conv,
262 pm8058_xoadc_read_adc_code,
263 pm8058_xoadc_get_properties,
264 pm8058_xoadc_slot_request,
265 pm8058_xoadc_restore_slot,
266 pm8058_xoadc_calibrate,
267};
268
269static struct msm_adc_channels msm_adc_channels_data[] = {
270 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
271 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
272 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
273 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
274 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
275 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
276 {"fsm_therm", CHANNEL_ADC_FSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE6,
277 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
278 {"pa_therm", CHANNEL_ADC_PA_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
279 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
280};
281
282static struct msm_adc_platform_data msm_adc_pdata = {
283 .channel = msm_adc_channels_data,
284 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
285 .target_hw = FSM_9xxx,
286};
287
288static struct platform_device msm_adc_device = {
289 .name = "msm_adc",
290 .id = -1,
291 .dev = {
292 .platform_data = &msm_adc_pdata,
293 },
294};
295
296static void pmic8058_xoadc_mpp_config(void)
297{
298 int rc;
299
300 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
301 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
302 if (rc)
303 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
304
305 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
306 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
307 if (rc)
308 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
309}
310
311static struct regulator *vreg_ldo18_adc;
312
313static int pmic8058_xoadc_vreg_config(int on)
314{
315 int rc;
316
317 if (on) {
318 rc = regulator_enable(vreg_ldo18_adc);
319 if (rc)
320 pr_err("%s: Enable of regulator ldo18_adc "
321 "failed\n", __func__);
322 } else {
323 rc = regulator_disable(vreg_ldo18_adc);
324 if (rc)
325 pr_err("%s: Disable of regulator ldo18_adc "
326 "failed\n", __func__);
327 }
328
329 return rc;
330}
331
332static int pmic8058_xoadc_vreg_setup(void)
333{
334 int rc;
335
336 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
337 if (IS_ERR(vreg_ldo18_adc)) {
338 pr_err("%s: vreg get failed (%ld)\n",
339 __func__, PTR_ERR(vreg_ldo18_adc));
340 rc = PTR_ERR(vreg_ldo18_adc);
341 goto fail;
342 }
343
344 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
345 if (rc) {
346 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
347 goto fail;
348 }
349
350 return rc;
351fail:
352 regulator_put(vreg_ldo18_adc);
353 return rc;
354}
355
356static void pmic8058_xoadc_vreg_shutdown(void)
357{
358 regulator_put(vreg_ldo18_adc);
359}
360
361/* usec. For this ADC,
362 * this time represents clk rate @ txco w/ 1024 decimation ratio.
363 * Each channel has different configuration, thus at the time of starting
364 * the conversion, xoadc will return actual conversion time
365 * */
366static struct adc_properties pm8058_xoadc_data = {
367 .adc_reference = 2200, /* milli-voltage for this adc */
368 .bitresolution = 15,
369 .bipolar = 0,
370 .conversiontime = 54,
371};
372
373static struct xoadc_platform_data xoadc_pdata = {
374 .xoadc_prop = &pm8058_xoadc_data,
375 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
376 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
377 .xoadc_num = XOADC_PMIC_0,
378 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
379 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
380};
381#endif
382
383/* Put sub devices with fixed location first in sub_devices array */
384static struct mfd_cell pm8058_subdevs[] = {
385 { .name = "pm8058-mpp",
386 .platform_data = &pm8058_mpp_data,
387 .pdata_size = sizeof(pm8058_mpp_data),
388 },
389 {
390 .name = "pm8058-gpio",
391 .id = -1,
392 .platform_data = &pm8058_gpio_data,
393 .pdata_size = sizeof(pm8058_gpio_data),
394 },
395#ifdef CONFIG_SENSORS_MSM_ADC
396 {
397 .name = "pm8058-xoadc",
398 .id = -1,
399 .num_resources = ARRAY_SIZE(resources_adc),
400 .resources = resources_adc,
401 .platform_data = &xoadc_pdata,
402 .pdata_size =sizeof(xoadc_pdata),
403 },
404#endif
405 PM8058_VREG(PM8058_VREG_ID_L3),
406 PM8058_VREG(PM8058_VREG_ID_L8),
407 PM8058_VREG(PM8058_VREG_ID_L9),
408 PM8058_VREG(PM8058_VREG_ID_L14),
409 PM8058_VREG(PM8058_VREG_ID_L15),
410 PM8058_VREG(PM8058_VREG_ID_L18),
411 PM8058_VREG(PM8058_VREG_ID_S4),
412 PM8058_VREG(PM8058_VREG_ID_LVS0),
413 PM8058_XO(PM8058_XO_ID_A0),
414 PM8058_XO(PM8058_XO_ID_A1),
415};
416
417static struct pm8058_platform_data pm8058_fsm9xxx_data = {
418 .irq_base = PMIC8058_IRQ_BASE,
419
420 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
421 .sub_devices = pm8058_subdevs,
422};
423
424static struct i2c_board_info pm8058_boardinfo[] __initdata = {
425 {
426 I2C_BOARD_INFO("pm8058-core", 0x55),
427 .irq = MSM_GPIO_TO_INT(47),
428 .platform_data = &pm8058_fsm9xxx_data,
429 },
430};
431
432static int __init buses_init(void)
433{
434 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 5, GPIO_CFG_INPUT,
435 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
436 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
437 __func__, PMIC_GPIO_INT);
438
439 i2c_register_board_info(0 /* I2C_SSBI ID */, pm8058_boardinfo,
440 ARRAY_SIZE(pm8058_boardinfo));
441
442 return 0;
443}
444
445/*
446 * EPHY
447 */
448
449static struct msm_gpio phy_config_data[] = {
450 { GPIO_CFG(GPIO_EPHY_RST_N, 0, GPIO_CFG_OUTPUT,
451 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "MAC_RST_N" },
452};
453
454static int __init phy_init(void)
455{
456 msm_gpios_request_enable(phy_config_data, ARRAY_SIZE(phy_config_data));
457 gpio_direction_output(GPIO_EPHY_RST_N, 0);
458 udelay(100);
459 gpio_set_value(GPIO_EPHY_RST_N, 1);
460
461 return 0;
462}
463
464/*
465 * RF
466 */
467
468static struct msm_gpio grfc_config_data[] = {
469 { GPIO_CFG(GPIO_GRFC_FTR0_0, 7, GPIO_CFG_OUTPUT,
470 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_0" },
471 { GPIO_CFG(GPIO_GRFC_FTR0_1, 7, GPIO_CFG_OUTPUT,
472 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_1" },
473 { GPIO_CFG(GPIO_GRFC_FTR1_0, 7, GPIO_CFG_OUTPUT,
474 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_0" },
475 { GPIO_CFG(GPIO_GRFC_FTR1_1, 7, GPIO_CFG_OUTPUT,
476 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_1" },
477 { GPIO_CFG(GPIO_GRFC_2, 7, GPIO_CFG_OUTPUT,
478 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_2" },
479 { GPIO_CFG(GPIO_GRFC_3, 7, GPIO_CFG_OUTPUT,
480 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_3" },
481 { GPIO_CFG(GPIO_GRFC_4, 7, GPIO_CFG_OUTPUT,
482 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_4" },
483 { GPIO_CFG(GPIO_GRFC_5, 7, GPIO_CFG_OUTPUT,
484 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_5" },
485 { GPIO_CFG(GPIO_GRFC_6, 7, GPIO_CFG_OUTPUT,
486 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_6" },
487 { GPIO_CFG(GPIO_GRFC_7, 7, GPIO_CFG_OUTPUT,
488 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_7" },
489 { GPIO_CFG(GPIO_GRFC_8, 7, GPIO_CFG_OUTPUT,
490 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_8" },
491 { GPIO_CFG(GPIO_GRFC_9, 7, GPIO_CFG_OUTPUT,
492 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_9" },
493 { GPIO_CFG(GPIO_GRFC_10, 7, GPIO_CFG_OUTPUT,
494 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_10" },
495 { GPIO_CFG(GPIO_GRFC_11, 7, GPIO_CFG_OUTPUT,
496 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_11" },
497 { GPIO_CFG(GPIO_GRFC_13, 7, GPIO_CFG_OUTPUT,
498 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_13" },
499 { GPIO_CFG(GPIO_GRFC_14, 7, GPIO_CFG_OUTPUT,
500 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_14" },
501 { GPIO_CFG(GPIO_GRFC_15, 7, GPIO_CFG_OUTPUT,
502 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_15" },
503 { GPIO_CFG(GPIO_GRFC_16, 7, GPIO_CFG_OUTPUT,
504 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_16" },
505 { GPIO_CFG(GPIO_GRFC_17, 7, GPIO_CFG_OUTPUT,
506 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_17" },
507 { GPIO_CFG(GPIO_GRFC_18, 7, GPIO_CFG_OUTPUT,
508 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_18" },
509 { GPIO_CFG(GPIO_GRFC_24, 7, GPIO_CFG_OUTPUT,
510 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_24" },
511 { GPIO_CFG(GPIO_GRFC_25, 7, GPIO_CFG_OUTPUT,
512 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_25" },
513 { GPIO_CFG(GPIO_GRFC_26, 7, GPIO_CFG_OUTPUT,
514 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_26" },
515 { GPIO_CFG(GPIO_GRFC_27, 7, GPIO_CFG_OUTPUT,
516 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_27" },
517 { GPIO_CFG(GPIO_GRFC_28, 7, GPIO_CFG_OUTPUT,
518 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_28" },
519 { GPIO_CFG(GPIO_GRFC_29, 7, GPIO_CFG_OUTPUT,
520 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_29" },
521 { GPIO_CFG(39, 1, GPIO_CFG_OUTPUT,
522 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "PP2S_EXT_SYNC" },
523};
524
525static int __init grfc_init(void)
526{
527 msm_gpios_request_enable(grfc_config_data,
528 ARRAY_SIZE(grfc_config_data));
529
530 return 0;
531}
532
533/*
534 * UART
535 */
536
537#ifdef CONFIG_SERIAL_MSM_CONSOLE
538static struct msm_gpio uart1_config_data[] = {
539 { GPIO_CFG(138, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
540 "UART1_Rx" },
541 { GPIO_CFG(139, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
542 "UART1_Tx" },
543};
544
545static void fsm9xxx_init_uart1(void)
546{
547 msm_gpios_request_enable(uart1_config_data,
548 ARRAY_SIZE(uart1_config_data));
549
550}
551#endif
552
553/*
554 * SSBI
555 */
556
557#ifdef CONFIG_I2C_SSBI
558static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi1_pdata = {
559 .controller_type = FSM_SBI_CTRL_SSBI,
560};
561
562static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi2_pdata = {
563 .controller_type = FSM_SBI_CTRL_SSBI,
564};
565
566static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi3_pdata = {
567 .controller_type = FSM_SBI_CTRL_SSBI,
568};
569
570/* Intialize GPIO configuration for SSBI */
571static struct msm_gpio ssbi_gpio_config_data[] = {
572 { GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
573 "SSBI_1" },
574 { GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
575 "SSBI_2" },
576 { GPIO_CFG(92, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
577 "SSBI_3" },
578};
579
580static void
581fsm9xxx_init_ssbi_gpio(void)
582{
583 msm_gpios_request_enable(ssbi_gpio_config_data,
584 ARRAY_SIZE(ssbi_gpio_config_data));
585
586}
587#endif
588
589/*
Rohit Vaswani26512de2011-07-11 16:01:13 -0700[diff] [blame^]590 * User GPIOs
591 */
592
593static void user_gpios_init(void)
594{
595 unsigned int gpio;
596
597 for (gpio = GPIO_USER_FIRST; gpio <= GPIO_USER_LAST; ++gpio)
598 gpio_tlmm_config(GPIO_CFG(gpio, 0, GPIO_CFG_INPUT,
599 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE);
600}
601
602/*
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]603 * Crypto
604 */
605
606#define QCE_SIZE 0x10000
607
608#define QCE_0_BASE 0x80C00000
609#define QCE_1_BASE 0x80E00000
610#define QCE_2_BASE 0x81000000
611
612#define QCE_NO_HW_KEY_SUPPORT 0 /* No shared HW key with external */
613#define QCE_NO_SHARE_CE_RESOURCE 0 /* No CE resource shared with TZ */
614#define QCE_NO_CE_SHARED 0 /* CE not shared with TZ */
615#define QCE_NO_SHA_HMAC_SUPPORT 0 /* No SHA-HMAC by SHA operation */
616
617static struct resource qcrypto_resources[] = {
618 [0] = {
619 .start = QCE_0_BASE,
620 .end = QCE_0_BASE + QCE_SIZE - 1,
621 .flags = IORESOURCE_MEM,
622 },
623 [1] = {
624 .name = "crypto_channels",
625 .start = DMOV_CE1_IN_CHAN,
626 .end = DMOV_CE1_OUT_CHAN,
627 .flags = IORESOURCE_DMA,
628 },
629 [2] = {
630 .name = "crypto_crci_in",
631 .start = DMOV_CE1_IN_CRCI,
632 .end = DMOV_CE1_IN_CRCI,
633 .flags = IORESOURCE_DMA,
634 },
635 [3] = {
636 .name = "crypto_crci_out",
637 .start = DMOV_CE1_OUT_CRCI,
638 .end = DMOV_CE1_OUT_CRCI,
639 .flags = IORESOURCE_DMA,
640 },
641 [4] = {
642 .name = "crypto_crci_hash",
643 .start = DMOV_CE1_HASH_CRCI,
644 .end = DMOV_CE1_HASH_CRCI,
645 .flags = IORESOURCE_DMA,
646 },
647};
648
649static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
650 .ce_shared = QCE_NO_CE_SHARED,
651 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
652 .hw_key_support = QCE_NO_HW_KEY_SUPPORT,
653 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
654};
655
656struct platform_device qcrypto_device = {
657 .name = "qcrypto",
658 .id = 0,
659 .num_resources = ARRAY_SIZE(qcrypto_resources),
660 .resource = qcrypto_resources,
661 .dev = {
662 .coherent_dma_mask = DMA_BIT_MASK(32),
663 .platform_data = &qcrypto_ce_hw_suppport,
664 },
665};
666
667static struct resource qcedev_resources[] = {
668 [0] = {
669 .start = QCE_0_BASE,
670 .end = QCE_0_BASE + QCE_SIZE - 1,
671 .flags = IORESOURCE_MEM,
672 },
673 [1] = {
674 .name = "crypto_channels",
675 .start = DMOV_CE1_IN_CHAN,
676 .end = DMOV_CE1_OUT_CHAN,
677 .flags = IORESOURCE_DMA,
678 },
679 [2] = {
680 .name = "crypto_crci_in",
681 .start = DMOV_CE1_IN_CRCI,
682 .end = DMOV_CE1_IN_CRCI,
683 .flags = IORESOURCE_DMA,
684 },
685 [3] = {
686 .name = "crypto_crci_out",
687 .start = DMOV_CE1_OUT_CRCI,
688 .end = DMOV_CE1_OUT_CRCI,
689 .flags = IORESOURCE_DMA,
690 },
691 [4] = {
692 .name = "crypto_crci_hash",
693 .start = DMOV_CE1_HASH_CRCI,
694 .end = DMOV_CE1_HASH_CRCI,
695 .flags = IORESOURCE_DMA,
696 },
697};
698
699static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
700 .ce_shared = QCE_NO_CE_SHARED,
701 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
702 .hw_key_support = QCE_NO_HW_KEY_SUPPORT,
703 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
704};
705
706static struct platform_device qcedev_device = {
707 .name = "qce",
708 .id = 0,
709 .num_resources = ARRAY_SIZE(qcedev_resources),
710 .resource = qcedev_resources,
711 .dev = {
712 .coherent_dma_mask = DMA_BIT_MASK(32),
713 .platform_data = &qcedev_ce_hw_suppport,
714 },
715};
716
717static struct resource ota_qcrypto_resources[] = {
718 [0] = {
719 .start = QCE_1_BASE,
720 .end = QCE_1_BASE + QCE_SIZE - 1,
721 .flags = IORESOURCE_MEM,
722 },
723 [1] = {
724 .name = "crypto_channels",
725 .start = DMOV_CE2_IN_CHAN,
726 .end = DMOV_CE2_OUT_CHAN,
727 .flags = IORESOURCE_DMA,
728 },
729 [2] = {
730 .name = "crypto_crci_in",
731 .start = DMOV_CE2_IN_CRCI,
732 .end = DMOV_CE2_IN_CRCI,
733 .flags = IORESOURCE_DMA,
734 },
735 [3] = {
736 .name = "crypto_crci_out",
737 .start = DMOV_CE2_OUT_CRCI,
738 .end = DMOV_CE2_OUT_CRCI,
739 .flags = IORESOURCE_DMA,
740 },
741 [4] = {
742 .name = "crypto_crci_hash",
743 .start = DMOV_CE2_HASH_CRCI,
744 .end = DMOV_CE2_HASH_CRCI,
745 .flags = IORESOURCE_DMA,
746 },
747};
748
749struct platform_device ota_qcrypto_device = {
750 .name = "qcota",
751 .id = 0,
752 .num_resources = ARRAY_SIZE(ota_qcrypto_resources),
753 .resource = ota_qcrypto_resources,
754 .dev = {
755 .coherent_dma_mask = DMA_BIT_MASK(32),
756 },
757};
758
759/*
760 * Devices
761 */
762
763static struct platform_device *devices[] __initdata = {
764 &msm_device_smd,
765 &msm_device_dmov,
766 &msm_device_nand,
767#ifdef CONFIG_I2C_SSBI
768 &msm_device_ssbi1,
769 &msm_device_ssbi2,
770 &msm_device_ssbi3,
771#endif
772#ifdef CONFIG_SENSORS_MSM_ADC
773 &msm_adc_device,
774#endif
775#ifdef CONFIG_I2C_QUP
776 &msm_gsbi1_qup_i2c_device,
777#endif
778#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
779 &msm_device_uart1,
780#endif
781#if defined(CONFIG_QFP_FUSE)
782 &fsm_qfp_fuse_device,
783#endif
784 &qfec_device,
785 &qcrypto_device,
786 &qcedev_device,
787 &ota_qcrypto_device,
788};
789
790static struct msm_acpu_clock_platform_data fsm9xxx_clock_data = {
791 .acpu_switch_time_us = 50,
792 .vdd_switch_time_us = 62,
793};
794
795static void __init fsm9xxx_init_irq(void)
796{
797 msm_init_irq();
798 msm_init_sirc();
799}
800
801#ifdef CONFIG_MSM_SPM
802static struct msm_spm_platform_data msm_spm_data __initdata = {
803 .reg_base_addr = MSM_SAW_BASE,
804
805 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
806 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
807 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
808 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
809
810 .reg_init_values[MSM_SPM_REG_SAW_SPM_PMIC_CTL] = 0xE0F272,
811 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
812 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
813 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
814
815 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
816 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
817 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
818
819 .awake_vlevel = 0xF2,
820 .retention_vlevel = 0xE0,
821 .collapse_vlevel = 0x72,
822 .retention_mid_vlevel = 0xE0,
823 .collapse_mid_vlevel = 0xE0,
824};
825#endif
826
827static void __init fsm9xxx_init(void)
828{
829 if (socinfo_init() < 0)
830 pr_err("%s: socinfo_init() failed!\n",
831 __func__);
832
833 msm_acpu_clock_init(&fsm9xxx_clock_data);
834
835 regulator_has_full_constraints();
836
837 platform_add_devices(devices, ARRAY_SIZE(devices));
838
839#ifdef CONFIG_MSM_SPM
840 msm_spm_init(&msm_spm_data, 1);
841#endif
842 buses_init();
843 phy_init();
844 grfc_init();
Rohit Vaswani26512de2011-07-11 16:01:13 -0700[diff] [blame^]845 user_gpios_init();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]846
847#ifdef CONFIG_SERIAL_MSM_CONSOLE
848 fsm9xxx_init_uart1();
849#endif
850#ifdef CONFIG_I2C_SSBI
851 fsm9xxx_init_ssbi_gpio();
852 msm_device_ssbi1.dev.platform_data = &msm_i2c_ssbi1_pdata;
853 msm_device_ssbi2.dev.platform_data = &msm_i2c_ssbi2_pdata;
854 msm_device_ssbi3.dev.platform_data = &msm_i2c_ssbi3_pdata;
855#endif
856}
857
858static void __init fsm9xxx_map_io(void)
859{
860 msm_shared_ram_phys = 0x00100000;
861 msm_map_fsm9xxx_io();
862 msm_clock_init(msm_clocks_fsm9xxx, msm_num_clocks_fsm9xxx);
863}
864
865MACHINE_START(FSM9XXX_SURF, "QCT FSM9XXX")
866 .boot_params = PHYS_OFFSET + 0x100,
867 .map_io = fsm9xxx_map_io,
868 .init_irq = fsm9xxx_init_irq,
869 .init_machine = fsm9xxx_init,
870 .timer = &msm_timer,
871MACHINE_END