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review.evervolv.com / android_kernel_htc_msm8960 / 28b79ff9661b22e4c41c0d00d4ab8503e810f13d / . / arch / powerpc / kernel / misc.S
blob: f770805f1215df787d7840e3acbc7692cd228503 [file] [log] [blame]
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]1/*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
9 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16#include <asm/ppc_asm.h>
17
18 .text
19
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]20/*
21 * Returns (address we are running at) - (address we were linked at)
22 * for use before the text and data are mapped to KERNELBASE.
23 */
24
25_GLOBAL(reloc_offset)
26 mflr r0
27 bl 1f
281: mflr r3
29 LOAD_REG_IMMEDIATE(r4,1b)
30 subf r3,r4,r3
31 mtlr r0
32 blr
33
34/*
35 * add_reloc_offset(x) returns x + reloc_offset().
36 */
37_GLOBAL(add_reloc_offset)
38 mflr r0
39 bl 1f
401: mflr r5
41 LOAD_REG_IMMEDIATE(r4,1b)
42 subf r5,r4,r5
43 add r3,r3,r5
44 mtlr r0
45 blr
46
47/*
48 * I/O string operations
49 *
50 * insb(port, buf, len)
51 * outsb(port, buf, len)
52 * insw(port, buf, len)
53 * outsw(port, buf, len)
54 * insl(port, buf, len)
55 * outsl(port, buf, len)
56 * insw_ns(port, buf, len)
57 * outsw_ns(port, buf, len)
58 * insl_ns(port, buf, len)
59 * outsl_ns(port, buf, len)
60 *
61 * The *_ns versions don't do byte-swapping.
62 */
63_GLOBAL(_insb)
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]64 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]65 cmpwi 0,r5,0
66 mtctr r5
67 subi r4,r4,1
68 blelr-
6900: lbz r5,0(r3)
70 eieio
71 stbu r5,1(r4)
72 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]73 twi 0,r5,0
74 isync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]75 blr
76
77_GLOBAL(_outsb)
78 cmpwi 0,r5,0
79 mtctr r5
80 subi r4,r4,1
81 blelr-
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]82 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]8300: lbzu r5,1(r4)
84 stb r5,0(r3)
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]85 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]86 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]87 blr
88
89_GLOBAL(_insw)
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]90 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]91 cmpwi 0,r5,0
92 mtctr r5
93 subi r4,r4,2
94 blelr-
9500: lhbrx r5,0,r3
96 eieio
97 sthu r5,2(r4)
98 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]99 twi 0,r5,0
100 isync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]101 blr
102
103_GLOBAL(_outsw)
104 cmpwi 0,r5,0
105 mtctr r5
106 subi r4,r4,2
107 blelr-
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]108 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]10900: lhzu r5,2(r4)
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]110 sthbrx r5,0,r3
111 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]112 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]113 blr
114
115_GLOBAL(_insl)
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]116 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]117 cmpwi 0,r5,0
118 mtctr r5
119 subi r4,r4,4
120 blelr-
12100: lwbrx r5,0,r3
122 eieio
123 stwu r5,4(r4)
124 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]125 twi 0,r5,0
126 isync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]127 blr
128
129_GLOBAL(_outsl)
130 cmpwi 0,r5,0
131 mtctr r5
132 subi r4,r4,4
133 blelr-
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]134 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]13500: lwzu r5,4(r4)
136 stwbrx r5,0,r3
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]137 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]138 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]139 blr
140
141#ifdef CONFIG_PPC32
142_GLOBAL(__ide_mm_insw)
143#endif
144_GLOBAL(_insw_ns)
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]145 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]146 cmpwi 0,r5,0
147 mtctr r5
148 subi r4,r4,2
149 blelr-
15000: lhz r5,0(r3)
151 eieio
152 sthu r5,2(r4)
153 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]154 twi 0,r5,0
155 isync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]156 blr
157
158#ifdef CONFIG_PPC32
159_GLOBAL(__ide_mm_outsw)
160#endif
161_GLOBAL(_outsw_ns)
162 cmpwi 0,r5,0
163 mtctr r5
164 subi r4,r4,2
165 blelr-
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]166 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]16700: lhzu r5,2(r4)
168 sth r5,0(r3)
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]169 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]170 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]171 blr
172
173#ifdef CONFIG_PPC32
174_GLOBAL(__ide_mm_insl)
175#endif
176_GLOBAL(_insl_ns)
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]177 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]178 cmpwi 0,r5,0
179 mtctr r5
180 subi r4,r4,4
181 blelr-
18200: lwz r5,0(r3)
183 eieio
184 stwu r5,4(r4)
185 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]186 twi 0,r5,0
187 isync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]188 blr
189
190#ifdef CONFIG_PPC32
191_GLOBAL(__ide_mm_outsl)
192#endif
193_GLOBAL(_outsl_ns)
194 cmpwi 0,r5,0
195 mtctr r5
196 subi r4,r4,4
197 blelr-
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]198 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]19900: lwzu r5,4(r4)
200 stw r5,0(r3)
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]201 bdnz 00b
Paul Mackerrasf007cac2006-09-13 22:08:26 +1000[diff] [blame]202 sync
Stephen Rothwell127efeb2006-06-28 11:55:49 +1000[diff] [blame]203 blr
204