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review.evervolv.com / android_kernel_htc_msm8960 / 28baebae73c3ea8b75c7cae225a7db817ab825a9 / . / arch / frv / kernel / entry-table.S
blob: 81568acea9cdb0fe1b31a4b39ac5a094e587fbbb [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* entry-table.S: main trap vector tables and exception jump table
2 *
3 * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/sys.h>
14#include <linux/config.h>
15#include <linux/linkage.h>
16#include <asm/spr-regs.h>
17
18###############################################################################
19#
20# Declare the main trap and vector tables
21#
22# There are six tables:
23#
24# (1) The trap table for debug mode
25# (2) The trap table for kernel mode
26# (3) The trap table for user mode
27#
28# The CPU jumps to an appropriate slot in the appropriate table to perform
29# exception processing. We have three different tables for the three
30# different CPU modes because there is no hardware differentiation between
31# stack pointers for these three modes, and so we have to invent one when
32# crossing mode boundaries.
33#
34# (4) The exception handler vector table
35#
36# The user and kernel trap tables use the same prologue for normal
37# exception processing. The prologue then jumps to the handler in this
38# table, as indexed by the exception ID from the TBR.
39#
40# (5) The fixup table for kernel-trap single-step
41# (6) The fixup table for user-trap single-step
42#
43# Due to the way single-stepping works on this CPU (single-step is not
44# disabled when crossing exception boundaries, only when in debug mode),
45# we have to catch the single-step event in break.S and jump to the fixup
46# routine pointed to by this table.
47#
48# The linker script places the user mode and kernel mode trap tables on to
49# the same 8Kb page, so that break.S can be more efficient when performing
50# single-step bypass management
51#
52###############################################################################
53
54 # trap table for entry from debug mode
55 .section .trap.break,"ax"
56 .balign 256*16
57 .globl __entry_breaktrap_table
58__entry_breaktrap_table:
59
60 # trap table for entry from user mode
61 .section .trap.user,"ax"
62 .balign 256*16
63 .globl __entry_usertrap_table
64__entry_usertrap_table:
65
66 # trap table for entry from kernel mode
67 .section .trap.kernel,"ax"
68 .balign 256*16
69 .globl __entry_kerneltrap_table
70__entry_kerneltrap_table:
71
72 # exception handler jump table
73 .section .trap.vector,"ax"
74 .balign 256*4
75 .globl __entry_vector_table
76__entry_vector_table:
77
78 # trap fixup table for single-stepping in user mode
79 .section .trap.fixup.user,"a"
80 .balign 256*4
81 .globl __break_usertrap_fixup_table
82__break_usertrap_fixup_table:
83
84 # trap fixup table for single-stepping in user mode
85 .section .trap.fixup.kernel,"a"
86 .balign 256*4
87 .globl __break_kerneltrap_fixup_table
88__break_kerneltrap_fixup_table:
89
90 # handler declaration for a sofware or program interrupt
91.macro VECTOR_SOFTPROG tbr_tt, vec
92 .section .trap.user
93 .org \tbr_tt
94 bra __entry_uspace_softprog_interrupt
95 .section .trap.fixup.user
96 .org \tbr_tt >> 2
97 .long __break_step_uspace_softprog_interrupt
98 .section .trap.kernel
99 .org \tbr_tt
100 bra __entry_kernel_softprog_interrupt
101 .section .trap.fixup.kernel
102 .org \tbr_tt >> 2
103 .long __break_step_kernel_softprog_interrupt
104 .section .trap.vector
105 .org \tbr_tt >> 2
106 .long \vec
107.endm
108
109 # handler declaration for a maskable external interrupt
110.macro VECTOR_IRQ tbr_tt, vec
111 .section .trap.user
112 .org \tbr_tt
113 bra __entry_uspace_external_interrupt
114 .section .trap.fixup.user
115 .org \tbr_tt >> 2
116 .long __break_step_uspace_external_interrupt
117 .section .trap.kernel
118 .org \tbr_tt
David Howells28baeba2006-02-14 13:53:20 -0800[diff] [blame^]119 # deal with virtual interrupt disablement
120 beq icc2,#0,__entry_kernel_external_interrupt_virtually_disabled
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]121 bra __entry_kernel_external_interrupt
122 .section .trap.fixup.kernel
123 .org \tbr_tt >> 2
124 .long __break_step_kernel_external_interrupt
125 .section .trap.vector
126 .org \tbr_tt >> 2
127 .long \vec
128.endm
129
130 # handler declaration for an NMI external interrupt
131.macro VECTOR_NMI tbr_tt, vec
132 .section .trap.user
133 .org \tbr_tt
134 break
135 break
136 break
137 break
138 .section .trap.kernel
139 .org \tbr_tt
140 break
141 break
142 break
143 break
144 .section .trap.vector
145 .org \tbr_tt >> 2
146 .long \vec
147.endm
148
149 # handler declaration for an MMU only sofware or program interrupt
150.macro VECTOR_SP_MMU tbr_tt, vec
151#ifdef CONFIG_MMU
152 VECTOR_SOFTPROG \tbr_tt, \vec
153#else
154 VECTOR_NMI \tbr_tt, 0
155#endif
156.endm
157
158
159###############################################################################
160#
161# specification of the vectors
162# - note: each macro inserts code into multiple sections
163#
164###############################################################################
165 VECTOR_SP_MMU TBR_TT_INSTR_MMU_MISS, __entry_insn_mmu_miss
166 VECTOR_SOFTPROG TBR_TT_INSTR_ACC_ERROR, __entry_insn_access_error
167 VECTOR_SOFTPROG TBR_TT_INSTR_ACC_EXCEP, __entry_insn_access_exception
168 VECTOR_SOFTPROG TBR_TT_PRIV_INSTR, __entry_privileged_instruction
169 VECTOR_SOFTPROG TBR_TT_ILLEGAL_INSTR, __entry_illegal_instruction
170 VECTOR_SOFTPROG TBR_TT_FP_EXCEPTION, __entry_media_exception
171 VECTOR_SOFTPROG TBR_TT_MP_EXCEPTION, __entry_media_exception
172 VECTOR_SOFTPROG TBR_TT_DATA_ACC_ERROR, __entry_data_access_error
173 VECTOR_SP_MMU TBR_TT_DATA_MMU_MISS, __entry_data_mmu_miss
174 VECTOR_SOFTPROG TBR_TT_DATA_ACC_EXCEP, __entry_data_access_exception
175 VECTOR_SOFTPROG TBR_TT_DATA_STR_ERROR, __entry_data_store_error
176 VECTOR_SOFTPROG TBR_TT_DIVISION_EXCEP, __entry_division_exception
177
178#ifdef CONFIG_MMU
179 .section .trap.user
180 .org TBR_TT_INSTR_TLB_MISS
181 .globl __trap_user_insn_tlb_miss
182__trap_user_insn_tlb_miss:
183 movsg ear0,gr28 /* faulting address */
184 movsg scr0,gr31 /* get mapped PTD coverage start address */
185 xor.p gr28,gr31,gr31 /* compare addresses */
186 bra __entry_user_insn_tlb_miss
187
188 .org TBR_TT_DATA_TLB_MISS
189 .globl __trap_user_data_tlb_miss
190__trap_user_data_tlb_miss:
191 movsg ear0,gr28 /* faulting address */
192 movsg scr1,gr31 /* get mapped PTD coverage start address */
193 xor.p gr28,gr31,gr31 /* compare addresses */
194 bra __entry_user_data_tlb_miss
195
196 .section .trap.kernel
197 .org TBR_TT_INSTR_TLB_MISS
198 .globl __trap_kernel_insn_tlb_miss
199__trap_kernel_insn_tlb_miss:
200 movsg ear0,gr29 /* faulting address */
201 movsg scr0,gr31 /* get mapped PTD coverage start address */
202 xor.p gr29,gr31,gr31 /* compare addresses */
203 bra __entry_kernel_insn_tlb_miss
204
205 .org TBR_TT_DATA_TLB_MISS
206 .globl __trap_kernel_data_tlb_miss
207__trap_kernel_data_tlb_miss:
208 movsg ear0,gr29 /* faulting address */
209 movsg scr1,gr31 /* get mapped PTD coverage start address */
210 xor.p gr29,gr31,gr31 /* compare addresses */
211 bra __entry_kernel_data_tlb_miss
212
213 .section .trap.fixup.user
214 .org TBR_TT_INSTR_TLB_MISS >> 2
215 .globl __trap_fixup_user_insn_tlb_miss
216__trap_fixup_user_insn_tlb_miss:
217 .long __break_user_insn_tlb_miss
218 .org TBR_TT_DATA_TLB_MISS >> 2
219 .globl __trap_fixup_user_data_tlb_miss
220__trap_fixup_user_data_tlb_miss:
221 .long __break_user_data_tlb_miss
222
223 .section .trap.fixup.kernel
224 .org TBR_TT_INSTR_TLB_MISS >> 2
225 .globl __trap_fixup_kernel_insn_tlb_miss
226__trap_fixup_kernel_insn_tlb_miss:
227 .long __break_kernel_insn_tlb_miss
228 .org TBR_TT_DATA_TLB_MISS >> 2
229 .globl __trap_fixup_kernel_data_tlb_miss
230__trap_fixup_kernel_data_tlb_miss:
231 .long __break_kernel_data_tlb_miss
232
233 .section .trap.vector
234 .org TBR_TT_INSTR_TLB_MISS >> 2
235 .long __entry_insn_mmu_fault
236 .org TBR_TT_DATA_TLB_MISS >> 2
237 .long __entry_data_mmu_fault
238#endif
239
240 VECTOR_SP_MMU TBR_TT_DATA_DAT_EXCEP, __entry_data_dat_fault
241 VECTOR_NMI TBR_TT_DECREMENT_TIMER, __entry_do_NMI
242 VECTOR_SOFTPROG TBR_TT_COMPOUND_EXCEP, __entry_compound_exception
243 VECTOR_IRQ TBR_TT_INTERRUPT_1, __entry_do_IRQ
244 VECTOR_IRQ TBR_TT_INTERRUPT_2, __entry_do_IRQ
245 VECTOR_IRQ TBR_TT_INTERRUPT_3, __entry_do_IRQ
246 VECTOR_IRQ TBR_TT_INTERRUPT_4, __entry_do_IRQ
247 VECTOR_IRQ TBR_TT_INTERRUPT_5, __entry_do_IRQ
248 VECTOR_IRQ TBR_TT_INTERRUPT_6, __entry_do_IRQ
249 VECTOR_IRQ TBR_TT_INTERRUPT_7, __entry_do_IRQ
250 VECTOR_IRQ TBR_TT_INTERRUPT_8, __entry_do_IRQ
251 VECTOR_IRQ TBR_TT_INTERRUPT_9, __entry_do_IRQ
252 VECTOR_IRQ TBR_TT_INTERRUPT_10, __entry_do_IRQ
253 VECTOR_IRQ TBR_TT_INTERRUPT_11, __entry_do_IRQ
254 VECTOR_IRQ TBR_TT_INTERRUPT_12, __entry_do_IRQ
255 VECTOR_IRQ TBR_TT_INTERRUPT_13, __entry_do_IRQ
256 VECTOR_IRQ TBR_TT_INTERRUPT_14, __entry_do_IRQ
257 VECTOR_NMI TBR_TT_INTERRUPT_15, __entry_do_NMI
258
259 # miscellaneous user mode entry points
260 .section .trap.user
261 .org TBR_TT_TRAP0
262 .rept 127
263 bra __entry_uspace_softprog_interrupt
David Howells28baeba2006-02-14 13:53:20 -0800[diff] [blame^]264 .long 0,0,0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]265 .endr
266 .org TBR_TT_BREAK
267 bra __entry_break
268 .long 0,0,0
269
David Howells28baeba2006-02-14 13:53:20 -0800[diff] [blame^]270 .section .trap.fixup.user
271 .org TBR_TT_TRAP0 >> 2
272 .rept 127
273 .long __break_step_uspace_softprog_interrupt
274 .endr
275 .org TBR_TT_BREAK >> 2
276 .long 0
277
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]278 # miscellaneous kernel mode entry points
279 .section .trap.kernel
280 .org TBR_TT_TRAP0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]281 bra __entry_kernel_softprog_interrupt
David Howells28baeba2006-02-14 13:53:20 -0800[diff] [blame^]282 .org TBR_TT_TRAP1
283 bra __entry_kernel_softprog_interrupt
284
285 # trap #2 in kernel - reenable interrupts
286 .org TBR_TT_TRAP2
287 bra __entry_kernel_external_interrupt_virtual_reenable
288
289 # miscellaneous kernel traps
290 .org TBR_TT_TRAP3
291 .rept 124
292 bra __entry_kernel_softprog_interrupt
293 .long 0,0,0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]294 .endr
295 .org TBR_TT_BREAK
296 bra __entry_break
297 .long 0,0,0
298
David Howells28baeba2006-02-14 13:53:20 -0800[diff] [blame^]299 .section .trap.fixup.kernel
300 .org TBR_TT_TRAP0 >> 2
301 .long __break_step_kernel_softprog_interrupt
302 .long __break_step_kernel_softprog_interrupt
303 .long __break_step_kernel_external_interrupt_virtual_reenable
304 .rept 124
305 .long __break_step_kernel_softprog_interrupt
306 .endr
307 .org TBR_TT_BREAK >> 2
308 .long 0
309
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]310 # miscellaneous debug mode entry points
311 .section .trap.break
312 .org TBR_TT_BREAK
313 movsg bpcsr,gr30
314 jmpl @(gr30,gr0)
315
316 # miscellaneous vectors
317 .section .trap.vector
318 .org TBR_TT_TRAP0 >> 2
319 .long system_call
320 .rept 126
321 .long __entry_unsupported_trap
322 .endr
323 .org TBR_TT_BREAK >> 2
324 .long __entry_debug_exception