Blame - arch/sparc64/kernel/winfixup.S - android_kernel_htc_msm8960

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David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	1	/* winfixup.S: Handle cases where user stack pointer is found to be bogus.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2	*
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	3	* Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*/
				5
				6	#include <asm/asi.h>
				7	#include <asm/head.h>
				8	#include <asm/page.h>
				9	#include <asm/ptrace.h>
				10	#include <asm/processor.h>
				11	#include <asm/spitfire.h>
				12	#include <asm/thread_info.h>
				13
				14	.text
				15
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	16	/* It used to be the case that these register window fault
				17	* handlers could run via the save and restore instructions
				18	* done by the trap entry and exit code. They now do the
				19	* window spill/fill by hand, so that case no longer can occur.
				20	*/
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	21
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	22	.align 32
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	23	fill_fixup:
David S. Miller	ffe483d	2006-02-02 21:55:10 -0800	[diff] [blame]	24	TRAP_LOAD_THREAD_REG(%g6, %g1)
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	25	rdpr %tstate, %g1
				26	and %g1, TSTATE_CWP, %g1
				27	or %g4, FAULT_CODE_WINFIXUP, %g4
				28	stb %g4, [%g6 + TI_FAULT_CODE]
				29	stx %g5, [%g6 + TI_FAULT_ADDR]
				30	wrpr %g1, %cwp
				31	ba,pt %xcc, etrap
				32	rd %pc, %g7
				33	call do_sparc64_fault
				34	add %sp, PTREGS_OFF, %o0
David S. Miller	7697daa	2008-04-24 03:15:22 -0700	[diff] [blame]	35	ba,pt %xcc, rtrap
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	36	nop
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	37
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	38	/* Be very careful about usage of the trap globals here.
				39	* You cannot touch %g5 as that has the fault information.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	40	*/
				41	spill_fixup:
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	42	spill_fixup_mna:
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	43	spill_fixup_dax:
David S. Miller	ffe483d	2006-02-02 21:55:10 -0800	[diff] [blame]	44	TRAP_LOAD_THREAD_REG(%g6, %g1)
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	45	ldx [%g6 + TI_FLAGS], %g1
				46	andcc %g1, _TIF_32BIT, %g0
				47	ldub [%g6 + TI_WSAVED], %g1
				48	sll %g1, 3, %g3
				49	add %g6, %g3, %g3
				50	stx %sp, [%g3 + TI_RWIN_SPTRS]
				51	sll %g1, 7, %g3
				52	bne,pt %xcc, 1f
				53	add %g6, %g3, %g3
				54	stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
				55	stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
				56	stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
				57	stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
				58	stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
				59	stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
				60	stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
				61	stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
				62	stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
				63	stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
				64	stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
				65	stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
				66	stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
				67	stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
				68	stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
				69	ba,pt %xcc, 2f
				70	stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
				71	1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
				72	stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
				73	stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
				74	stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
				75	stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
				76	stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
				77	stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
				78	stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
				79	stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
				80	stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
				81	stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
				82	stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
				83	stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
				84	stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
				85	stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
				86	stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
				87	2: add %g1, 1, %g1
				88	stb %g1, [%g6 + TI_WSAVED]
				89	rdpr %tstate, %g1
				90	andcc %g1, TSTATE_PRIV, %g0
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	91	saved
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	92	be,pn %xcc, 1f
				93	and %g1, TSTATE_CWP, %g1
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	94	retry
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	95	1: mov FAULT_CODE_WRITE \| FAULT_CODE_DTLB \| FAULT_CODE_WINFIXUP, %g4
				96	stb %g4, [%g6 + TI_FAULT_CODE]
				97	stx %g5, [%g6 + TI_FAULT_ADDR]
				98	wrpr %g1, %cwp
				99	ba,pt %xcc, etrap
				100	rd %pc, %g7
				101	call do_sparc64_fault
				102	add %sp, PTREGS_OFF, %o0
David S. Miller	7697daa	2008-04-24 03:15:22 -0700	[diff] [blame]	103	ba,a,pt %xcc, rtrap
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	104
				105	winfix_mna:
				106	andn %g3, 0x7f, %g3
				107	add %g3, 0x78, %g3
				108	wrpr %g3, %tnpc
				109	done
				110
				111	fill_fixup_mna:
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	112	rdpr %tstate, %g1
				113	and %g1, TSTATE_CWP, %g1
				114	wrpr %g1, %cwp
				115	ba,pt %xcc, etrap
				116	rd %pc, %g7
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	117	sethi %hi(tlb_type), %g1
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	118	lduw [%g1 + %lo(tlb_type)], %g1
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	119	cmp %g1, 3
				120	bne,pt %icc, 1f
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	121	add %sp, PTREGS_OFF, %o0
David S. Miller	24c523e	2006-02-18 16:39:39 -0800	[diff] [blame]	122	mov %l4, %o2
David S. Miller	9b6b464	2006-02-16 01:45:49 -0800	[diff] [blame]	123	call sun4v_do_mna
David S. Miller	24c523e	2006-02-18 16:39:39 -0800	[diff] [blame]	124	mov %l5, %o1
David S. Miller	7697daa	2008-04-24 03:15:22 -0700	[diff] [blame]	125	ba,a,pt %xcc, rtrap
David S. Miller	24c523e	2006-02-18 16:39:39 -0800	[diff] [blame]	126	1: mov %l4, %o1
				127	mov %l5, %o2
				128	call mem_address_unaligned
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	129	nop
David S. Miller	7697daa	2008-04-24 03:15:22 -0700	[diff] [blame]	130	ba,a,pt %xcc, rtrap
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	131
				132	winfix_dax:
				133	andn %g3, 0x7f, %g3
				134	add %g3, 0x74, %g3
				135	wrpr %g3, %tnpc
				136	done
				137
				138	fill_fixup_dax:
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	139	rdpr %tstate, %g1
				140	and %g1, TSTATE_CWP, %g1
				141	wrpr %g1, %cwp
				142	ba,pt %xcc, etrap
				143	rd %pc, %g7
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	144	sethi %hi(tlb_type), %g1
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	145	mov %l4, %o1
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	146	lduw [%g1 + %lo(tlb_type)], %g1
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	147	mov %l5, %o2
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	148	cmp %g1, 3
				149	bne,pt %icc, 1f
David S. Miller	314ef68	2006-02-04 00:10:01 -0800	[diff] [blame]	150	add %sp, PTREGS_OFF, %o0
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	151	call sun4v_data_access_exception
				152	nop
David S. Miller	7697daa	2008-04-24 03:15:22 -0700	[diff] [blame]	153	ba,a,pt %xcc, rtrap
David S. Miller	ed6b0b4	2006-02-09 20:20:34 -0800	[diff] [blame]	154	1: call spitfire_data_access_exception
				155	nop
David S. Miller	7697daa	2008-04-24 03:15:22 -0700	[diff] [blame]	156	ba,a,pt %xcc, rtrap