| Josh Boyer | 94c73a8 | 2008-09-03 21:01:39 -0400 | [diff] [blame] | 1 | /* | 
|  | 2 | * Old U-boot compatibility for Acadia | 
|  | 3 | * | 
|  | 4 | * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com> | 
|  | 5 | * | 
|  | 6 | * Copyright 2008 IBM Corporation | 
|  | 7 | * | 
|  | 8 | * This program is free software; you can redistribute it and/or modify it | 
|  | 9 | * under the terms of the GNU General Public License version 2 as published | 
|  | 10 | * by the Free Software Foundation. | 
|  | 11 | */ | 
|  | 12 |  | 
|  | 13 | #include "ops.h" | 
|  | 14 | #include "io.h" | 
|  | 15 | #include "dcr.h" | 
|  | 16 | #include "stdio.h" | 
|  | 17 | #include "4xx.h" | 
|  | 18 | #include "44x.h" | 
|  | 19 | #include "cuboot.h" | 
|  | 20 |  | 
|  | 21 | #define TARGET_4xx | 
|  | 22 | #include "ppcboot.h" | 
|  | 23 |  | 
|  | 24 | static bd_t bd; | 
|  | 25 |  | 
|  | 26 | #define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */ | 
|  | 27 |  | 
|  | 28 | #define PLLC_SRC_MASK	       0x20000000     /* PLL feedback source */ | 
|  | 29 |  | 
|  | 30 | #define PLLD_FBDV_MASK	       0x1F000000     /* PLL feedback divider value */ | 
|  | 31 | #define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */ | 
|  | 32 | #define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */ | 
|  | 33 |  | 
|  | 34 | #define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */ | 
|  | 35 | #define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */ | 
|  | 36 | #define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */ | 
|  | 37 | #define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */ | 
|  | 38 |  | 
|  | 39 | #define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */ | 
|  | 40 | #define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */ | 
|  | 41 | #define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */ | 
|  | 42 | #define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */ | 
|  | 43 |  | 
|  | 44 | static void get_clocks(void) | 
|  | 45 | { | 
|  | 46 | unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i; | 
|  | 47 | unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv; | 
|  | 48 | unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB; | 
|  | 49 | unsigned long div;		/* total divisor udiv * bdiv */ | 
|  | 50 | unsigned long umin;		/* minimum udiv	*/ | 
|  | 51 | unsigned short diff;		/* smallest diff */ | 
|  | 52 | unsigned long udiv;		/* best udiv */ | 
|  | 53 | unsigned short idiff;		/* current diff */ | 
|  | 54 | unsigned short ibdiv;		/* current bdiv */ | 
|  | 55 | unsigned long est;		/* current estimate */ | 
|  | 56 | unsigned long baud; | 
|  | 57 | void *np; | 
|  | 58 |  | 
|  | 59 | /* read the sysclk value from the CPLD */ | 
|  | 60 | sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000; | 
|  | 61 |  | 
|  | 62 | /* | 
|  | 63 | * Read PLL Mode registers | 
|  | 64 | */ | 
|  | 65 | cpr_plld = CPR0_READ(DCRN_CPR0_PLLD); | 
|  | 66 | cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC); | 
|  | 67 |  | 
|  | 68 | /* | 
|  | 69 | * Determine forward divider A | 
|  | 70 | */ | 
|  | 71 | pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16); | 
|  | 72 |  | 
|  | 73 | /* | 
|  | 74 | * Determine forward divider B | 
|  | 75 | */ | 
|  | 76 | pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8); | 
|  | 77 | if (pllFwdDivB == 0) | 
|  | 78 | pllFwdDivB = 8; | 
|  | 79 |  | 
|  | 80 | /* | 
|  | 81 | * Determine FBK_DIV. | 
|  | 82 | */ | 
|  | 83 | pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); | 
|  | 84 | if (pllFbkDiv == 0) | 
|  | 85 | pllFbkDiv = 256; | 
|  | 86 |  | 
|  | 87 | /* | 
|  | 88 | * Read CPR_PRIMAD register | 
|  | 89 | */ | 
|  | 90 | cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD); | 
|  | 91 |  | 
|  | 92 | /* | 
|  | 93 | * Determine PLB_DIV. | 
|  | 94 | */ | 
|  | 95 | pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16); | 
|  | 96 | if (pllPlbDiv == 0) | 
|  | 97 | pllPlbDiv = 16; | 
|  | 98 |  | 
|  | 99 | /* | 
|  | 100 | * Determine EXTBUS_DIV. | 
|  | 101 | */ | 
|  | 102 | pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK); | 
|  | 103 | if (pllExtBusDiv == 0) | 
|  | 104 | pllExtBusDiv = 16; | 
|  | 105 |  | 
|  | 106 | /* | 
|  | 107 | * Determine OPB_DIV. | 
|  | 108 | */ | 
|  | 109 | pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8); | 
|  | 110 | if (pllOpbDiv == 0) | 
|  | 111 | pllOpbDiv = 16; | 
|  | 112 |  | 
|  | 113 | /* There is a bug in U-Boot that prevents us from using | 
|  | 114 | * bd.bi_opbfreq because U-Boot doesn't populate it for | 
|  | 115 | * 405EZ.  We get to calculate it, yay! | 
|  | 116 | */ | 
|  | 117 | freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv; | 
|  | 118 |  | 
|  | 119 | freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv; | 
|  | 120 |  | 
|  | 121 | plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ? | 
|  | 122 | pllFwdDivB : pllFwdDiv) * | 
|  | 123 | pllFbkDiv) / pllFwdDivB); | 
|  | 124 |  | 
|  | 125 | np = find_node_by_alias("serial0"); | 
|  | 126 | if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud)) | 
|  | 127 | fatal("no current-speed property\n\r"); | 
|  | 128 |  | 
|  | 129 | udiv = 256;			/* Assume lowest possible serial clk */ | 
|  | 130 | div = plloutb / (16 * baud); /* total divisor */ | 
|  | 131 | umin = (plloutb / freqOPB) << 1;	/* 2 x OPB divisor */ | 
|  | 132 | diff = 256;			/* highest possible */ | 
|  | 133 |  | 
|  | 134 | /* i is the test udiv value -- start with the largest | 
|  | 135 | * possible (256) to minimize serial clock and constrain | 
|  | 136 | * search to umin. | 
|  | 137 | */ | 
|  | 138 | for (i = 256; i > umin; i--) { | 
|  | 139 | ibdiv = div / i; | 
|  | 140 | est = i * ibdiv; | 
|  | 141 | idiff = (est > div) ? (est-div) : (div-est); | 
|  | 142 | if (idiff == 0) { | 
|  | 143 | udiv = i; | 
|  | 144 | break;      /* can't do better */ | 
|  | 145 | } else if (idiff < diff) { | 
|  | 146 | udiv = i;       /* best so far */ | 
|  | 147 | diff = idiff;   /* update lowest diff*/ | 
|  | 148 | } | 
|  | 149 | } | 
|  | 150 | freqUART = plloutb / udiv; | 
|  | 151 |  | 
|  | 152 | dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq); | 
|  | 153 | dt_fixup_clock("/plb/ebc", freqEBC); | 
|  | 154 | dt_fixup_clock("/plb/opb", freqOPB); | 
|  | 155 | dt_fixup_clock("/plb/opb/serial@ef600300", freqUART); | 
|  | 156 | dt_fixup_clock("/plb/opb/serial@ef600400", freqUART); | 
|  | 157 | } | 
|  | 158 |  | 
|  | 159 | static void acadia_fixups(void) | 
|  | 160 | { | 
|  | 161 | dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); | 
|  | 162 | get_clocks(); | 
|  | 163 | dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr); | 
|  | 164 | } | 
|  | 165 |  | 
|  | 166 | void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | 
|  | 167 | unsigned long r6, unsigned long r7) | 
|  | 168 | { | 
|  | 169 | CUBOOT_INIT(); | 
|  | 170 | platform_ops.fixups = acadia_fixups; | 
|  | 171 | platform_ops.exit = ibm40x_dbcr_reset; | 
|  | 172 | fdt_init(_dtb_start); | 
|  | 173 | serial_console_init(); | 
|  | 174 | } |