| Suresh Siddha | 2d9579a | 2008-07-10 11:16:59 -0700 | [diff] [blame^] | 1 | #include <linux/threads.h> |
| 2 | #include <linux/cpumask.h> |
| 3 | #include <linux/string.h> |
| 4 | #include <linux/kernel.h> |
| 5 | #include <linux/ctype.h> |
| 6 | #include <linux/init.h> |
| 7 | #include <asm/smp.h> |
| 8 | #include <asm/ipi.h> |
| 9 | #include <asm/genapic.h> |
| 10 | |
| 11 | |
| 12 | /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ |
| 13 | |
| 14 | static cpumask_t x2apic_target_cpus(void) |
| 15 | { |
| 16 | return cpumask_of_cpu(0); |
| 17 | } |
| 18 | |
| 19 | static cpumask_t x2apic_vector_allocation_domain(int cpu) |
| 20 | { |
| 21 | cpumask_t domain = CPU_MASK_NONE; |
| 22 | cpu_set(cpu, domain); |
| 23 | return domain; |
| 24 | } |
| 25 | |
| 26 | static void __x2apic_send_IPI_dest(unsigned int apicid, int vector, |
| 27 | unsigned int dest) |
| 28 | { |
| 29 | unsigned long cfg; |
| 30 | |
| 31 | cfg = __prepare_ICR(0, vector, dest); |
| 32 | |
| 33 | /* |
| 34 | * send the IPI. |
| 35 | */ |
| 36 | x2apic_icr_write(cfg, apicid); |
| 37 | } |
| 38 | |
| 39 | static void x2apic_send_IPI_mask(cpumask_t mask, int vector) |
| 40 | { |
| 41 | unsigned long flags; |
| 42 | unsigned long query_cpu; |
| 43 | |
| 44 | local_irq_save(flags); |
| 45 | for_each_cpu_mask(query_cpu, mask) { |
| 46 | __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu), |
| 47 | vector, APIC_DEST_PHYSICAL); |
| 48 | } |
| 49 | local_irq_restore(flags); |
| 50 | } |
| 51 | |
| 52 | static void x2apic_send_IPI_allbutself(int vector) |
| 53 | { |
| 54 | cpumask_t mask = cpu_online_map; |
| 55 | |
| 56 | cpu_clear(smp_processor_id(), mask); |
| 57 | |
| 58 | if (!cpus_empty(mask)) |
| 59 | x2apic_send_IPI_mask(mask, vector); |
| 60 | } |
| 61 | |
| 62 | static void x2apic_send_IPI_all(int vector) |
| 63 | { |
| 64 | x2apic_send_IPI_mask(cpu_online_map, vector); |
| 65 | } |
| 66 | |
| 67 | static int x2apic_apic_id_registered(void) |
| 68 | { |
| 69 | return 1; |
| 70 | } |
| 71 | |
| 72 | static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask) |
| 73 | { |
| 74 | int cpu; |
| 75 | |
| 76 | /* |
| 77 | * We're using fixed IRQ delivery, can only return one phys APIC ID. |
| 78 | * May as well be the first. |
| 79 | */ |
| 80 | cpu = first_cpu(cpumask); |
| 81 | if ((unsigned)cpu < NR_CPUS) |
| 82 | return per_cpu(x86_cpu_to_apicid, cpu); |
| 83 | else |
| 84 | return BAD_APICID; |
| 85 | } |
| 86 | |
| 87 | static unsigned int x2apic_read_id(void) |
| 88 | { |
| 89 | return apic_read(APIC_ID); |
| 90 | } |
| 91 | |
| 92 | static unsigned int phys_pkg_id(int index_msb) |
| 93 | { |
| 94 | return x2apic_read_id() >> index_msb; |
| 95 | } |
| 96 | |
| 97 | void x2apic_send_IPI_self(int vector) |
| 98 | { |
| 99 | apic_write(APIC_SELF_IPI, vector); |
| 100 | } |
| 101 | |
| 102 | void init_x2apic_ldr(void) |
| 103 | { |
| 104 | return; |
| 105 | } |
| 106 | |
| 107 | struct genapic apic_x2apic_phys = { |
| 108 | .name = "physical x2apic", |
| 109 | .int_delivery_mode = dest_Fixed, |
| 110 | .int_dest_mode = (APIC_DEST_PHYSICAL != 0), |
| 111 | .target_cpus = x2apic_target_cpus, |
| 112 | .vector_allocation_domain = x2apic_vector_allocation_domain, |
| 113 | .apic_id_registered = x2apic_apic_id_registered, |
| 114 | .init_apic_ldr = init_x2apic_ldr, |
| 115 | .send_IPI_all = x2apic_send_IPI_all, |
| 116 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, |
| 117 | .send_IPI_mask = x2apic_send_IPI_mask, |
| 118 | .send_IPI_self = x2apic_send_IPI_self, |
| 119 | .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, |
| 120 | .phys_pkg_id = phys_pkg_id, |
| 121 | .read_apic_id = x2apic_read_id, |
| 122 | }; |