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review.evervolv.com / android_kernel_htc_msm8960 / 32f960e9439bbe72c45f8cd854049254122fc198 / . / arch / powerpc / boot / dts / mpc8544ds.dts
blob: e238ebb4596eaf1da43732cb6bd6c15cd4462ad5 [file] [log] [blame]
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]1/*
2 * MPC8544 DS Device Tree Source
3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]12/dts-v1/;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]13/ {
14 model = "MPC8544DS";
15 compatible = "MPC8544DS", "MPC85xxDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 pci3 = &pci3;
28 };
29
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]30 cpus {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]31 #cpus = <0x1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8544@0 {
36 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]45 };
46 };
47
48 memory {
49 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]50 reg = <0x0 0x0>; // Filled by U-Boot
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]51 };
52
53 soc8544@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]56 device_type = "soc";
Kumar Galab66510c2007-08-16 23:55:55 -0500[diff] [blame]57
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]58 ranges = <0x0 0xe0000000 0x100000>;
59 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]60 bus-frequency = <0>; // Filled out by uboot.
61
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]62 memory-controller@2000 {
63 compatible = "fsl,8544-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]64 reg = <0x2000 0x1000>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]65 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]66 interrupts = <18 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]67 };
68
69 l2-cache-controller@20000 {
70 compatible = "fsl,8544-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; // 32 bytes
73 cache-size = <0x40000>; // L2, 256K
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]74 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]75 interrupts = <16 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]76 };
77
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]78 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]79 #address-cells = <1>;
80 #size-cells = <0>;
81 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]82 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]83 reg = <0x3000 0x100>;
84 interrupts = <43 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]85 interrupt-parent = <&mpic>;
86 dfsrr;
87 };
88
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]89 i2c@3100 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 cell-index = <1>;
93 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]94 reg = <0x3100 0x100>;
95 interrupts = <43 2>;
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]96 interrupt-parent = <&mpic>;
97 dfsrr;
98 };
99
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]100 mdio@24520 {
101 #address-cells = <1>;
102 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]103 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]104 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]105
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]106 phy0: ethernet-phy@0 {
107 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]108 interrupts = <10 1>;
109 reg = <0x0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]110 device_type = "ethernet-phy";
111 };
112 phy1: ethernet-phy@1 {
113 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]114 interrupts = <10 1>;
115 reg = <0x1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]116 device_type = "ethernet-phy";
117 };
118 };
119
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]120 dma@21300 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]124 reg = <0x21300 0x4>;
125 ranges = <0x0 0x21100 0x200>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]126 cell-index = <0>;
127 dma-channel@0 {
128 compatible = "fsl,mpc8544-dma-channel",
129 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]130 reg = <0x0 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]131 cell-index = <0>;
132 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]133 interrupts = <20 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]134 };
135 dma-channel@80 {
136 compatible = "fsl,mpc8544-dma-channel",
137 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]138 reg = <0x80 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]139 cell-index = <1>;
140 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]141 interrupts = <21 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]142 };
143 dma-channel@100 {
144 compatible = "fsl,mpc8544-dma-channel",
145 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]146 reg = <0x100 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]147 cell-index = <2>;
148 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]149 interrupts = <22 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]150 };
151 dma-channel@180 {
152 compatible = "fsl,mpc8544-dma-channel",
153 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]154 reg = <0x180 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]155 cell-index = <3>;
156 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]157 interrupts = <23 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]158 };
159 };
160
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]161 enet0: ethernet@24000 {
162 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]163 device_type = "network";
164 model = "TSEC";
165 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]166 reg = <0x24000 0x1000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]167 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]168 interrupts = <29 2 30 2 34 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]169 interrupt-parent = <&mpic>;
170 phy-handle = <&phy0>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500[diff] [blame]171 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]172 };
173
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]174 enet1: ethernet@26000 {
175 cell-index = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]176 device_type = "network";
177 model = "TSEC";
178 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]179 reg = <0x26000 0x1000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]180 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]181 interrupts = <31 2 32 2 33 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]182 interrupt-parent = <&mpic>;
183 phy-handle = <&phy1>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500[diff] [blame]184 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]185 };
186
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]187 serial0: serial@4500 {
188 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]189 device_type = "serial";
190 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]191 reg = <0x4500 0x100>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]192 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]193 interrupts = <42 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]194 interrupt-parent = <&mpic>;
195 };
196
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]197 serial1: serial@4600 {
198 cell-index = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]199 device_type = "serial";
200 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]201 reg = <0x4600 0x100>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]202 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]203 interrupts = <42 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]204 interrupt-parent = <&mpic>;
205 };
206
Roy Zang10ce8c62007-07-13 17:35:33 +0800[diff] [blame]207 global-utilities@e0000 { //global utilities block
208 compatible = "fsl,mpc8548-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]209 reg = <0xe0000 0x1000>;
Roy Zang10ce8c62007-07-13 17:35:33 +0800[diff] [blame]210 fsl,has-rstcr;
211 };
212
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]213 mpic: pic@40000 {
214 clock-frequency = <0>;
215 interrupt-controller;
216 #address-cells = <0>;
217 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]218 reg = <0x40000 0x40000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]219 compatible = "chrp,open-pic";
220 device_type = "open-pic";
221 big-endian;
222 };
223 };
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]224
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]225 pci0: pci@e0008000 {
226 cell-index = <0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]227 compatible = "fsl,mpc8540-pci";
228 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]229 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]230 interrupt-map = <
231
232 /* IDSEL 0x11 J17 Slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]233 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
234 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
235 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
236 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]237
238 /* IDSEL 0x12 J16 Slot 2 */
239
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]240 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
241 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
242 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
243 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]244
245 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]246 interrupts = <24 2>;
247 bus-range = <0 255>;
248 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
249 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
250 clock-frequency = <66666666>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]251 #interrupt-cells = <1>;
252 #size-cells = <2>;
253 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]254 reg = <0xe0008000 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]255 };
256
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]257 pci1: pcie@e0009000 {
258 cell-index = <1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]259 compatible = "fsl,mpc8548-pcie";
260 device_type = "pci";
261 #interrupt-cells = <1>;
262 #size-cells = <2>;
263 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]264 reg = <0xe0009000 0x1000>;
265 bus-range = <0 255>;
266 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
267 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
268 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]269 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]270 interrupts = <26 2>;
271 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]272 interrupt-map = <
273 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]274 0000 0x0 0x0 0x1 &mpic 0x4 0x1
275 0000 0x0 0x0 0x2 &mpic 0x5 0x1
276 0000 0x0 0x0 0x3 &mpic 0x6 0x1
277 0000 0x0 0x0 0x4 &mpic 0x7 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]278 >;
279 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]280 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]281 #size-cells = <2>;
282 #address-cells = <3>;
283 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]284 ranges = <0x2000000 0x0 0x80000000
285 0x2000000 0x0 0x80000000
286 0x0 0x20000000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]287
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]288 0x1000000 0x0 0x0
289 0x1000000 0x0 0x0
290 0x0 0x10000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]291 };
292 };
293
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]294 pci2: pcie@e000a000 {
295 cell-index = <2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]296 compatible = "fsl,mpc8548-pcie";
297 device_type = "pci";
298 #interrupt-cells = <1>;
299 #size-cells = <2>;
300 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]301 reg = <0xe000a000 0x1000>;
302 bus-range = <0 255>;
303 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
304 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
305 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]306 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]307 interrupts = <25 2>;
308 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]309 interrupt-map = <
310 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]311 0000 0x0 0x0 0x1 &mpic 0x0 0x1
312 0000 0x0 0x0 0x2 &mpic 0x1 0x1
313 0000 0x0 0x0 0x3 &mpic 0x2 0x1
314 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]315 >;
316 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]317 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]318 #size-cells = <2>;
319 #address-cells = <3>;
320 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]321 ranges = <0x2000000 0x0 0xa0000000
322 0x2000000 0x0 0xa0000000
323 0x0 0x10000000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]324
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]325 0x1000000 0x0 0x0
326 0x1000000 0x0 0x0
327 0x0 0x10000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]328 };
329 };
330
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]331 pci3: pcie@e000b000 {
332 cell-index = <3>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]333 compatible = "fsl,mpc8548-pcie";
334 device_type = "pci";
335 #interrupt-cells = <1>;
336 #size-cells = <2>;
337 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]338 reg = <0xe000b000 0x1000>;
339 bus-range = <0 255>;
340 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
341 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
342 clock-frequency = <33333333>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]343 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]344 interrupts = <27 2>;
345 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]346 interrupt-map = <
347 // IDSEL 0x1c USB
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]348 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
349 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
350 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
351 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]352
353 // IDSEL 0x1d Audio
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]354 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]355
356 // IDSEL 0x1e Legacy
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]357 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
358 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]359
360 // IDSEL 0x1f IDE/SATA
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]361 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
362 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]363 >;
364
365 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]366 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]367 #size-cells = <2>;
368 #address-cells = <3>;
369 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]370 ranges = <0x2000000 0x0 0xb0000000
371 0x2000000 0x0 0xb0000000
372 0x0 0x100000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]373
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]374 0x1000000 0x0 0x0
375 0x1000000 0x0 0x0
376 0x0 0x100000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]377
378 uli1575@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]379 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]380 #size-cells = <2>;
381 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]382 ranges = <0x2000000 0x0 0xb0000000
383 0x2000000 0x0 0xb0000000
384 0x0 0x100000
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]385
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]386 0x1000000 0x0 0x0
387 0x1000000 0x0 0x0
388 0x0 0x100000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]389 isa@1e {
390 device_type = "isa";
391 #interrupt-cells = <2>;
392 #size-cells = <1>;
393 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]394 reg = <0xf000 0x0 0x0 0x0 0x0>;
395 ranges = <0x1 0x0
396 0x1000000 0x0 0x0
397 0x1000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]398 interrupt-parent = <&i8259>;
399
400 i8259: interrupt-controller@20 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]401 reg = <0x1 0x20 0x2
402 0x1 0xa0 0x2
403 0x1 0x4d0 0x2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]404 interrupt-controller;
405 device_type = "interrupt-controller";
406 #address-cells = <0>;
407 #interrupt-cells = <2>;
408 compatible = "chrp,iic";
409 interrupts = <9 2>;
410 interrupt-parent = <&mpic>;
411 };
412
413 i8042@60 {
414 #size-cells = <0>;
415 #address-cells = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]416 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
417 interrupts = <1 3 12 3>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]418 interrupt-parent = <&i8259>;
419
420 keyboard@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]421 reg = <0x0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]422 compatible = "pnpPNP,303";
423 };
424
425 mouse@1 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]426 reg = <0x1>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]427 compatible = "pnpPNP,f03";
428 };
429 };
430
431 rtc@70 {
432 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]433 reg = <0x1 0x70 0x2>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]434 };
435
436 gpio@400 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame^]437 reg = <0x1 0x400 0x80>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]438 };
439 };
440 };
441 };
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500[diff] [blame]442 };
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]443};