blob: b4f9b000368501301672a2f073eb86cc12711252 [file] [log] [blame]
Jassi Brar5033f432010-11-22 15:37:25 +09001/* sound/soc/samsung/ac97.c
Jassi Brarfc93ea22010-01-27 14:59:08 +09002 *
3 * ALSA SoC Audio Layer - S3C AC97 Controller driver
4 * Evolved from s3c2443-ac97.c
5 *
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Author: Jaswinder Singh <jassi.brar@samsung.com>
8 * Credits: Graeme Gregory, Sean Choi
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Jassi Brarfc93ea22010-01-27 14:59:08 +090015#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/clk.h>
18
19#include <sound/soc.h>
20
Jassi Brarfc93ea22010-01-27 14:59:08 +090021#include <mach/dma.h>
Seungwhan Youn0378b6a2011-01-11 07:26:06 +090022#include <plat/regs-ac97.h>
Jassi Brarfc93ea22010-01-27 14:59:08 +090023#include <plat/audio.h>
24
Jassi Brar4b640cf2010-11-22 15:35:57 +090025#include "dma.h"
Jassi Brarfc93ea22010-01-27 14:59:08 +090026
27#define AC_CMD_ADDR(x) (x << 16)
28#define AC_CMD_DATA(x) (x & 0xffff)
29
Seungwhan Youn4f644ea2011-01-07 13:46:52 +090030#define S3C_AC97_DAI_PCM 0
31#define S3C_AC97_DAI_MIC 1
32
Jassi Brarfc93ea22010-01-27 14:59:08 +090033struct s3c_ac97_info {
Jassi Brarfc93ea22010-01-27 14:59:08 +090034 struct clk *ac97_clk;
35 void __iomem *regs;
36 struct mutex lock;
37 struct completion done;
38};
39static struct s3c_ac97_info s3c_ac97;
40
41static struct s3c2410_dma_client s3c_dma_client_out = {
42 .name = "AC97 PCMOut"
43};
44
45static struct s3c2410_dma_client s3c_dma_client_in = {
46 .name = "AC97 PCMIn"
47};
48
49static struct s3c2410_dma_client s3c_dma_client_micin = {
50 .name = "AC97 MicIn"
51};
52
53static struct s3c_dma_params s3c_ac97_pcm_out = {
54 .client = &s3c_dma_client_out,
55 .dma_size = 4,
56};
57
58static struct s3c_dma_params s3c_ac97_pcm_in = {
59 .client = &s3c_dma_client_in,
60 .dma_size = 4,
61};
62
63static struct s3c_dma_params s3c_ac97_mic_in = {
64 .client = &s3c_dma_client_micin,
65 .dma_size = 4,
66};
67
68static void s3c_ac97_activate(struct snd_ac97 *ac97)
69{
70 u32 ac_glbctrl, stat;
71
72 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
73 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
74 return; /* Return if already active */
75
76 INIT_COMPLETION(s3c_ac97.done);
77
78 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
79 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
80 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
81 msleep(1);
82
83 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
84 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
85 msleep(1);
86
87 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
88 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
89 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
90
91 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
Mark Brown4a6f9982010-09-23 16:48:54 +010092 pr_err("AC97: Unable to activate!");
Jassi Brarfc93ea22010-01-27 14:59:08 +090093}
94
95static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
96 unsigned short reg)
97{
98 u32 ac_glbctrl, ac_codec_cmd;
99 u32 stat, addr, data;
100
101 mutex_lock(&s3c_ac97.lock);
102
103 s3c_ac97_activate(ac97);
104
105 INIT_COMPLETION(s3c_ac97.done);
106
107 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
108 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
109 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
110
111 udelay(50);
112
113 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
114 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
115 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
116
117 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
Mark Brown4a6f9982010-09-23 16:48:54 +0100118 pr_err("AC97: Unable to read!");
Jassi Brarfc93ea22010-01-27 14:59:08 +0900119
120 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
121 addr = (stat >> 16) & 0x7f;
122 data = (stat & 0xffff);
123
124 if (addr != reg)
Jassi Brar99ce3a32010-11-22 15:36:03 +0900125 pr_err("ac97: req addr = %02x, rep addr = %02x\n",
Mark Brown4a6f9982010-09-23 16:48:54 +0100126 reg, addr);
Jassi Brarfc93ea22010-01-27 14:59:08 +0900127
128 mutex_unlock(&s3c_ac97.lock);
129
130 return (unsigned short)data;
131}
132
133static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
134 unsigned short val)
135{
136 u32 ac_glbctrl, ac_codec_cmd;
137
138 mutex_lock(&s3c_ac97.lock);
139
140 s3c_ac97_activate(ac97);
141
142 INIT_COMPLETION(s3c_ac97.done);
143
144 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
145 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
146 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
147
148 udelay(50);
149
150 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
151 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
152 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
153
154 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
Mark Brown4a6f9982010-09-23 16:48:54 +0100155 pr_err("AC97: Unable to write!");
Jassi Brarfc93ea22010-01-27 14:59:08 +0900156
157 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
158 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
159 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
160
161 mutex_unlock(&s3c_ac97.lock);
162}
163
164static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
165{
Mark Brown8d85d742010-09-23 17:41:46 +0100166 pr_debug("AC97: Cold reset\n");
Jassi Brarfc93ea22010-01-27 14:59:08 +0900167 writel(S3C_AC97_GLBCTRL_COLDRESET,
168 s3c_ac97.regs + S3C_AC97_GLBCTRL);
169 msleep(1);
170
171 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
172 msleep(1);
173}
174
175static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
176{
177 u32 stat;
178
179 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
180 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
181 return; /* Return if already active */
182
Mark Brown8d85d742010-09-23 17:41:46 +0100183 pr_debug("AC97: Warm reset\n");
184
Jassi Brarfc93ea22010-01-27 14:59:08 +0900185 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
186 msleep(1);
187
188 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
189 msleep(1);
190
191 s3c_ac97_activate(ac97);
192}
193
194static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
195{
196 u32 ac_glbctrl, ac_glbstat;
197
198 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
199
200 if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
201
202 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
203 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
204 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
205
206 complete(&s3c_ac97.done);
207 }
208
209 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
210 ac_glbctrl |= (1<<30); /* Clear interrupt */
211 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
212
213 return IRQ_HANDLED;
214}
215
216struct snd_ac97_bus_ops soc_ac97_ops = {
217 .read = s3c_ac97_read,
218 .write = s3c_ac97_write,
219 .warm_reset = s3c_ac97_warm_reset,
220 .reset = s3c_ac97_cold_reset,
221};
222EXPORT_SYMBOL_GPL(soc_ac97_ops);
223
224static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
225 struct snd_pcm_hw_params *params,
226 struct snd_soc_dai *dai)
227{
228 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000229 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Daniel Mack5f712b22010-03-22 10:11:15 +0100230 struct s3c_dma_params *dma_data;
Jassi Brarfc93ea22010-01-27 14:59:08 +0900231
232 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Daniel Mack5f712b22010-03-22 10:11:15 +0100233 dma_data = &s3c_ac97_pcm_out;
Jassi Brarfc93ea22010-01-27 14:59:08 +0900234 else
Daniel Mack5f712b22010-03-22 10:11:15 +0100235 dma_data = &s3c_ac97_pcm_in;
236
237 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
Jassi Brarfc93ea22010-01-27 14:59:08 +0900238
239 return 0;
240}
241
242static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
243 struct snd_soc_dai *dai)
244{
245 u32 ac_glbctrl;
246 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Daniel Mack5f712b22010-03-22 10:11:15 +0100247 struct s3c_dma_params *dma_data =
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000248 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
Jassi Brarfc93ea22010-01-27 14:59:08 +0900249
250 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
251 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
252 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
253 else
254 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
255
256 switch (cmd) {
257 case SNDRV_PCM_TRIGGER_START:
258 case SNDRV_PCM_TRIGGER_RESUME:
259 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
260 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
261 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
262 else
263 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
264 break;
265
266 case SNDRV_PCM_TRIGGER_STOP:
267 case SNDRV_PCM_TRIGGER_SUSPEND:
268 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
269 break;
270 }
271
272 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
273
Boojin Kim344b4c42011-09-02 09:44:43 +0900274 if (!dma_data->ops)
275 dma_data->ops = samsung_dma_get_ops();
276
277 dma_data->ops->started(dma_data->channel);
Jassi Brarfc93ea22010-01-27 14:59:08 +0900278
279 return 0;
280}
281
282static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
283 struct snd_pcm_hw_params *params,
284 struct snd_soc_dai *dai)
285{
286 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000287 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Jassi Brarfc93ea22010-01-27 14:59:08 +0900288
289 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
290 return -ENODEV;
291 else
Daniel Mack5f712b22010-03-22 10:11:15 +0100292 snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
Jassi Brarfc93ea22010-01-27 14:59:08 +0900293
294 return 0;
295}
296
297static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
298 int cmd, struct snd_soc_dai *dai)
299{
300 u32 ac_glbctrl;
301 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Daniel Mack5f712b22010-03-22 10:11:15 +0100302 struct s3c_dma_params *dma_data =
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000303 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
Jassi Brarfc93ea22010-01-27 14:59:08 +0900304
305 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
306 ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
307
308 switch (cmd) {
309 case SNDRV_PCM_TRIGGER_START:
310 case SNDRV_PCM_TRIGGER_RESUME:
311 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
312 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
313 break;
314
315 case SNDRV_PCM_TRIGGER_STOP:
316 case SNDRV_PCM_TRIGGER_SUSPEND:
317 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
318 break;
319 }
320
321 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
322
Boojin Kim344b4c42011-09-02 09:44:43 +0900323 if (!dma_data->ops)
324 dma_data->ops = samsung_dma_get_ops();
325
326 dma_data->ops->started(dma_data->channel);
Jassi Brarfc93ea22010-01-27 14:59:08 +0900327
328 return 0;
329}
330
331static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
332 .hw_params = s3c_ac97_hw_params,
333 .trigger = s3c_ac97_trigger,
334};
335
336static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
337 .hw_params = s3c_ac97_hw_mic_params,
338 .trigger = s3c_ac97_mic_trigger,
339};
340
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000341static struct snd_soc_dai_driver s3c_ac97_dai[] = {
Jassi Brarfc93ea22010-01-27 14:59:08 +0900342 [S3C_AC97_DAI_PCM] = {
Jassi Brar99ce3a32010-11-22 15:36:03 +0900343 .name = "samsung-ac97",
Jassi Brarfc93ea22010-01-27 14:59:08 +0900344 .ac97_control = 1,
345 .playback = {
346 .stream_name = "AC97 Playback",
347 .channels_min = 2,
348 .channels_max = 2,
349 .rates = SNDRV_PCM_RATE_8000_48000,
350 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
351 .capture = {
352 .stream_name = "AC97 Capture",
353 .channels_min = 2,
354 .channels_max = 2,
355 .rates = SNDRV_PCM_RATE_8000_48000,
356 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
357 .ops = &s3c_ac97_dai_ops,
358 },
359 [S3C_AC97_DAI_MIC] = {
Jassi Brar99ce3a32010-11-22 15:36:03 +0900360 .name = "samsung-ac97-mic",
Jassi Brarfc93ea22010-01-27 14:59:08 +0900361 .ac97_control = 1,
362 .capture = {
363 .stream_name = "AC97 Mic Capture",
364 .channels_min = 1,
365 .channels_max = 1,
366 .rates = SNDRV_PCM_RATE_8000_48000,
367 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
368 .ops = &s3c_ac97_mic_dai_ops,
369 },
370};
Jassi Brarfc93ea22010-01-27 14:59:08 +0900371
372static __devinit int s3c_ac97_probe(struct platform_device *pdev)
373{
374 struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
375 struct s3c_audio_pdata *ac97_pdata;
376 int ret;
377
378 ac97_pdata = pdev->dev.platform_data;
379 if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
380 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
381 return -EINVAL;
382 }
383
384 /* Check for availability of necessary resource */
385 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
386 if (!dmatx_res) {
387 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
388 return -ENXIO;
389 }
390
391 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
392 if (!dmarx_res) {
393 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
394 return -ENXIO;
395 }
396
397 dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
398 if (!dmamic_res) {
399 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
400 return -ENXIO;
401 }
402
403 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
404 if (!mem_res) {
405 dev_err(&pdev->dev, "Unable to get register resource\n");
406 return -ENXIO;
407 }
408
409 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
410 if (!irq_res) {
411 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
412 return -ENXIO;
413 }
414
415 if (!request_mem_region(mem_res->start,
Jassi Brar99ce3a32010-11-22 15:36:03 +0900416 resource_size(mem_res), "ac97")) {
Jassi Brarfc93ea22010-01-27 14:59:08 +0900417 dev_err(&pdev->dev, "Unable to request register region\n");
418 return -EBUSY;
419 }
420
421 s3c_ac97_pcm_out.channel = dmatx_res->start;
422 s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
423 s3c_ac97_pcm_in.channel = dmarx_res->start;
424 s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
425 s3c_ac97_mic_in.channel = dmamic_res->start;
426 s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
427
428 init_completion(&s3c_ac97.done);
429 mutex_init(&s3c_ac97.lock);
430
431 s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
432 if (s3c_ac97.regs == NULL) {
433 dev_err(&pdev->dev, "Unable to ioremap register region\n");
434 ret = -ENXIO;
435 goto err1;
436 }
437
438 s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
439 if (IS_ERR(s3c_ac97.ac97_clk)) {
Jassi Brar99ce3a32010-11-22 15:36:03 +0900440 dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n");
Jassi Brarfc93ea22010-01-27 14:59:08 +0900441 ret = -ENODEV;
442 goto err2;
443 }
444 clk_enable(s3c_ac97.ac97_clk);
445
446 if (ac97_pdata->cfg_gpio(pdev)) {
447 dev_err(&pdev->dev, "Unable to configure gpio\n");
448 ret = -EINVAL;
449 goto err3;
450 }
451
452 ret = request_irq(irq_res->start, s3c_ac97_irq,
453 IRQF_DISABLED, "AC97", NULL);
454 if (ret < 0) {
Jassi Brar99ce3a32010-11-22 15:36:03 +0900455 dev_err(&pdev->dev, "ac97: interrupt request failed.\n");
Jassi Brarfc93ea22010-01-27 14:59:08 +0900456 goto err4;
457 }
458
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000459 ret = snd_soc_register_dais(&pdev->dev, s3c_ac97_dai,
460 ARRAY_SIZE(s3c_ac97_dai));
Jassi Brarfc93ea22010-01-27 14:59:08 +0900461 if (ret)
462 goto err5;
463
464 return 0;
465
466err5:
467 free_irq(irq_res->start, NULL);
468err4:
469err3:
470 clk_disable(s3c_ac97.ac97_clk);
471 clk_put(s3c_ac97.ac97_clk);
472err2:
473 iounmap(s3c_ac97.regs);
474err1:
475 release_mem_region(mem_res->start, resource_size(mem_res));
476
477 return ret;
478}
479
480static __devexit int s3c_ac97_remove(struct platform_device *pdev)
481{
482 struct resource *mem_res, *irq_res;
483
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000484 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(s3c_ac97_dai));
Jassi Brarfc93ea22010-01-27 14:59:08 +0900485
486 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
487 if (irq_res)
488 free_irq(irq_res->start, NULL);
489
490 clk_disable(s3c_ac97.ac97_clk);
491 clk_put(s3c_ac97.ac97_clk);
492
493 iounmap(s3c_ac97.regs);
494
495 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
496 if (mem_res)
497 release_mem_region(mem_res->start, resource_size(mem_res));
498
499 return 0;
500}
501
502static struct platform_driver s3c_ac97_driver = {
503 .probe = s3c_ac97_probe,
504 .remove = s3c_ac97_remove,
505 .driver = {
Jassi Brare6104672010-11-22 15:36:00 +0900506 .name = "samsung-ac97",
Jassi Brarfc93ea22010-01-27 14:59:08 +0900507 .owner = THIS_MODULE,
508 },
509};
510
511static int __init s3c_ac97_init(void)
512{
513 return platform_driver_register(&s3c_ac97_driver);
514}
515module_init(s3c_ac97_init);
516
517static void __exit s3c_ac97_exit(void)
518{
519 platform_driver_unregister(&s3c_ac97_driver);
520}
521module_exit(s3c_ac97_exit);
522
523MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
524MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
525MODULE_LICENSE("GPL");
Jassi Brare6104672010-11-22 15:36:00 +0900526MODULE_ALIAS("platform:samsung-ac97");