Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_htc_msm8960 / 350b6938953e9a806d34a315ed4185ae32b47142 / . / arch / arm / boot / dts / msm8974.dtsi
blob: de1d54f2568dfdf0b5de2389d2855177659ce2da [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Kevin Chan350b6932012-08-01 02:21:00 -0700[diff] [blame^]16/include/ "msm8974-camera.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]17/include/ "msm-gdsc.dtsi"
Pu Chen1335e872012-08-01 08:45:25 -0600[diff] [blame]18/include/ "msm8974-gpu.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]19
20/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]21 model = "Qualcomm MSM 8974";
22 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]23 interrupt-parent = <&intc>;
24
25 intc: interrupt-controller@F9000000 {
26 compatible = "qcom,msm-qgic2";
27 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]28 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]29 reg = <0xF9000000 0x1000>,
30 <0xF9002000 0x1000>;
31 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]32
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]33 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]34 compatible = "qcom,msm-gpio";
35 interrupt-controller;
36 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]37 reg = <0xfd510000 0x4000>;
38 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]39 };
40
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]41 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]42 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]43 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]44 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]45 };
46
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]47 qcom,vidc@fdc00000 {
48 compatible = "qcom,msm-vidc";
49 reg = <0xfdc00000 0xff000>;
50 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -0700[diff] [blame]51 vidc-cp-map = <0x1000000 0x40000000>;
52 vidc-ns-map = <0x40000000 0x40000000>;
Vinay Kalia40680aa2012-07-23 12:45:39 -0700[diff] [blame]53 load-freq-tbl = <979200 410000000>,
54 <560145 266670000>,
55 <421161 200000000>,
56 <243000 133330000>,
57 <108000 100000000>,
58 <36000 50000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]59 };
60
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]61 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]62 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]63 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]64 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]65 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]66
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]67 serial@f995e000 {
68 compatible = "qcom,msm-lsuart-v14";
69 reg = <0xf995e000 0x1000>;
70 interrupts = <0 114 0>;
71 };
72
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]73 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]74 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]75 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]76 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]77 HSUSB_VDDCX-supply = <&pm8841_s2>;
78 HSUSB_1p8-supply = <&pm8941_l6>;
79 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]80
81 qcom,hsusb-otg-phy-type = <2>;
82 qcom,hsusb-otg-mode = <1>;
83 qcom,hsusb-otg-otg-control = <1>;
84 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]85
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]86 qcom,sdcc@f9824000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]87 cell-index = <1>; /* SDC1 eMMC slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]88 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]89 reg = <0xf9824000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]90 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]91 interrupts = <0 123 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]92 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]93 vdd-supply = <&pm8941_l20>;
94 vdd-io-supply = <&pm8941_s3>;
95
96 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
97 qcom,sdcc-vdd-current_level = <800 500000>;
98
99 qcom,sdcc-vdd-io-always_on;
100 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
101 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]102
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]103 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
104 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
105 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
106 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
107
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]108 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
109 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]110 qcom,sdcc-bus-width = <8>;
111 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]112 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]113 };
114
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]115 qcom,sdcc@f98a4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]116 cell-index = <2>; /* SDC2 SD card slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]117 compatible = "qcom,msm-sdcc";
118 reg = <0xf98a4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]119 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]120 interrupts = <0 125 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]121 interrupt-names = "core_irq";
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]122 vdd-supply = <&pm8941_l21>;
123 vdd-io-supply = <&pm8941_l13>;
124
125 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
126 qcom,sdcc-vdd-current_level = <9000 800000>;
127
128 qcom,sdcc-vdd-io-always_on;
129 qcom,sdcc-vdd-io-lpm_sup;
130 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
131 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]132
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]133 qcom,sdcc-pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
134 qcom,sdcc-pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
135 qcom,sdcc-pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
136 qcom,sdcc-pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
137
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]138 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
139 qcom,sdcc-sup-voltages = <2950 2950>;
140 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]141 qcom,sdcc-xpc;
142 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
143 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]144 };
145
146 qcom,sdcc@f9864000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]147 cell-index = <3>; /* SDC3 SDIO slot */
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]148 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]149 reg = <0xf9864000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]150 reg-names = "core_mem";
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]151 interrupts = <0 127 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]152 interrupt-names = "core_irq";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]153
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]154 gpios = <&msmgpio 40 0>, /* CLK */
155 <&msmgpio 39 0>, /* CMD */
156 <&msmgpio 38 0>, /* DATA0 */
157 <&msmgpio 37 0>, /* DATA1 */
158 <&msmgpio 36 0>, /* DATA2 */
159 <&msmgpio 35 0>; /* DATA3 */
160 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
161
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]162 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
163 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]164 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]165 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]166 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]167 };
168
169 qcom,sdcc@f98e4000 {
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]170 cell-index = <4>; /* SDC4 SDIO slot */
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]171 compatible = "qcom,msm-sdcc";
172 reg = <0xf98e4000 0x1000>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]173 reg-names = "core_mem";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]174 interrupts = <0 129 0>;
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +0530[diff] [blame]175 interrupt-names = "core_irq";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]176
Sujit Reddy Thumma38459152012-06-26 00:07:59 +0530[diff] [blame]177 gpios = <&msmgpio 93 0>, /* CLK */
178 <&msmgpio 91 0>, /* CMD */
179 <&msmgpio 96 0>, /* DATA0 */
180 <&msmgpio 95 0>, /* DATA1 */
181 <&msmgpio 94 0>, /* DATA2 */
182 <&msmgpio 92 0>; /* DATA3 */
183 qcom,sdcc-gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
184
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]185 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
186 qcom,sdcc-sup-voltages = <1800 1800>;
187 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]188 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]189 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]190 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]191
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]192 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]193 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]194 reg = <0xf9984000 0x15000>,
195 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]196 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]197
198 qcom,bam-dma-res-pipes = <6>;
199 };
200
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]201
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]202 spi@f9924000 {
203 compatible = "qcom,spi-qup-v2";
204 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]205 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]206 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]207 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]208
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]209 slim@fe12f000 {
210 cell-index = <1>;
211 compatible = "qcom,slim-msm";
212 reg = <0xfe12f000 0x35000>,
213 <0xfe104000 0x20000>;
214 reg-names = "slimbus_physical", "slimbus_bam_physical";
215 interrupts = <0 163 0 0 164 0>;
216 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
217 qcom,min-clk-gear = <10>;
218 };
219
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]220 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]221 cell-index = <0>;
222 compatible = "qcom,spmi-pmic-arb";
223 reg = <0xfc4cf000 0x1000>,
224 <0Xfc4cb000 0x1000>;
225 /* 190,ee0_krait_hlos_spmi_periph_irq */
226 /* 187,channel_0_krait_hlos_trans_done_irq */
227 interrupts = <0 190 0 0 187 0>;
228 qcom,pmic-arb-ee = <0>;
229 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]230 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
231 <0x13100001>, /* PM8941_LDO2 */
232 <0x13200002>, /* PM8941_LDO3 */
233 <0x13300003>, /* PM8941_LDO4 */
234 <0x13400004>, /* PM8941_LDO5 */
235 <0x13500005>, /* PM8941_LDO6 */
236 <0x13600006>, /* PM8941_LDO7 */
237 <0x13700007>, /* PM8941_LDO8 */
238 <0x13800008>, /* PM8941_LDO9 */
239 <0x13900009>, /* PM8941_LDO10 */
240 <0x13a0000a>, /* PM8941_LDO11 */
241 <0x13b0000b>, /* PM8941_LDO12 */
242 <0x13c0000c>, /* PM8941_LDO13 */
243 <0x13d0000d>, /* PM8941_LDO14 */
244 <0x13e0000e>, /* PM8941_LDO15 */
245 <0x13f0000f>, /* PM8941_LDO16 */
246 <0x14000010>, /* PM8941_LDO17 */
247 <0x14100011>, /* PM8941_LDO18 */
248 <0x14200012>, /* PM8941_LDO19 */
249 <0x14300013>, /* PM8941_LDO20 */
250 <0x14400014>, /* PM8941_LDO21 */
251 <0x14500015>, /* PM8941_LDO22 */
252 <0x14600016>, /* PM8941_LDO23 */
253 <0x14700017>, /* PM8941_LDO24 */
254 <0x14800018>, /* PM8941_LDO25 */
255 <0x14900019>, /* PM8941_LDO26 */
256 <0x0c00001a>, /* PM8941_GPIO1 */
257 <0x0c10001b>, /* PM8941_GPIO2 */
258 <0x0c20001c>, /* PM8941_GPIO3 */
259 <0x0c30001d>, /* PM8941_GPIO4 */
260 <0x0c40001e>, /* PM8941_GPIO5 */
261 <0x0c50001f>, /* PM8941_GPIO6 */
262 <0x0c600020>, /* PM8941_GPIO7 */
263 <0x0c700021>, /* PM8941_GPIO8 */
264 <0x0c800022>, /* PM8941_GPIO9 */
265 <0x0c900023>, /* PM8941_GPIO10 */
266 <0x0ca00024>, /* PM8941_GPIO11 */
267 <0x0cb00025>, /* PM8941_GPIO12 */
268 <0x0cc00026>, /* PM8941_GPIO13 */
269 <0x0cd00027>, /* PM8941_GPIO14 */
270 <0x0ce00028>, /* PM8941_GPIO15 */
271 <0x0cf00029>, /* PM8941_GPIO16 */
272 <0x0d00002a>, /* PM8941_GPIO17 */
273 <0x0d10002b>, /* PM8941_GPIO18 */
274 <0x0d20002c>, /* PM8941_GPIO19 */
275 <0x0d30002d>, /* PM8941_GPIO20 */
276 <0x0d40002e>, /* PM8941_GPIO21 */
277 <0x0d50002f>, /* PM8941_GPIO22 */
278 <0x0d600030>, /* PM8941_GPIO23 */
279 <0x0d700031>, /* PM8941_GPIO24 */
280 <0x0d800032>, /* PM8941_GPIO25 */
281 <0x0d900033>, /* PM8941_GPIO26 */
282 <0x0da00034>, /* PM8941_GPIO27 */
283 <0x0db00035>, /* PM8941_GPIO28 */
284 <0x0dc00036>, /* PM8941_GPIO29 */
285 <0x0dd00037>, /* PM8941_GPIO30 */
286 <0x0de00038>, /* PM8941_GPIO31 */
287 <0x0df00039>, /* PM8941_GPIO32 */
288 <0x0e00003a>, /* PM8941_GPIO33 */
289 <0x0e10003b>, /* PM8941_GPIO34 */
290 <0x0e20003c>, /* PM8941_GPIO35 */
291 <0x0e30003d>, /* PM8941_GPIO36 */
292 <0x0280003e>, /* COINCELL */
293 <0x0100003f>, /* SMBC_OVP */
294 <0x01100040>, /* SMBC_CHG */
295 <0x01200041>, /* SMBC_BIF */
296 <0x00500042>, /* INTERRUPT */
297 <0x00100043>, /* PM8941_0 */
298 <0x20100044>, /* PM8841_0 */
299 <0x10100045>, /* PM8941_1 */
300 <0x30100046>, /* PM8841_1 */
301 <0x00800047>, /* PON0 */
302 <0x20800048>, /* PON1 */
303 <0x11000049>, /* PM8941_SMPS1 */
304 <0x1110004a>, /* PM8941_SMPS2 */
305 <0x1120004b>, /* PM8941_SMPS3 */
306 <0x3100004c>, /* PM8841_SMPS1 */
307 <0x3110004d>, /* PM8841_SMPS2 */
308 <0x3120004e>, /* PM8841_SMPS3 */
309 <0x3130004f>, /* PM8841_SMPS4 */
310 <0x31400050>, /* PM8841_SMPS5 */
311 <0x31500051>, /* PM8841_SMPS6 */
312 <0x31600052>, /* PM8841_SMPS7 */
313 <0x31700053>, /* PM8841_SMPS8 */
314 <0x05000054>, /* SHARED_XO */
315 <0x05100055>, /* BB_CLK1 */
316 <0x05200056>, /* BB_CLK2 */
317 <0x05900057>, /* SLEEP_CLK */
318 <0x07000058>, /* PBS_CORE */
319 <0x07100059>, /* PBS_CLIENT1 */
320 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]321 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]322
323 i2c@f9966000 {
324 cell-index = <0>;
325 compatible = "qcom,i2c-qup";
326 reg = <0Xf9966000 0x1000>;
327 reg-names = "qup_phys_addr";
328 interrupts = <0 104 0>;
329 interrupt-names = "qup_err_intr";
330 qcom,i2c-bus-freq = <100000>;
331 qcom,i2c-src-freq = <24000000>;
332 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]333
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]334 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]335 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]336 krait0-supply = <&krait0_vreg>;
337 krait1-supply = <&krait1_vreg>;
338 krait2-supply = <&krait2_vreg>;
339 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]340 krait0_mem-supply = <&pm8841_s1_ao>;
341 krait1_mem-supply = <&pm8841_s1_ao>;
342 krait2_mem-supply = <&pm8841_s1_ao>;
343 krait3_mem-supply = <&pm8841_s1_ao>;
344 krait0_dig-supply = <&pm8841_s2_corner_ao>;
345 krait1_dig-supply = <&pm8841_s2_corner_ao>;
346 krait2_dig-supply = <&pm8841_s2_corner_ao>;
347 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]348 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
349 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
350 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
351 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
352 l2_hfpll_a-supply = <&pm8941_s2_ao>;
353 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
354 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
355 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
356 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
357 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]358 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]359
360 qcom,ssusb@F9200000 {
361 compatible = "qcom,dwc-usb3-msm";
Manu Gautam8c642812012-06-07 10:35:10 +0530[diff] [blame]362 reg = <0xF9200000 0xFA000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]363 interrupts = <0 131 0 0 179 0>;
364 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]365 SSUSB_VDDCX-supply = <&pm8841_s2>;
366 SSUSB_1p8-supply = <&pm8941_l6>;
367 HSUSB_VDDCX-supply = <&pm8841_s2>;
368 HSUSB_1p8-supply = <&pm8941_l6>;
369 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]370 qcom,dwc-usb3-msm-dbm-eps = <4>;
371 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]372
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]373 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
374 parent-supply = <&pm8841_s4>;
375 };
376
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]377 qcom,lpass@fe200000 {
378 compatible = "qcom,pil-q6v5-lpass";
379 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]380 <0xfd485100 0x00010>;
381
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]382 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]383 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]384
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]385 qcom,msm-pcm {
386 compatible = "qcom,msm-pcm-dsp";
387 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]388
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]389 qcom,msm-pcm-routing {
390 compatible = "qcom,msm-pcm-routing";
391 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]392
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]393 qcom,msm-pcm-lpa {
394 compatible = "qcom,msm-pcm-lpa";
395 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]396
Harmandeep Singha3453a72012-07-03 12:31:09 -0700[diff] [blame]397 qcom,msm-compr-dsp {
398 compatible = "qcom,msm-compr-dsp";
399 };
400
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]401 qcom,msm-voip-dsp {
402 compatible = "qcom,msm-voip-dsp";
403 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]404
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]405 qcom,msm-stub-codec {
406 compatible = "qcom,msm-stub-codec";
407 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]408
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]409 qcom,msm-dai-fe {
410 compatible = "qcom,msm-dai-fe";
411 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]412
Joonwoo Park6572ac52012-07-10 17:17:00 -0700[diff] [blame]413 qcom,msm-dai-q6 {
414 compatible = "qcom,msm-dai-q6";
415 qcom,msm-dai-q6-sb-0-rx {
416 compatible = "qcom,msm-dai-q6-dev";
417 qcom,msm-dai-q6-dev-id = <16384>;
418 };
419
420 qcom,msm-dai-q6-sb-0-tx {
421 compatible = "qcom,msm-dai-q6-dev";
422 qcom,msm-dai-q6-dev-id = <16385>;
423 };
424 };
425
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]426 qcom,msm-auxpcm {
427 compatible = "qcom,msm-auxpcm-resource";
428 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
429 qcom,msm-cpudai-auxpcm-mode = <0>;
430 qcom,msm-cpudai-auxpcm-sync = <1>;
431 qcom,msm-cpudai-auxpcm-frame = <5>;
432 qcom,msm-cpudai-auxpcm-quant = <2>;
433 qcom,msm-cpudai-auxpcm-slot = <1>;
434 qcom,msm-cpudai-auxpcm-data = <0>;
435 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]436
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]437 qcom,msm-auxpcm-rx {
438 qcom,msm-auxpcm-dev-id = <4106>;
439 compatible = "qcom,msm-auxpcm-dev";
440 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]441
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]442 qcom,msm-auxpcm-tx {
443 qcom,msm-auxpcm-dev-id = <4107>;
444 compatible = "qcom,msm-auxpcm-dev";
445 };
446 };
447
448 qcom,msm-pcm-hostless {
449 compatible = "qcom,msm-pcm-hostless";
450 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]451
Phani Kumar Uppalapati8b3a1bb2012-06-26 19:56:58 -0700[diff] [blame]452 qcom,msm-ocmem-audio {
453 compatible = "qcom,msm-ocmem-audio";
454 qcom,msm-ocmem-audio-src-id = <11>;
455 qcom,msm-ocmem-audio-dst-id = <604>;
456 qcom,msm-ocmem-audio-ab = <32505856>;
457 qcom,msm-ocmem-audio-ib = <32505856>;
458 };
459
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]460 qcom,mss@fc880000 {
461 compatible = "qcom,pil-q6v5-mss";
462 reg = <0xfc880000 0x100>,
463 <0xfd485000 0x400>,
464 <0xfc820000 0x020>,
465 <0xfc401680 0x004>;
466 vdd_mss-supply = <&pm8841_s3>;
467
468 qcom,firmware-name = "mba";
469 qcom,pil-self-auth = <1>;
470 };
471
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]472 qcom,mba@fc820000 {
473 compatible = "qcom,pil-mba";
474 reg = <0xfc820000 0x0020>,
475 <0x0d1fc000 0x4000>;
476
477 qcom,firmware-name = "modem";
478 qcom,depends-on = "mba";
479 };
480
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]481 qcom,pronto@fb21b000 {
482 compatible = "qcom,pil-pronto";
483 reg = <0xfb21b000 0x3000>,
484 <0xfc401700 0x4>,
485 <0xfd485300 0xc>;
486 vdd_pronto_pll-supply = <&pm8941_l12>;
487
488 qcom,firmware-name = "wcnss";
489 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]490
491 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]492 compatible = "qcom,msm-ocmem";
493 reg = <0xfdd00000 0x2000>,
494 <0xfdd02000 0x2000>,
495 <0xfe039000 0x400>,
496 <0xfec00000 0x180000>;
497 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
498 interrupts = <0 76 0 0 77 0>;
499 interrupt-names = "ocmem_irq", "dm_irq";
500 qcom,ocmem-num-regions = <0x3>;
501 #address-cells = <1>;
502 #size-cells = <1>;
503 ranges = <0x0 0xfec00000 0x180000>;
504
505 partition@0 {
506 reg = <0x0 0x100000>;
507 qcom,ocmem-part-name = "graphics";
508 qcom,ocmem-part-min = <0x80000>;
509 };
510
511 partition@80000 {
512 reg = <0x80000 0xA0000>;
513 qcom,ocmem-part-name = "lp_audio";
514 qcom,ocmem-part-min = <0xA0000>;
515 };
516
517 partition@E0000 {
518 reg = <0x120000 0x20000>;
Naveen Ramarajcc4ec152012-05-14 09:55:29 -0700[diff] [blame]519 qcom,ocmem-part-name = "other_os";
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]520 qcom,ocmem-part-min = <0x20000>;
521 };
522
523 partition@100000 {
524 reg = <0x100000 0x80000>;
525 qcom,ocmem-part-name = "video";
526 qcom,ocmem-part-min = <0x55000>;
527 };
528
529 partition@140000 {
530 reg = <0x140000 0x40000>;
531 qcom,ocmem-part-name = "sensors";
532 qcom,ocmem-part-min = <0x40000>;
533 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]534 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]535
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]536 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]537 compatible = "qcom,rpm-smd";
538 rpm-channel-name = "rpm_requests";
539 rpm-channel-type = <15>; /* SMD_APPS_RPM */
540 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]541
542 qcom,msm-rng@f9bff000 {
543 compatible = "qcom,msm-rng";
544 reg = <0xf9bff000 0x200>;
545 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]546
547 qcom,qseecom@fe806000 {
548 compatible = "qcom,qseecom";
549 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]550
551 qcom,mdss_mdp@fd900000 {
552 cell-index = <0>;
553 compatible = "qcom,mdss_mdp";
554 reg = <0xfd900000 0x22100>;
555 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]556 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]557 };
558
559 qcom,mdss_wb_panel {
560 cell-index = <1>;
561 compatible = "qcom,mdss_wb";
562 qcom,mdss_pan_res = <640 480>;
563 qcom,mdss_pan_bpp = <24>;
564 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]565
566 qcom,wdt@f9017000 {
567 compatible = "qcom,msm-watchdog";
568 reg = <0xf9017000 0x1000>;
569 interrupts = <0 3 0 0 4 0>;
570 qcom,bark-time = <11000>;
571 qcom,pet-time = <10000>;
572 qcom,ipi-ping = <1>;
573 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]574
575 qcom,tz-log@fe805720 {
576 compatible = "qcom,tz-log";
577 reg = <0xfe805720 0x1000>;
578 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]579
580 qcom,venus@fdce0000 {
581 compatible = "qcom,pil-venus";
582 reg = <0xfdce0000 0x4000>,
583 <0xfdc80208 0x8>;
584 vdd-supply = <&gdsc_venus>;
585
586 qcom,firmware-name = "venus";
587 qcom,firmware-min-paddr = <0xF500000>;
588 qcom,firmware-max-paddr = <0xFA00000>;
589 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]590
Stepan Moskovchenkoc79a7382012-07-19 17:24:32 -0700[diff] [blame]591 qcom,cache_erp {
592 compatible = "qcom,cache_erp";
593 interrupts = <1 9 0>, <0 2 0>;
594 interrupt-names = "l1_irq", "l2_irq";
595 };
596
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]597 tsens@fc4a8000 {
598 compatible = "qcom,msm-tsens";
599 reg = <0xfc4a8000 0x2000>,
600 <0xfc4b80d0 0x5>;
601 reg-names = "tsens_physical", "tsens_eeprom_physical";
602 interrupts = <0 184 0>;
603 qcom,sensors = <11>;
Siddartha Mohanadoss205bce62012-07-27 17:17:18 -0700[diff] [blame]604 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
605 3200 3200>;
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]606 };
Laura Abbottf7e44042012-06-22 12:50:32 -0700[diff] [blame]607
608 qcom,msm-rtb {
609 compatible = "qcom,msm-rtb";
610 qcom,memory-reservation-type = "EBI1";
611 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
612 };
Mona Hossainb43e94b2012-05-07 08:52:06 -0700[diff] [blame]613
614 qcom,qcedev@fd440000 {
615 compatible = "qcom,qcedev";
616 reg = <0xfd440000 0x20000>,
617 <0xfd444000 0x8000>;
618 interrupts = <0 235 0>;
619 qcom,bam-pipes = <0>;
620 };
621
622 qcom,qcrypto@fd444000 {
623 compatible = "qcom,qcrypto";
624 reg = <0xfd440000 0x20000>,
625 <0xfd444000 0x8000>;
626 interrupts = <0 235 0>;
627 qcom,bam-pipes = <1>;
628 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]629};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]630
631/include/ "msm-pm8x41-rpm-regulator.dtsi"
632/include/ "msm-pm8841.dtsi"
633/include/ "msm-pm8941.dtsi"
634/include/ "msm8974-regulator.dtsi"
635/include/ "msm8974-gpio.dtsi"