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review.evervolv.com / android_kernel_htc_msm8960 / 382b00b9a664fa0bd9b8d8bee2dae3f4340d425d / . / drivers / video / msm / mdp4_util.c
blob: 645d5a85f85e38285624b1f83d2ada115008700c [file] [log] [blame]
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]1/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/hrtimer.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/debugfs.h>
25#include <linux/semaphore.h>
26#include <linux/uaccess.h>
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]27#include <linux/msm_mdp.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]28#include <asm/system.h>
29#include <asm/mach-types.h>
30#include <mach/hardware.h>
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]31#include <mach/iommu_domains.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]32#include "mdp.h"
33#include "msm_fb.h"
34#include "mdp4.h"
35
36struct mdp4_statistic mdp4_stat;
37
38unsigned is_mdp4_hw_reset(void)
39{
40 unsigned hw_reset = 0;
41
42 /* Only revisions > v2.1 may be reset or powered off/on at runtime */
43 if (mdp_hw_revision > MDP4_REVISION_V2_1) {
44 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
45 hw_reset = !inpdw(MDP_BASE + 0x003c);
46 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
47 }
48
49 return hw_reset;
50}
51
52void mdp4_sw_reset(ulong bits)
53{
54 /* MDP cmd block enable */
55 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
56
57 bits &= 0x1f; /* 5 bits */
58 outpdw(MDP_BASE + 0x001c, bits); /* MDP_SW_RESET */
59
60 while (inpdw(MDP_BASE + 0x001c) & bits) /* self clear when complete */
61 ;
62 /* MDP cmd block disable */
63 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
64
65 MSM_FB_DEBUG("mdp4_sw_reset: 0x%x\n", (int)bits);
66}
67
68void mdp4_overlay_cfg(int overlayer, int blt_mode, int refresh, int direct_out)
69{
70 ulong bits = 0;
71
72 if (blt_mode)
73 bits |= (1 << 3);
74 refresh &= 0x03; /* 2 bites */
75 bits |= (refresh << 1);
76 direct_out &= 0x01;
77 bits |= direct_out;
78 /* MDP cmd block enable */
79 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
80
81
82 if (overlayer == MDP4_MIXER0)
83 outpdw(MDP_BASE + 0x10004, bits); /* MDP_OVERLAY0_CFG */
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]84 else if (overlayer == MDP4_MIXER1)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]85 outpdw(MDP_BASE + 0x18004, bits); /* MDP_OVERLAY1_CFG */
86
87 MSM_FB_DEBUG("mdp4_overlay_cfg: 0x%x\n",
88 (int)inpdw(MDP_BASE + 0x10004));
89 /* MDP cmd block disable */
90 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
91}
92
93void mdp4_display_intf_sel(int output, ulong intf)
94{
95 ulong bits, mask, data;
96 /* MDP cmd block enable */
97 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
98
99 bits = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */
100
101 if (intf == DSI_VIDEO_INTF) {
102 data = 0x40; /* bit 6 */
103 intf = MDDI_LCDC_INTF;
104 if (output == SECONDARY_INTF_SEL) {
105 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
106 intf=%d\n", __func__, output, (int)intf);
107 }
108 } else if (intf == DSI_CMD_INTF) {
109 data = 0x80; /* bit 7 */
110 intf = MDDI_INTF;
111 if (output == EXTERNAL_INTF_SEL) {
112 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
113 intf=%d\n", __func__, output, (int)intf);
114 }
115 } else
116 data = 0;
117
118 mask = 0x03; /* 2 bits */
119 intf &= 0x03; /* 2 bits */
120
121 switch (output) {
122 case EXTERNAL_INTF_SEL:
123 intf <<= 4;
124 mask <<= 4;
125 break;
126 case SECONDARY_INTF_SEL:
127 intf &= 0x02; /* only MDDI and EBI2 support */
128 intf <<= 2;
129 mask <<= 2;
130 break;
131 default:
132 break;
133 }
134
135 intf |= data;
136 mask |= data;
137
138 bits &= ~mask;
139 bits |= intf;
140
141 outpdw(MDP_BASE + 0x0038, bits); /* MDP_DISP_INTF_SEL */
142 /* MDP cmd block disable */
143 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
144
145 MSM_FB_DEBUG("mdp4_display_intf_sel: 0x%x\n", (int)inpdw(MDP_BASE + 0x0038));
146}
147
148unsigned long mdp4_display_status(void)
149{
150 ulong status;
151 /* MDP cmd block enable */
152 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
153
154 status = inpdw(MDP_BASE + 0x0018) & 0x3ff; /* MDP_DISPLAY_STATUS */
155
156 /* MDP cmd block disable */
157 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
158 return status;
159}
160
161void mdp4_ebi2_lcd_setup(int lcd, ulong base, int ystride)
162{
163 /* always use memory map */
164 ystride &= 0x01fff; /* 13 bits */
165 /* MDP cmd block enable */
166 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
167
168 if (lcd == EBI2_LCD0) {
169 outpdw(MDP_BASE + 0x0060, base);/* MDP_EBI2_LCD0 */
170 outpdw(MDP_BASE + 0x0068, ystride);/* MDP_EBI2_LCD0_YSTRIDE */
171 } else {
172 outpdw(MDP_BASE + 0x0064, base);/* MDP_EBI2_LCD1 */
173 outpdw(MDP_BASE + 0x006c, ystride);/* MDP_EBI2_LCD1_YSTRIDE */
174 }
175 /* MDP cmd block disable */
176 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
177}
178
179void mdp4_mddi_setup(int mddi, unsigned long id)
180{
181 ulong bits;
182
183 if (mddi == MDDI_EXTERNAL_SET)
184 bits = 0x02;
185 else if (mddi == MDDI_SECONDARY_SET)
186 bits = 0x01;
187 else
188 bits = 0; /* PRIMARY_SET */
189
190 id <<= 16;
191
192 bits |= id;
193 /* MDP cmd block enable */
194 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
195
196 outpdw(MDP_BASE + 0x0090, bits); /* MDP_MDDI_PARAM_WR_SEL */
197 /* MDP cmd block disable */
198 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
199}
200
201int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req)
202{
203
204 /* not implemented yet */
205 return -1;
206}
207
208void mdp4_fetch_cfg(uint32 core_clk)
209{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]210 uint32 dmap_data, vg_data;
211 char *base;
212 int i;
213 /* MDP cmd block enable */
214 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
215
Adrian Salido-Moreno3436dae2011-08-08 12:13:07 -0700[diff] [blame]216 if (mdp_rev >= MDP_REV_41 || core_clk >= 90000000) { /* 90 Mhz */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]217 dmap_data = 0x47; /* 16 bytes-burst x 8 req */
218 vg_data = 0x47; /* 16 bytes-burs x 8 req */
219 } else {
220 dmap_data = 0x27; /* 8 bytes-burst x 8 req */
221 vg_data = 0x43; /* 16 bytes-burst x 4 req */
222 }
223
224 MSM_FB_DEBUG("mdp4_fetch_cfg: dmap=%x vg=%x\n",
225 dmap_data, vg_data);
226
227 /* dma_p fetch config */
228 outpdw(MDP_BASE + 0x91004, dmap_data);
229 /* dma_e fetch config */
230 outpdw(MDP_BASE + 0xB1004, dmap_data);
231
232 /*
233 * set up two vg pipes and two rgb pipes
234 */
235 base = MDP_BASE + MDP4_VIDEO_BASE;
236 for (i = 0; i < 4; i++) {
237 outpdw(base + 0x1004, vg_data);
238 base += MDP4_VIDEO_OFF;
239 }
240 /* MDP cmd block disable */
241 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
242}
243
244void mdp4_hw_init(void)
245{
246 ulong bits;
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]247 uint32 clk_rate;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]248
249 /* MDP cmd block enable */
250 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
251
Nagamalleswararao Ganji074ee022011-09-02 12:06:37 -0700[diff] [blame]252 mdp4_update_perf_level(OVERLAY_PERF_LEVEL4);
253
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]254#ifdef MDP4_ERROR
255 /*
256 * Issue software reset on DMA_P will casue DMA_P dma engine stall
257 * on LCDC mode. However DMA_P does not stall at MDDI mode.
258 * This need further investigation.
259 */
260 mdp4_sw_reset(0x17);
261#endif
262
kuogee hsieh4b910f22011-11-15 09:43:04 -0800[diff] [blame]263 if (mdp_rev > MDP_REV_41) {
264 /* mdp chip select controller */
265 outpdw(MDP_BASE + 0x00c0, CS_CONTROLLER_0);
266 outpdw(MDP_BASE + 0x00c4, CS_CONTROLLER_1);
267 }
268
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]269 mdp4_clear_lcdc();
270
271 mdp4_mixer_blend_init(0);
272 mdp4_mixer_blend_init(1);
273 mdp4_vg_qseed_init(0);
274 mdp4_vg_qseed_init(1);
275
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]276 mdp4_vg_csc_setup(0);
277 mdp4_vg_csc_setup(1);
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]278 mdp4_mixer_csc_setup(1);
279 mdp4_mixer_csc_setup(2);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]280 mdp4_dmap_csc_setup();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]281
Ravishangar Kalyaname7833e22011-07-22 16:20:19 -0700[diff] [blame]282 if (mdp_rev <= MDP_REV_41) {
283 mdp4_mixer_gc_lut_setup(0);
284 mdp4_mixer_gc_lut_setup(1);
285 }
286
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]287 mdp4_vg_igc_lut_setup(0);
288 mdp4_vg_igc_lut_setup(1);
289
290 mdp4_rgb_igc_lut_setup(0);
291 mdp4_rgb_igc_lut_setup(1);
292
293 outp32(MDP_EBI2_PORTMAP_MODE, 0x3);
294
295 /* system interrupts */
296
297 bits = mdp_intr_mask;
298 outpdw(MDP_BASE + 0x0050, bits);/* enable specififed interrupts */
299
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]300 /* For the max read pending cmd config below, if the MDP clock */
301 /* is less than the AXI clock, then we must use 3 pending */
302 /* pending requests. Otherwise, we should use 8 pending requests. */
303 /* In the future we should do this detection automatically. */
304
305 /* max read pending cmd config */
306 outpdw(MDP_BASE + 0x004c, 0x02222); /* 3 pending requests */
307
308#ifndef CONFIG_FB_MSM_OVERLAY
309 /* both REFRESH_MODE and DIRECT_OUT are ignored at BLT mode */
310 mdp4_overlay_cfg(MDP4_MIXER0, OVERLAY_MODE_BLT, 0, 0);
311 mdp4_overlay_cfg(MDP4_MIXER1, OVERLAY_MODE_BLT, 0, 0);
312#endif
313
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]314 clk_rate = mdp_get_core_clk();
315 mdp4_fetch_cfg(clk_rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]316
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800[diff] [blame]317 mdp4_overlay_cfg_init();
318
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]319 /* Mark hardware as initialized. Only revisions > v2.1 have a register
320 * for tracking core reset status. */
321 if (mdp_hw_revision > MDP4_REVISION_V2_1)
322 outpdw(MDP_BASE + 0x003c, 1);
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]323
324 /* MDP cmd block disable */
325 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]326}
327
328
329void mdp4_clear_lcdc(void)
330{
331 uint32 bits;
332
333 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
334
335 bits = inpdw(MDP_BASE + 0xc0000);
336 if (bits & 0x01) { /* enabled already */
337 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
338 return;
339 }
340
341 outpdw(MDP_BASE + 0xc0004, 0); /* vsync ctrl out */
342 outpdw(MDP_BASE + 0xc0008, 0); /* vsync period */
343 outpdw(MDP_BASE + 0xc000c, 0); /* vsync pusle width */
344 outpdw(MDP_BASE + 0xc0010, 0); /* lcdc display HCTL */
345 outpdw(MDP_BASE + 0xc0014, 0); /* lcdc display v start */
346 outpdw(MDP_BASE + 0xc0018, 0); /* lcdc display v end */
347 outpdw(MDP_BASE + 0xc001c, 0); /* lcdc active hctl */
348 outpdw(MDP_BASE + 0xc0020, 0); /* lcdc active v start */
349 outpdw(MDP_BASE + 0xc0024, 0); /* lcdc active v end */
350 outpdw(MDP_BASE + 0xc0028, 0); /* lcdc board color */
351 outpdw(MDP_BASE + 0xc002c, 0); /* lcdc underflow ctrl */
352 outpdw(MDP_BASE + 0xc0030, 0); /* lcdc hsync skew */
353 outpdw(MDP_BASE + 0xc0034, 0); /* lcdc test ctl */
354 outpdw(MDP_BASE + 0xc0038, 0); /* lcdc ctl polarity */
355
356 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
357}
358
359irqreturn_t mdp4_isr(int irq, void *ptr)
360{
361 uint32 isr, mask, panel;
362 struct mdp_dma_data *dma;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]363 struct mdp_hist_mgmt *mgmt = NULL;
364 char *base_addr;
365 int i, ret;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]366
367 mdp_is_in_isr = TRUE;
368
369 /* complete all the reads before reading the interrupt
370 * status register - eliminate effects of speculative
371 * reads by the cpu
372 */
373 rmb();
374 isr = inpdw(MDP_INTR_STATUS);
375 if (isr == 0)
376 goto out;
377
378 mdp4_stat.intr_tot++;
379 mask = inpdw(MDP_INTR_ENABLE);
380 outpdw(MDP_INTR_CLEAR, isr);
381
382 if (isr & INTR_PRIMARY_INTF_UDERRUN) {
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800[diff] [blame]383 pr_debug("%s: UNDERRUN -- primary\n", __func__);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]384 mdp4_stat.intr_underrun_p++;
385 /* When underun occurs mdp clear the histogram registers
386 that are set before in hw_init so restore them back so
387 that histogram works.*/
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]388 for (i = 0; i < MDP_HIST_MGMT_MAX; i++) {
389 mgmt = mdp_hist_mgmt_array[i];
390 if (!mgmt)
391 continue;
392 base_addr = MDP_BASE + mgmt->base;
393 MDP_OUTP(base_addr + 0x010, 1);
394 outpdw(base_addr + 0x01c, INTR_HIST_DONE |
395 INTR_HIST_RESET_SEQ_DONE);
396 mgmt->mdp_is_hist_valid = FALSE;
397 __mdp_histogram_reset(mgmt);
398 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]399 }
400
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800[diff] [blame]401 if (isr & INTR_EXTERNAL_INTF_UDERRUN) {
402 pr_debug("%s: UNDERRUN -- external\n", __func__);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]403 mdp4_stat.intr_underrun_e++;
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800[diff] [blame]404 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]405
406 isr &= mask;
407
408 if (isr == 0)
409 goto out;
410
411 panel = mdp4_overlay_panel_list();
412 if (isr & INTR_PRIMARY_VSYNC) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]413 mdp4_stat.intr_vsync_p++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]414 dma = &dma2_data;
415 spin_lock(&mdp_spin_lock);
416 mdp_intr_mask &= ~INTR_PRIMARY_VSYNC;
417 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
418 dma->waiting = FALSE;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]419 if (panel & MDP4_PANEL_LCDC)
420 mdp4_primary_vsync_lcdc();
421#ifdef CONFIG_FB_MSM_MIPI_DSI
422 else if (panel & MDP4_PANEL_DSI_VIDEO)
423 mdp4_primary_vsync_dsi_video();
424#endif
kuogee hsieh3de11f32011-07-08 14:09:11 -0700[diff] [blame]425 spin_unlock(&mdp_spin_lock);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]426 }
427#ifdef CONFIG_FB_MSM_DTV
428 if (isr & INTR_EXTERNAL_VSYNC) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]429 mdp4_stat.intr_vsync_e++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]430 dma = &dma_e_data;
431 spin_lock(&mdp_spin_lock);
432 mdp_intr_mask &= ~INTR_EXTERNAL_VSYNC;
433 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
434 dma->waiting = FALSE;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]435 if (panel & MDP4_PANEL_DTV)
436 mdp4_external_vsync_dtv();
kuogee hsieh3de11f32011-07-08 14:09:11 -0700[diff] [blame]437 spin_unlock(&mdp_spin_lock);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]438 }
439#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]440
441#ifdef CONFIG_FB_MSM_OVERLAY
442 if (isr & INTR_OVERLAY0_DONE) {
443 mdp4_stat.intr_overlay0++;
444 dma = &dma2_data;
445 if (panel & (MDP4_PANEL_LCDC | MDP4_PANEL_DSI_VIDEO)) {
446 /* disable LCDC interrupt */
447 spin_lock(&mdp_spin_lock);
448 mdp_intr_mask &= ~INTR_OVERLAY0_DONE;
449 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
450 dma->waiting = FALSE;
451 spin_unlock(&mdp_spin_lock);
452 if (panel & MDP4_PANEL_LCDC)
453 mdp4_overlay0_done_lcdc(dma);
454#ifdef CONFIG_FB_MSM_MIPI_DSI
455 else if (panel & MDP4_PANEL_DSI_VIDEO)
456 mdp4_overlay0_done_dsi_video(dma);
457#endif
458 } else { /* MDDI, DSI_CMD */
459#ifdef CONFIG_FB_MSM_MIPI_DSI
460 if (panel & MDP4_PANEL_DSI_CMD)
461 mdp4_overlay0_done_dsi_cmd(dma);
462#else
463 if (panel & MDP4_PANEL_MDDI)
464 mdp4_overlay0_done_mddi(dma);
465#endif
466 }
467 mdp_hw_cursor_done();
468 }
469 if (isr & INTR_OVERLAY1_DONE) {
470 mdp4_stat.intr_overlay1++;
471 /* disable DTV interrupt */
472 dma = &dma_e_data;
473 spin_lock(&mdp_spin_lock);
474 mdp_intr_mask &= ~INTR_OVERLAY1_DONE;
475 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
476 dma->waiting = FALSE;
477 spin_unlock(&mdp_spin_lock);
478#if defined(CONFIG_FB_MSM_DTV)
479 if (panel & MDP4_PANEL_DTV)
480 mdp4_overlay1_done_dtv();
481#endif
482#if defined(CONFIG_FB_MSM_TVOUT)
483 if (panel & MDP4_PANEL_ATV)
484 mdp4_overlay1_done_atv();
485#endif
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]486 }
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]487#if defined(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL)
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]488 if (isr & INTR_OVERLAY2_DONE) {
489 mdp4_stat.intr_overlay2++;
490 /* disable DTV interrupt */
491 dma = &dma_wb_data;
492 spin_lock(&mdp_spin_lock);
493 mdp_intr_mask &= ~INTR_OVERLAY2_DONE;
494 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
495 dma->waiting = FALSE;
496 spin_unlock(&mdp_spin_lock);
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]497 if (panel & MDP4_PANEL_WRITEBACK)
498 mdp4_overlay1_done_writeback(dma);
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]499 }
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]500#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]501#endif /* OVERLAY */
502
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]503 if (isr & INTR_DMA_P_DONE) {
504 mdp4_stat.intr_dma_p++;
505 dma = &dma2_data;
506 if (panel & MDP4_PANEL_LCDC) {
507 /* disable LCDC interrupt */
508 spin_lock(&mdp_spin_lock);
509 mdp_intr_mask &= ~INTR_DMA_P_DONE;
510 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
511 dma->waiting = FALSE;
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]512 mdp4_dma_p_done_lcdc();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]513 spin_unlock(&mdp_spin_lock);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]514 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]515#ifdef CONFIG_FB_MSM_OVERLAY
516#ifdef CONFIG_FB_MSM_MIPI_DSI
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]517 else if (panel & MDP4_PANEL_DSI_VIDEO) {
518 /* disable LCDC interrupt */
519 spin_lock(&mdp_spin_lock);
520 mdp_intr_mask &= ~INTR_DMA_P_DONE;
521 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
522 dma->waiting = FALSE;
Kuogee Hsieh5ff2cb62012-04-11 10:43:07 -0700[diff] [blame]523 mdp4_dma_p_done_dsi_video(dma);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]524 spin_unlock(&mdp_spin_lock);
525 } else if (panel & MDP4_PANEL_DSI_CMD) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]526 mdp4_dma_p_done_dsi(dma);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]527 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]528#else
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]529 else { /* MDDI */
Mayank Chopra33a7d722012-02-29 12:25:31 +0530[diff] [blame]530 mdp4_dma_p_done_mddi(dma);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]531 mdp_pipe_ctrl(MDP_DMA2_BLOCK,
532 MDP_BLOCK_POWER_OFF, TRUE);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]533 complete(&dma->comp);
534 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]535#endif
536#else
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]537 else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]538 spin_lock(&mdp_spin_lock);
539 dma->busy = FALSE;
540 spin_unlock(&mdp_spin_lock);
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -0700[diff] [blame]541 complete(&dma->comp);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]542 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]543#endif
544 }
545 if (isr & INTR_DMA_S_DONE) {
546 mdp4_stat.intr_dma_s++;
547#if defined(CONFIG_FB_MSM_OVERLAY) && defined(CONFIG_FB_MSM_MDDI)
548 dma = &dma2_data;
549#else
550 dma = &dma_s_data;
551#endif
552
553 dma->busy = FALSE;
554 mdp_pipe_ctrl(MDP_DMA_S_BLOCK,
555 MDP_BLOCK_POWER_OFF, TRUE);
556 complete(&dma->comp);
557 }
558 if (isr & INTR_DMA_E_DONE) {
559 mdp4_stat.intr_dma_e++;
560 dma = &dma_e_data;
561 spin_lock(&mdp_spin_lock);
562 mdp_intr_mask &= ~INTR_DMA_E_DONE;
563 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
564 dma->busy = FALSE;
Huaibin Yang0da46922011-11-29 15:08:04 -0800[diff] [blame]565 mdp4_dma_e_done_dtv();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]566 if (dma->waiting) {
567 dma->waiting = FALSE;
568 complete(&dma->comp);
569 }
570 spin_unlock(&mdp_spin_lock);
571 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]572 if (isr & INTR_DMA_P_HISTOGRAM) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]573 mdp4_stat.intr_histogram++;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]574 ret = mdp_histogram_block2mgmt(MDP_BLOCK_DMA_P, &mgmt);
575 if (!ret)
576 mdp_histogram_handle_isr(mgmt);
577 }
578 if (isr & INTR_DMA_S_HISTOGRAM) {
579 mdp4_stat.intr_histogram++;
580 ret = mdp_histogram_block2mgmt(MDP_BLOCK_DMA_S, &mgmt);
581 if (!ret)
582 mdp_histogram_handle_isr(mgmt);
583 }
584 if (isr & INTR_VG1_HISTOGRAM) {
585 mdp4_stat.intr_histogram++;
586 ret = mdp_histogram_block2mgmt(MDP_BLOCK_VG_1, &mgmt);
587 if (!ret)
588 mdp_histogram_handle_isr(mgmt);
589 }
590 if (isr & INTR_VG2_HISTOGRAM) {
591 mdp4_stat.intr_histogram++;
592 ret = mdp_histogram_block2mgmt(MDP_BLOCK_VG_2, &mgmt);
593 if (!ret)
594 mdp_histogram_handle_isr(mgmt);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]595 }
596
597out:
598 mdp_is_in_isr = FALSE;
599
600 return IRQ_HANDLED;
601}
602
603
604/*
605 * QSEED tables
606 */
607
608static uint32 vg_qseed_table0[] = {
609 0x5556aaff, 0x00000000, 0x00000000, 0x00000000
610};
611
612static uint32 vg_qseed_table1[] = {
Carl Vanderlipd89c0e72012-03-28 10:17:20 -0700[diff] [blame]613 0x00000000, 0x20000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]614};
615
616static uint32 vg_qseed_table2[] = {
617 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
618 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
619 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
620 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
621 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
622 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
623 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
624 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
625 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
626 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
627 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
628 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
629 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
630 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
631 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
632 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
633
634 0x02000000, 0x00000000, 0x02000000, 0x00000000,
635 0x02000000, 0x00000000, 0x02000000, 0x00000000,
636 0x02000000, 0x00000000, 0x02000000, 0x00000000,
637 0x02000000, 0x00000000, 0x02000000, 0x00000000,
638 0x02000000, 0x00000000, 0x02000000, 0x00000000,
639 0x02000000, 0x00000000, 0x02000000, 0x00000000,
640 0x02000000, 0x00000000, 0x02000000, 0x00000000,
641 0x02000000, 0x00000000, 0x02000000, 0x00000000,
642 0x02000000, 0x00000000, 0x02000000, 0x00000000,
643 0x02000000, 0x00000000, 0x02000000, 0x00000000,
644 0x02000000, 0x00000000, 0x02000000, 0x00000000,
645 0x02000000, 0x00000000, 0x02000000, 0x00000000,
646 0x02000000, 0x00000000, 0x02000000, 0x00000000,
647 0x02000000, 0x00000000, 0x02000000, 0x00000000,
648 0x02000000, 0x00000000, 0x02000000, 0x00000000,
649 0x02000000, 0x00000000, 0x02000000, 0x00000000,
650
651 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
652 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
653 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
654 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
655 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
656 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
657 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
658 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
659 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
660 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
661 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
662 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
663 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
664 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
665 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
666 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
667
668 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
669 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
670 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
671 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
672 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
673 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
674 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
675 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
676 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
677 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
678 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
679 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
680 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
681 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
682 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
683 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
684
685 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
686 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
687 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
688 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
689 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
690 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
691 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
692 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
693 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
694 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
695 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
696 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
697 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
698 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
699 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
700 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
701
702 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
703 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
704 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
705 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
706 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
707 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
708 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
709 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
710 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
711 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
712 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
713 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
714 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
715 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
716 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
717 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
718
719 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
720 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
721 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
722 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
723 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
724 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
725 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
726 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
727 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
728 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
729 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
730 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
731 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
732 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
733 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
734 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
735
736 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
737 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
738 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
739 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
740 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
741 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
742 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
743 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
744 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
745 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
746 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
747 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
748 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
749 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
750 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
751 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
752
753 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
754 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
755 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
756 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
757 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
758 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
759 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
760 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
761 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
762 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
763 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
764 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
765 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
766 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
767 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
768 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
769
770 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
771 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
772 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
773 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
774 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
775 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
776 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
777 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
778 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
779 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
780 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
781 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
782 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
783 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
784 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
785 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
786
787 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
788 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
789 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
790 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
791 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
792 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
793 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
794 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
795 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
796 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
797 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
798 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
799 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
800 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
801 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
802 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
803
804 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
805 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
806 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
807 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
808 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
809 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
810 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
811 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
812 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
813 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
814 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
815 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
816 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
817 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
818 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
819 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
820
821 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
822 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
823 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
824 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
825 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
826 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
827 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
828 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
829 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
830 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
831 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
832 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
833 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
834 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
835 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
836 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
837
838 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
839 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
840 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
841 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
842 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
843 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
844 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
845 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
846 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
847 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
848 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
849 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
850 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
851 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
852 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
853 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
854
855 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
856 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
857 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
858 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
859 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
860 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
861 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
862 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
863 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
864 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
865 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
866 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
867 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
868 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
869 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
870 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
871
872 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
873 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
874 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
875 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
876 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
877 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
878 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
879 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
880 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
881 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
882 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
883 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
884 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
885 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
886 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
887 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e,
888
889 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
890 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
891 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
892 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
893 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
894 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
895 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
896 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
897 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
898 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
899 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
900 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
901 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
902 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
903 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
904 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
905
906 0x02000000, 0x00000000, 0x02000000, 0x00000000,
907 0x02000000, 0x00000000, 0x02000000, 0x00000000,
908 0x02000000, 0x00000000, 0x02000000, 0x00000000,
909 0x02000000, 0x00000000, 0x02000000, 0x00000000,
910 0x02000000, 0x00000000, 0x02000000, 0x00000000,
911 0x02000000, 0x00000000, 0x02000000, 0x00000000,
912 0x02000000, 0x00000000, 0x02000000, 0x00000000,
913 0x02000000, 0x00000000, 0x02000000, 0x00000000,
914 0x02000000, 0x00000000, 0x02000000, 0x00000000,
915 0x02000000, 0x00000000, 0x02000000, 0x00000000,
916 0x02000000, 0x00000000, 0x02000000, 0x00000000,
917 0x02000000, 0x00000000, 0x02000000, 0x00000000,
918 0x02000000, 0x00000000, 0x02000000, 0x00000000,
919 0x02000000, 0x00000000, 0x02000000, 0x00000000,
920 0x02000000, 0x00000000, 0x02000000, 0x00000000,
921 0x02000000, 0x00000000, 0x02000000, 0x00000000,
922
923 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
924 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
925 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
926 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
927 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
928 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
929 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
930 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
931 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
932 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
933 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
934 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
935 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
936 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
937 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
938 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
939
940 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
941 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
942 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
943 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
944 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
945 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
946 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
947 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
948 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
949 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
950 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
951 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
952 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
953 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
954 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
955 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
956
957 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
958 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
959 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
960 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
961 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
962 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
963 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
964 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
965 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
966 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
967 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
968 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
969 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
970 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
971 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
972 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
973
974 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
975 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
976 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
977 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
978 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
979 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
980 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
981 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
982 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
983 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
984 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
985 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
986 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
987 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
988 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
989 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
990
991 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
992 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
993 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
994 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
995 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
996 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
997 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
998 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
999 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
1000 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
1001 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
1002 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
1003 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
1004 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
1005 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
1006 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
1007
1008 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
1009 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
1010 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
1011 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
1012 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
1013 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
1014 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
1015 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
1016 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
1017 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
1018 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
1019 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
1020 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
1021 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
1022 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
1023 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
1024
1025 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
1026 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
1027 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
1028 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
1029 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
1030 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
1031 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
1032 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
1033 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
1034 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
1035 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
1036 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
1037 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
1038 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
1039 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
1040 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
1041
1042 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
1043 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
1044 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
1045 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
1046 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
1047 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
1048 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
1049 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
1050 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
1051 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
1052 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
1053 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
1054 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
1055 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
1056 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
1057 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
1058
1059 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
1060 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
1061 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
1062 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
1063 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
1064 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
1065 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
1066 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
1067 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
1068 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
1069 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
1070 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
1071 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
1072 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
1073 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
1074 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
1075
1076 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
1077 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
1078 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
1079 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
1080 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
1081 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
1082 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
1083 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
1084 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
1085 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
1086 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
1087 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
1088 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
1089 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
1090 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
1091 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
1092
1093 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
1094 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
1095 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
1096 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
1097 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
1098 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
1099 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
1100 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
1101 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
1102 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
1103 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
1104 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
1105 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
1106 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
1107 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
1108 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
1109
1110 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
1111 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
1112 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
1113 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
1114 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
1115 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
1116 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
1117 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
1118 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
1119 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
1120 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
1121 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
1122 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
1123 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
1124 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
1125 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
1126
1127 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
1128 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
1129 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
1130 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
1131 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
1132 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
1133 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
1134 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
1135 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
1136 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
1137 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
1138 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
1139 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
1140 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
1141 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
1142 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
1143
1144 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
1145 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
1146 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
1147 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
1148 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
1149 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
1150 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
1151 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
1152 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
1153 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
1154 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
1155 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
1156 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
1157 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
1158 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
1159 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e
1160};
1161
1162
1163#define MDP4_QSEED_TABLE0_OFF 0x8100
1164#define MDP4_QSEED_TABLE1_OFF 0x8200
1165#define MDP4_QSEED_TABLE2_OFF 0x9000
1166
1167void mdp4_vg_qseed_init(int vp_num)
1168{
1169 uint32 *off;
1170 int i, voff;
1171
1172 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1173
1174 voff = MDP4_VIDEO_OFF * vp_num;
1175 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1176 MDP4_QSEED_TABLE0_OFF);
1177 for (i = 0; i < (sizeof(vg_qseed_table0) / sizeof(uint32)); i++) {
1178 outpdw(off, vg_qseed_table0[i]);
1179 off++;
1180 /* This code is added to workaround the 1K Boundary AXI
1181 Interleave operations from Scorpion that can potentially
1182 corrupt the QSEED table. The idea is to complete the prevous
1183 to the buffer before making the next write when address is
1184 1KB aligned to ensure the write has been committed prior to
1185 next instruction write that can go out from the secondary AXI
1186 port.This happens also because of the expected write sequence
1187 from QSEED table, where LSP has to be written first then the
1188 MSP to trigger both to write out to SRAM, if this has not been
1189 the expectation, then corruption wouldn't have happened.*/
1190
1191 if (!((uint32)off & 0x3FF))
1192 wmb();
1193 }
1194
1195 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1196 MDP4_QSEED_TABLE1_OFF);
1197 for (i = 0; i < (sizeof(vg_qseed_table1) / sizeof(uint32)); i++) {
1198 outpdw(off, vg_qseed_table1[i]);
1199 off++;
1200 if (!((uint32)off & 0x3FF))
1201 wmb();
1202 }
1203
1204 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1205 MDP4_QSEED_TABLE2_OFF);
1206 for (i = 0; i < (sizeof(vg_qseed_table2) / sizeof(uint32)); i++) {
1207 outpdw(off, vg_qseed_table2[i]);
1208 off++;
1209 if (!((uint32)off & 0x3FF))
1210 wmb();
1211 }
1212
1213 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1214
1215}
1216
1217void mdp4_mixer_blend_init(mixer_num)
1218{
1219 unsigned char *overlay_base;
1220 int off;
1221
1222 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1223 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1224 else
1225 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1226
1227 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1228
1229 /* stage 0 to stage 2 */
1230 off = 0;
1231 outpdw(overlay_base + off + 0x104, 0x010);
1232 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1233 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1234
1235 off += 0x20;
1236 outpdw(overlay_base + off + 0x104, 0x010);
1237 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1238 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1239
1240 off += 0x20;
1241 outpdw(overlay_base + off + 0x104, 0x010);
1242 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1243 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1244
1245 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1246}
1247
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1248struct mdp_csc_cfg mdp_csc_convert[4] = {
1249 { /*RGB2RGB*/
1250 0,
1251 {
1252 0x0200, 0x0000, 0x0000,
1253 0x0000, 0x0200, 0x0000,
1254 0x0000, 0x0000, 0x0200,
1255 },
1256 { 0x0, 0x0, 0x0, },
1257 { 0x0, 0x0, 0x0, },
1258 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1259 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1260 },
1261 { /*YUV2RGB*/
1262 0,
1263 {
1264 0x0254, 0x0000, 0x0331,
1265 0x0254, 0xff37, 0xfe60,
1266 0x0254, 0x0409, 0x0000,
1267 },
1268 { 0xfff0, 0xff80, 0xff80, },
1269 { 0x0, 0x0, 0x0, },
1270 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1271 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1272 },
1273 { /*RGB2YUV*/
1274 0,
1275 {
1276 0x0083, 0x0102, 0x0032,
1277 0x1fb5, 0x1f6c, 0x00e1,
1278 0x00e1, 0x1f45, 0x1fdc
1279 },
1280 { 0x0, 0x0, 0x0, },
1281 { 0x0010, 0x0080, 0x0080, },
1282 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1283 { 0x0010, 0x00eb, 0x0010, 0x00f0, 0x0010, 0x00f0, },
1284 },
1285 { /*YUV2YUV ???*/
1286 0,
1287 {
1288 0x0200, 0x0000, 0x0000,
1289 0x0000, 0x0200, 0x0000,
1290 0x0000, 0x0000, 0x0200,
1291 },
1292 { 0x0, 0x0, 0x0, },
1293 { 0x0, 0x0, 0x0, },
1294 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1295 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1296 },
1297};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1298
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1299struct mdp_csc_cfg csc_matrix[3] = {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1300 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1301 (MDP_CSC_FLAG_YUV_OUT),
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1302 {
1303 0x0254, 0x0000, 0x0331,
1304 0x0254, 0xff37, 0xfe60,
1305 0x0254, 0x0409, 0x0000,
1306 },
1307 {
1308 0xfff0, 0xff80, 0xff80,
1309 },
1310 {
1311 0, 0, 0,
1312 },
1313 {
1314 0, 0xff, 0, 0xff, 0, 0xff,
1315 },
1316 {
1317 0, 0xff, 0, 0xff, 0, 0xff,
1318 },
1319 },
1320 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1321 (MDP_CSC_FLAG_YUV_OUT),
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1322 {
1323 0x0254, 0x0000, 0x0331,
1324 0x0254, 0xff37, 0xfe60,
1325 0x0254, 0x0409, 0x0000,
1326 },
1327 {
1328 0xfff0, 0xff80, 0xff80,
1329 },
1330 {
1331 0, 0, 0,
1332 },
1333 {
1334 0, 0xff, 0, 0xff, 0, 0xff,
1335 },
1336 {
1337 0, 0xff, 0, 0xff, 0, 0xff,
1338 },
1339 },
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1340 {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1341 (0),
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1342 {
1343 0x0200, 0x0000, 0x0000,
1344 0x0000, 0x0200, 0x0000,
1345 0x0000, 0x0000, 0x0200,
1346 },
1347 {
1348 0x0, 0x0, 0x0,
1349 },
1350 {
1351 0, 0, 0,
1352 },
1353 {
1354 0, 0xff, 0, 0xff, 0, 0xff,
1355 },
1356 {
1357 0, 0xff, 0, 0xff, 0, 0xff,
1358 },
1359 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1360};
1361
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1362
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1363
1364#define MDP4_CSC_MV_OFF 0x4400
1365#define MDP4_CSC_PRE_BV_OFF 0x4500
1366#define MDP4_CSC_POST_BV_OFF 0x4580
1367#define MDP4_CSC_PRE_LV_OFF 0x4600
1368#define MDP4_CSC_POST_LV_OFF 0x4680
1369
1370void mdp4_vg_csc_mv_setup(int vp_num)
1371{
1372 uint32 *off;
1373 int i, voff;
1374
1375 voff = MDP4_VIDEO_OFF * vp_num;
1376 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1377 MDP4_CSC_MV_OFF);
1378
1379 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1380 for (i = 0; i < 9; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1381 outpdw(off, csc_matrix[vp_num].csc_mv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1382 off++;
1383 }
1384 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1385}
1386
1387void mdp4_vg_csc_pre_bv_setup(int vp_num)
1388{
1389 uint32 *off;
1390 int i, voff;
1391
1392 voff = MDP4_VIDEO_OFF * vp_num;
1393 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1394 MDP4_CSC_PRE_BV_OFF);
1395
1396 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1397 for (i = 0; i < 3; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1398 outpdw(off, csc_matrix[vp_num].csc_pre_bv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1399 off++;
1400 }
1401 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1402}
1403
1404void mdp4_vg_csc_post_bv_setup(int vp_num)
1405{
1406 uint32 *off;
1407 int i, voff;
1408
1409 voff = MDP4_VIDEO_OFF * vp_num;
1410 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1411 MDP4_CSC_POST_BV_OFF);
1412
1413 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1414 for (i = 0; i < 3; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1415 outpdw(off, csc_matrix[vp_num].csc_post_bv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1416 off++;
1417 }
1418 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1419}
1420
1421void mdp4_vg_csc_pre_lv_setup(int vp_num)
1422{
1423 uint32 *off;
1424 int i, voff;
1425
1426 voff = MDP4_VIDEO_OFF * vp_num;
1427 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1428 MDP4_CSC_PRE_LV_OFF);
1429
1430 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1431 for (i = 0; i < 6; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1432 outpdw(off, csc_matrix[vp_num].csc_pre_lv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1433 off++;
1434 }
1435 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1436}
1437
1438void mdp4_vg_csc_post_lv_setup(int vp_num)
1439{
1440 uint32 *off;
1441 int i, voff;
1442
1443 voff = MDP4_VIDEO_OFF * vp_num;
1444 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1445 MDP4_CSC_POST_LV_OFF);
1446
1447 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1448 for (i = 0; i < 6; i++) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1449 outpdw(off, csc_matrix[vp_num].csc_post_lv[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1450 off++;
1451 }
1452 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1453}
1454
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1455void mdp4_vg_csc_convert_setup(int vp_num)
1456{
1457 struct mdp_csc_cfg_data cfg;
1458
1459 switch (vp_num) {
1460 case 0:
1461 cfg.block = MDP_BLOCK_VG_1;
1462 break;
1463 case 1:
1464 cfg.block = MDP_BLOCK_VG_2;
1465 break;
1466 default:
1467 pr_err("%s - invalid vp_num = %d", __func__, vp_num);
1468 return;
1469 }
1470 cfg.csc_data = csc_matrix[vp_num];
1471 mdp4_csc_enable(&cfg);
1472}
1473
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1474void mdp4_vg_csc_setup(int vp_num)
1475{
1476 /* yuv2rgb */
1477 mdp4_vg_csc_mv_setup(vp_num);
1478 mdp4_vg_csc_pre_bv_setup(vp_num);
1479 mdp4_vg_csc_post_bv_setup(vp_num);
1480 mdp4_vg_csc_pre_lv_setup(vp_num);
1481 mdp4_vg_csc_post_lv_setup(vp_num);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1482 mdp4_vg_csc_convert_setup(vp_num);
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1483}
1484void mdp4_vg_csc_update(struct mdp_csc *p)
1485{
1486 struct mdp4_overlay_pipe *pipe;
1487 int vp_num;
1488
1489 pipe = mdp4_overlay_ndx2pipe(p->id);
1490 if (pipe == NULL) {
1491 pr_err("%s: p->id = %d Error\n", __func__, p->id);
1492 return;
1493 }
1494
1495 vp_num = pipe->pipe_num - OVERLAY_PIPE_VG1;
1496
1497 if (vp_num == 0 || vp_num == 1) {
1498 memcpy(csc_matrix[vp_num].csc_mv, p->csc_mv, sizeof(p->csc_mv));
1499 memcpy(csc_matrix[vp_num].csc_pre_bv, p->csc_pre_bv,
1500 sizeof(p->csc_pre_bv));
1501 memcpy(csc_matrix[vp_num].csc_post_bv, p->csc_post_bv,
1502 sizeof(p->csc_post_bv));
1503 memcpy(csc_matrix[vp_num].csc_pre_lv, p->csc_pre_lv,
1504 sizeof(p->csc_pre_lv));
1505 memcpy(csc_matrix[vp_num].csc_post_lv, p->csc_post_lv,
1506 sizeof(p->csc_post_lv));
1507 mdp4_vg_csc_setup(vp_num);
1508 }
1509}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1510static uint32 csc_rgb2yuv_matrix_tab[9] = {
1511 0x0083, 0x0102, 0x0032,
1512 0x1fb5, 0x1f6c, 0x00e1,
1513 0x00e1, 0x1f45, 0x1fdc
1514};
1515
1516static uint32 csc_rgb2yuv_pre_bv_tab[3] = {0, 0, 0};
1517
1518static uint32 csc_rgb2yuv_post_bv_tab[3] = {0x0010, 0x0080, 0x0080};
1519
1520static uint32 csc_rgb2yuv_pre_lv_tab[6] = {
1521 0x00, 0xff, 0x00,
1522 0xff, 0x00, 0xff
1523};
1524
1525static uint32 csc_rgb2yuv_post_lv_tab[6] = {
1526 0x0010, 0x00eb, 0x0010,
1527 0x00f0, 0x0010, 0x00f0
1528};
1529
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1530void mdp4_mixer_csc_mv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1531{
1532 uint32 *off;
1533 int i;
1534
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1535 if (mixer == MDP4_MIXER1)
1536 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2400);
1537 else
1538 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2400);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1539
1540 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1541 for (i = 0; i < 9; i++) {
1542 outpdw(off, csc_rgb2yuv_matrix_tab[i]);
1543 off++;
1544 }
1545 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1546}
1547
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1548void mdp4_mixer_csc_pre_bv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1549{
1550 uint32 *off;
1551 int i;
1552
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1553 if (mixer == MDP4_MIXER1)
1554 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2500);
1555 else
1556 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2500);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1557
1558 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1559 for (i = 0; i < 3; i++) {
1560 outpdw(off, csc_rgb2yuv_pre_bv_tab[i]);
1561 off++;
1562 }
1563 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1564}
1565
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1566void mdp4_mixer_csc_post_bv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1567{
1568 uint32 *off;
1569 int i;
1570
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1571 if (mixer == MDP4_MIXER1)
1572 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2580);
1573 else
1574 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2580);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1575
1576 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1577 for (i = 0; i < 3; i++) {
1578 outpdw(off, csc_rgb2yuv_post_bv_tab[i]);
1579 off++;
1580 }
1581 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1582}
1583
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1584void mdp4_mixer_csc_pre_lv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1585{
1586 uint32 *off;
1587 int i;
1588
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1589 if (mixer == MDP4_MIXER1)
1590 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2600);
1591 else
1592 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2600);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1593
1594 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1595 for (i = 0; i < 6; i++) {
1596 outpdw(off, csc_rgb2yuv_pre_lv_tab[i]);
1597 off++;
1598 }
1599 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1600}
1601
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1602void mdp4_mixer_csc_post_lv_setup(uint32 mixer)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1603{
1604 uint32 *off;
1605 int i;
1606
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1607 if (mixer == MDP4_MIXER1)
1608 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x2680);
1609 else
1610 off = (uint32 *)(MDP_BASE + MDP4_OVERLAYPROC2_BASE + 0x2680);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1611
1612 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1613 for (i = 0; i < 6; i++) {
1614 outpdw(off, csc_rgb2yuv_post_lv_tab[i]);
1615 off++;
1616 }
1617 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1618}
1619
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1620void mdp4_mixer_csc_setup(uint32 mixer)
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1621{
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1622 if (mixer >= MDP4_MIXER1) {
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1623 /* rgb2yuv */
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1624 mdp4_mixer_csc_mv_setup(mixer);
1625 mdp4_mixer_csc_pre_bv_setup(mixer);
1626 mdp4_mixer_csc_post_bv_setup(mixer);
1627 mdp4_mixer_csc_pre_lv_setup(mixer);
1628 mdp4_mixer_csc_post_lv_setup(mixer);
1629 }
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1630}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1631
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1632#define DMA_P_BASE 0x90000
1633void mdp4_dmap_csc_mv_setup(void)
1634{
1635 uint32 *off;
1636 int i;
1637
1638 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3400);
1639
1640 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1641 for (i = 0; i < 9; i++) {
1642 outpdw(off, csc_matrix[2].csc_mv[i]);
1643 off++;
1644 }
1645 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1646}
1647
1648void mdp4_dmap_csc_pre_bv_setup(void)
1649{
1650 uint32 *off;
1651 int i;
1652
1653 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3500);
1654
1655 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1656 for (i = 0; i < 3; i++) {
1657 outpdw(off, csc_matrix[2].csc_pre_bv[i]);
1658 off++;
1659 }
1660 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1661}
1662
1663void mdp4_dmap_csc_post_bv_setup(void)
1664{
1665 uint32 *off;
1666 int i;
1667
1668 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3580);
1669
1670 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1671 for (i = 0; i < 3; i++) {
1672 outpdw(off, csc_matrix[2].csc_post_bv[i]);
1673 off++;
1674 }
1675 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1676}
1677
1678void mdp4_dmap_csc_pre_lv_setup(void)
1679{
1680 uint32 *off;
1681 int i;
1682
1683 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3600);
1684
1685 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1686 for (i = 0; i < 6; i++) {
1687 outpdw(off, csc_matrix[2].csc_pre_lv[i]);
1688 off++;
1689 }
1690 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1691}
1692
1693void mdp4_dmap_csc_post_lv_setup(void)
1694{
1695 uint32 *off;
1696 int i;
1697
1698 off = (uint32 *)(MDP_BASE + DMA_P_BASE + 0x3680);
1699
1700 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1701 for (i = 0; i < 6; i++) {
1702 outpdw(off, csc_matrix[2].csc_post_lv[i]);
1703 off++;
1704 }
1705 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1706}
1707
1708void mdp4_dmap_csc_setup(void)
1709{
1710 mdp4_dmap_csc_mv_setup();
1711 mdp4_dmap_csc_pre_bv_setup();
1712 mdp4_dmap_csc_post_bv_setup();
1713 mdp4_dmap_csc_pre_lv_setup();
1714 mdp4_dmap_csc_post_lv_setup();
1715}
1716
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1717char gc_lut[] = {
1718 0x0, 0x1, 0x2, 0x2, 0x3, 0x4, 0x5, 0x6,
1719 0x6, 0x7, 0x8, 0x9, 0xA, 0xA, 0xB, 0xC,
1720 0xD, 0xD, 0xE, 0xF, 0xF, 0x10, 0x10, 0x11,
1721 0x12, 0x12, 0x13, 0x13, 0x14, 0x14, 0x15, 0x15,
1722 0x16, 0x16, 0x17, 0x17, 0x17, 0x18, 0x18, 0x19,
1723 0x19, 0x19, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1C,
1724 0x1C, 0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F,
1725 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21,
1726 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24,
1727 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x26, 0x26,
1728 0x26, 0x26, 0x27, 0x27, 0x27, 0x28, 0x28, 0x28,
1729 0x28, 0x29, 0x29, 0x29, 0x29, 0x2A, 0x2A, 0x2A,
1730 0x2A, 0x2B, 0x2B, 0x2B, 0x2B, 0x2B, 0x2C, 0x2C,
1731 0x2C, 0x2C, 0x2D, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E,
1732 0x2E, 0x2E, 0x2E, 0x2F, 0x2F, 0x2F, 0x2F, 0x30,
1733 0x30, 0x30, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31,
1734 0x31, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33,
1735 0x33, 0x33, 0x33, 0x34, 0x34, 0x34, 0x34, 0x34,
1736 0x35, 0x35, 0x35, 0x35, 0x35, 0x36, 0x36, 0x36,
1737 0x36, 0x36, 0x37, 0x37, 0x37, 0x37, 0x37, 0x37,
1738 0x38, 0x38, 0x38, 0x38, 0x38, 0x39, 0x39, 0x39,
1739 0x39, 0x39, 0x39, 0x3A, 0x3A, 0x3A, 0x3A, 0x3A,
1740 0x3A, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3C,
1741 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D,
1742 0x3D, 0x3D, 0x3D, 0x3E, 0x3E, 0x3E, 0x3E, 0x3E,
1743 0x3E, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x40,
1744 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41,
1745 0x41, 0x41, 0x41, 0x41, 0x42, 0x42, 0x42, 0x42,
1746 0x42, 0x42, 0x42, 0x43, 0x43, 0x43, 0x43, 0x43,
1747 0x43, 0x43, 0x44, 0x44, 0x44, 0x44, 0x44, 0x44,
1748 0x44, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45,
1749 0x46, 0x46, 0x46, 0x46, 0x46, 0x46, 0x46, 0x47,
1750 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x48, 0x48,
1751 0x48, 0x48, 0x48, 0x48, 0x48, 0x48, 0x49, 0x49,
1752 0x49, 0x49, 0x49, 0x49, 0x49, 0x4A, 0x4A, 0x4A,
1753 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4B, 0x4B, 0x4B,
1754 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4C, 0x4C, 0x4C,
1755 0x4C, 0x4C, 0x4C, 0x4C, 0x4D, 0x4D, 0x4D, 0x4D,
1756 0x4D, 0x4D, 0x4D, 0x4D, 0x4E, 0x4E, 0x4E, 0x4E,
1757 0x4E, 0x4E, 0x4E, 0x4E, 0x4E, 0x4F, 0x4F, 0x4F,
1758 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x50, 0x50, 0x50,
1759 0x50, 0x50, 0x50, 0x50, 0x50, 0x51, 0x51, 0x51,
1760 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52,
1761 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x53, 0x53,
1762 0x53, 0x53, 0x53, 0x53, 0x53, 0x53, 0x53, 0x54,
1763 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54,
1764 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
1765 0x55, 0x56, 0x56, 0x56, 0x56, 0x56, 0x56, 0x56,
1766 0x56, 0x56, 0x57, 0x57, 0x57, 0x57, 0x57, 0x57,
1767 0x57, 0x57, 0x57, 0x58, 0x58, 0x58, 0x58, 0x58,
1768 0x58, 0x58, 0x58, 0x58, 0x58, 0x59, 0x59, 0x59,
1769 0x59, 0x59, 0x59, 0x59, 0x59, 0x59, 0x5A, 0x5A,
1770 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A, 0x5A,
1771 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B, 0x5B,
1772 0x5B, 0x5B, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C,
1773 0x5C, 0x5C, 0x5C, 0x5C, 0x5D, 0x5D, 0x5D, 0x5D,
1774 0x5D, 0x5D, 0x5D, 0x5D, 0x5D, 0x5D, 0x5E, 0x5E,
1775 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E,
1776 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F,
1777 0x5F, 0x5F, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60,
1778 0x60, 0x60, 0x60, 0x60, 0x60, 0x61, 0x61, 0x61,
1779 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x62,
1780 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62,
1781 0x62, 0x62, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
1782 0x63, 0x63, 0x63, 0x63, 0x63, 0x64, 0x64, 0x64,
1783 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64,
1784 0x65, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65, 0x65,
1785 0x65, 0x65, 0x65, 0x66, 0x66, 0x66, 0x66, 0x66,
1786 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x67, 0x67,
1787 0x67, 0x67, 0x67, 0x67, 0x67, 0x67, 0x67, 0x67,
1788 0x67, 0x67, 0x68, 0x68, 0x68, 0x68, 0x68, 0x68,
1789 0x68, 0x68, 0x68, 0x68, 0x68, 0x69, 0x69, 0x69,
1790 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69,
1791 0x69, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6A,
1792 0x6A, 0x6A, 0x6A, 0x6A, 0x6A, 0x6B, 0x6B, 0x6B,
1793 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B, 0x6B,
1794 0x6B, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C,
1795 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6D, 0x6D, 0x6D,
1796 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D,
1797 0x6D, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6E,
1798 0x6E, 0x6E, 0x6E, 0x6E, 0x6E, 0x6F, 0x6F, 0x6F,
1799 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F, 0x6F,
1800 0x6F, 0x6F, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
1801 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x71, 0x71,
1802 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71, 0x71,
1803 0x71, 0x71, 0x71, 0x72, 0x72, 0x72, 0x72, 0x72,
1804 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72, 0x72,
1805 0x73, 0x73, 0x73, 0x73, 0x73, 0x73, 0x73, 0x73,
1806 0x73, 0x73, 0x73, 0x73, 0x73, 0x74, 0x74, 0x74,
1807 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74,
1808 0x74, 0x74, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
1809 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
1810 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76,
1811 0x76, 0x76, 0x76, 0x76, 0x76, 0x77, 0x77, 0x77,
1812 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,
1813 0x77, 0x77, 0x77, 0x78, 0x78, 0x78, 0x78, 0x78,
1814 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
1815 0x78, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x79,
1816 0x79, 0x79, 0x79, 0x79, 0x79, 0x79, 0x7A, 0x7A,
1817 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7A,
1818 0x7A, 0x7A, 0x7A, 0x7A, 0x7A, 0x7B, 0x7B, 0x7B,
1819 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B, 0x7B,
1820 0x7B, 0x7B, 0x7B, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C,
1821 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C,
1822 0x7C, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D,
1823 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D, 0x7D,
1824 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E,
1825 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7E, 0x7F, 0x7F,
1826 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F,
1827 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x80, 0x80, 0x80,
1828 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
1829 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81,
1830 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
1831 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x82, 0x82,
1832 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82,
1833 0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83,
1834 0x83, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83, 0x83,
1835 0x83, 0x83, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84,
1836 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84,
1837 0x84, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
1838 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85,
1839 0x85, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86,
1840 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86,
1841 0x86, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87,
1842 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87,
1843 0x87, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1844 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
1845 0x88, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89,
1846 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89, 0x89,
1847 0x89, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
1848 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A, 0x8A,
1849 0x8A, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B,
1850 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B, 0x8B,
1851 0x8B, 0x8B, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C,
1852 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C, 0x8C,
1853 0x8C, 0x8C, 0x8C, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D,
1854 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D,
1855 0x8D, 0x8D, 0x8D, 0x8D, 0x8E, 0x8E, 0x8E, 0x8E,
1856 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8E,
1857 0x8E, 0x8E, 0x8E, 0x8E, 0x8E, 0x8F, 0x8F, 0x8F,
1858 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F,
1859 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x8F, 0x90, 0x90,
1860 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90,
1861 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x91,
1862 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91,
1863 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91,
1864 0x91, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92,
1865 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92,
1866 0x92, 0x92, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93,
1867 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93,
1868 0x93, 0x93, 0x93, 0x93, 0x94, 0x94, 0x94, 0x94,
1869 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94,
1870 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, 0x95, 0x95,
1871 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
1872 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
1873 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96,
1874 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96, 0x96,
1875 0x96, 0x96, 0x96, 0x97, 0x97, 0x97, 0x97, 0x97,
1876 0x97, 0x97, 0x97, 0x97, 0x97, 0x97, 0x97, 0x97,
1877 0x97, 0x97, 0x97, 0x97, 0x97, 0x98, 0x98, 0x98,
1878 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
1879 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
1880 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99,
1881 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99,
1882 0x99, 0x99, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A,
1883 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A,
1884 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9B, 0x9B, 0x9B,
1885 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B,
1886 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B, 0x9B,
1887 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C,
1888 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C, 0x9C,
1889 0x9C, 0x9C, 0x9C, 0x9C, 0x9D, 0x9D, 0x9D, 0x9D,
1890 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D,
1891 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9E,
1892 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E,
1893 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E, 0x9E,
1894 0x9E, 0x9E, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1895 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1896 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0xA0, 0xA0,
1897 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1898 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1899 0xA0, 0xA0, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1900 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1901 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA2, 0xA2,
1902 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1903 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1904 0xA2, 0xA2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1905 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1906 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA4, 0xA4,
1907 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1908 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1909 0xA4, 0xA4, 0xA4, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1910 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1911 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1912 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1913 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1914 0xA6, 0xA6, 0xA6, 0xA6, 0xA7, 0xA7, 0xA7, 0xA7,
1915 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1916 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1917 0xA7, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1918 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1919 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA9,
1920 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
1921 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
1922 0xA9, 0xA9, 0xA9, 0xA9, 0xAA, 0xAA, 0xAA, 0xAA,
1923 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1924 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1925 0xAA, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB,
1926 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB,
1927 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAB, 0xAC,
1928 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC,
1929 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAC,
1930 0xAC, 0xAC, 0xAC, 0xAC, 0xAC, 0xAD, 0xAD, 0xAD,
1931 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD,
1932 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD, 0xAD,
1933 0xAD, 0xAD, 0xAD, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1934 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1935 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE,
1936 0xAE, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF,
1937 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF,
1938 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xB0,
1939 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1940 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1941 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB1, 0xB1,
1942 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1943 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1944 0xB1, 0xB1, 0xB1, 0xB1, 0xB2, 0xB2, 0xB2, 0xB2,
1945 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1946 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1947 0xB2, 0xB2, 0xB2, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1948 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1949 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1950 0xB3, 0xB3, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1951 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1952 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1953 0xB4, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1954 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1955 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1956 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1957 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1958 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1959 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1960 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1961 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB8,
1962 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1963 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1964 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB9,
1965 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1966 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1967 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xBA,
1968 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1969 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1970 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBB,
1971 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1972 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1973 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1974 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1975 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1976 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1977 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1978 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1979 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1980 0xBD, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1981 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1982 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1983 0xBE, 0xBE, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1984 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1985 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1986 0xBF, 0xBF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1987 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1988 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1989 0xC0, 0xC0, 0xC0, 0xC0, 0xC1, 0xC1, 0xC1, 0xC1,
1990 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1991 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1992 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC2, 0xC2, 0xC2,
1993 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1994 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1995 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC3, 0xC3,
1996 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1997 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1998 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1999 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
2000 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
2001 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
2002 0xC4, 0xC4, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
2003 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
2004 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
2005 0xC5, 0xC5, 0xC5, 0xC5, 0xC6, 0xC6, 0xC6, 0xC6,
2006 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
2007 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
2008 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC7, 0xC7,
2009 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
2010 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
2011 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
2012 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
2013 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
2014 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
2015 0xC8, 0xC8, 0xC8, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
2016 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
2017 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
2018 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xCA, 0xCA,
2019 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2020 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2021 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
2022 0xCA, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2023 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2024 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
2025 0xCB, 0xCB, 0xCB, 0xCB, 0xCC, 0xCC, 0xCC, 0xCC,
2026 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
2027 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
2028 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCD,
2029 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2030 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2031 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
2032 0xCD, 0xCD, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2033 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2034 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
2035 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCF, 0xCF,
2036 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2037 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2038 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
2039 0xCF, 0xCF, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2040 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2041 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
2042 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD1, 0xD1, 0xD1,
2043 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2044 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2045 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
2046 0xD1, 0xD1, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2047 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2048 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
2049 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD3, 0xD3,
2050 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2051 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2052 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
2053 0xD3, 0xD3, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2054 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2055 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
2056 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD5,
2057 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2058 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2059 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
2060 0xD5, 0xD5, 0xD5, 0xD5, 0xD6, 0xD6, 0xD6, 0xD6,
2061 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2062 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2063 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
2064 0xD6, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2065 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2066 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
2067 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD8, 0xD8,
2068 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2069 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2070 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
2071 0xD8, 0xD8, 0xD8, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2072 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2073 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2074 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
2075 0xD9, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2076 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2077 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
2078 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDB, 0xDB,
2079 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2080 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2081 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
2082 0xDB, 0xDB, 0xDB, 0xDB, 0xDC, 0xDC, 0xDC, 0xDC,
2083 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2084 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2085 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
2086 0xDC, 0xDC, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2087 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2088 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2089 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
2090 0xDD, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2091 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2092 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
2093 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDF,
2094 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2095 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2096 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
2097 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xE0, 0xE0,
2098 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2099 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2100 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
2101 0xE0, 0xE0, 0xE0, 0xE0, 0xE1, 0xE1, 0xE1, 0xE1,
2102 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2103 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2104 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
2105 0xE1, 0xE1, 0xE1, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2106 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2107 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2108 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
2109 0xE2, 0xE2, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2110 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2111 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2112 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
2113 0xE3, 0xE3, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2114 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2115 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2116 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
2117 0xE4, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2118 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2119 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2120 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
2121 0xE5, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2122 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2123 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2124 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
2125 0xE6, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2126 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2127 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2128 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
2129 0xE7, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2130 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2131 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2132 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
2133 0xE8, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2134 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2135 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2136 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
2137 0xE9, 0xE9, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2138 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2139 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2140 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
2141 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2142 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2143 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2144 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
2145 0xEB, 0xEB, 0xEB, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2146 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2147 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2148 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
2149 0xEC, 0xEC, 0xEC, 0xEC, 0xED, 0xED, 0xED, 0xED,
2150 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2151 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2152 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
2153 0xED, 0xED, 0xED, 0xED, 0xED, 0xEE, 0xEE, 0xEE,
2154 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2155 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2156 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
2157 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEF, 0xEF,
2158 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2159 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2160 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2161 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
2162 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2163 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2164 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2165 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
2166 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2167 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2168 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2169 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
2170 0xF1, 0xF1, 0xF1, 0xF1, 0xF2, 0xF2, 0xF2, 0xF2,
2171 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2172 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2173 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
2174 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF3, 0xF3,
2175 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2176 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2177 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2178 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
2179 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2180 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2181 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2182 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
2183 0xF4, 0xF4, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2184 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2185 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2186 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
2187 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF6, 0xF6, 0xF6,
2188 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2189 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2190 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2191 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
2192 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2193 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2194 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2195 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
2196 0xF7, 0xF7, 0xF7, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2197 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2198 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2199 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
2200 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF9, 0xF9,
2201 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2202 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2203 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2204 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
2205 0xF9, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2206 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2207 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2208 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
2209 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB,
2210 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2211 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2212 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2213 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
2214 0xFB, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2215 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2216 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2217 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
2218 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFD, 0xFD, 0xFD,
2219 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2220 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2221 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2222 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
2223 0xFD, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2224 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2225 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2226 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
2227 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF,
2228 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2229 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2230};
2231
2232void mdp4_mixer_gc_lut_setup(int mixer_num)
2233{
2234 unsigned char *base;
2235 uint32 data;
2236 char val;
2237 int i, off;
2238
2239 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
2240 base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
2241 else
2242 base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
2243
2244 base += 0x4000; /* GC_LUT offset */
2245
2246 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2247 off = 0;
2248 for (i = 0; i < 4096; i++) {
2249 val = gc_lut[i];
2250 data = (val << 16 | val << 8 | val); /* R, B, and G are same */
2251 outpdw(base + off, data);
2252 off += 4;
2253 }
2254 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2255}
2256
2257uint32 igc_video_lut[] = { /* non linear */
2258 0x0, 0x1, 0x2, 0x4, 0x5, 0x6, 0x7, 0x9,
2259 0xA, 0xB, 0xC, 0xE, 0xF, 0x10, 0x12, 0x14,
2260 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F, 0x21, 0x23,
2261 0x25, 0x28, 0x2A, 0x2D, 0x30, 0x32, 0x35, 0x38,
2262 0x3B, 0x3E, 0x42, 0x45, 0x48, 0x4C, 0x4F, 0x53,
2263 0x57, 0x5B, 0x5F, 0x63, 0x67, 0x6B, 0x70, 0x74,
2264 0x79, 0x7E, 0x83, 0x88, 0x8D, 0x92, 0x97, 0x9C,
2265 0xA2, 0xA8, 0xAD, 0xB3, 0xB9, 0xBF, 0xC5, 0xCC,
2266 0xD2, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, 0xFB, 0x102,
2267 0x109, 0x111, 0x118, 0x120, 0x128, 0x130, 0x138, 0x140,
2268 0x149, 0x151, 0x15A, 0x162, 0x16B, 0x174, 0x17D, 0x186,
2269 0x190, 0x199, 0x1A3, 0x1AC, 0x1B6, 0x1C0, 0x1CA, 0x1D5,
2270 0x1DF, 0x1EA, 0x1F4, 0x1FF, 0x20A, 0x215, 0x220, 0x22B,
2271 0x237, 0x242, 0x24E, 0x25A, 0x266, 0x272, 0x27F, 0x28B,
2272 0x298, 0x2A4, 0x2B1, 0x2BE, 0x2CB, 0x2D8, 0x2E6, 0x2F3,
2273 0x301, 0x30F, 0x31D, 0x32B, 0x339, 0x348, 0x356, 0x365,
2274 0x374, 0x383, 0x392, 0x3A1, 0x3B1, 0x3C0, 0x3D0, 0x3E0,
2275 0x3F0, 0x400, 0x411, 0x421, 0x432, 0x443, 0x454, 0x465,
2276 0x476, 0x487, 0x499, 0x4AB, 0x4BD, 0x4CF, 0x4E1, 0x4F3,
2277 0x506, 0x518, 0x52B, 0x53E, 0x551, 0x565, 0x578, 0x58C,
2278 0x5A0, 0x5B3, 0x5C8, 0x5DC, 0x5F0, 0x605, 0x61A, 0x62E,
2279 0x643, 0x659, 0x66E, 0x684, 0x699, 0x6AF, 0x6C5, 0x6DB,
2280 0x6F2, 0x708, 0x71F, 0x736, 0x74D, 0x764, 0x77C, 0x793,
2281 0x7AB, 0x7C3, 0x7DB, 0x7F3, 0x80B, 0x824, 0x83D, 0x855,
2282 0x86F, 0x888, 0x8A1, 0x8BB, 0x8D4, 0x8EE, 0x908, 0x923,
2283 0x93D, 0x958, 0x973, 0x98E, 0x9A9, 0x9C4, 0x9DF, 0x9FB,
2284 0xA17, 0xA33, 0xA4F, 0xA6C, 0xA88, 0xAA5, 0xAC2, 0xADF,
2285 0xAFC, 0xB19, 0xB37, 0xB55, 0xB73, 0xB91, 0xBAF, 0xBCE,
2286 0xBEC, 0xC0B, 0xC2A, 0xC4A, 0xC69, 0xC89, 0xCA8, 0xCC8,
2287 0xCE8, 0xD09, 0xD29, 0xD4A, 0xD6B, 0xD8C, 0xDAD, 0xDCF,
2288 0xDF0, 0xE12, 0xE34, 0xE56, 0xE79, 0xE9B, 0xEBE, 0xEE1,
2289 0xF04, 0xF27, 0xF4B, 0xF6E, 0xF92, 0xFB6, 0xFDB, 0xFFF,
2290};
2291
2292void mdp4_vg_igc_lut_setup(int vp_num)
2293{
2294 unsigned char *base;
2295 int i, voff, off;
2296 uint32 data, val;
2297
2298 voff = MDP4_VIDEO_OFF * vp_num;
2299 base = MDP_BASE + MDP4_VIDEO_BASE + voff + 0x5000;
2300
2301 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2302 off = 0;
2303 for (i = 0; i < 256; i++) {
2304 val = igc_video_lut[i];
2305 data = (val << 16 | val); /* color 0 and 1 */
2306 outpdw(base + off, data);
2307 outpdw(base + off + 0x800, val); /* color 2 */
2308 off += 4;
2309 }
2310 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2311}
2312
2313uint32 igc_rgb_lut[] = { /* linear */
2314 0x0, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
2315 0x80, 0x91, 0xA1, 0xB1, 0xC1, 0xD1, 0xE1, 0xF1,
2316 0x101, 0x111, 0x121, 0x131, 0x141, 0x151, 0x161, 0x171,
2317 0x181, 0x191, 0x1A2, 0x1B2, 0x1C2, 0x1D2, 0x1E2, 0x1F2,
2318 0x202, 0x212, 0x222, 0x232, 0x242, 0x252, 0x262, 0x272,
2319 0x282, 0x292, 0x2A2, 0x2B3, 0x2C3, 0x2D3, 0x2E3, 0x2F3,
2320 0x303, 0x313, 0x323, 0x333, 0x343, 0x353, 0x363, 0x373,
2321 0x383, 0x393, 0x3A3, 0x3B3, 0x3C4, 0x3D4, 0x3E4, 0x3F4,
2322 0x404, 0x414, 0x424, 0x434, 0x444, 0x454, 0x464, 0x474,
2323 0x484, 0x494, 0x4A4, 0x4B4, 0x4C4, 0x4D5, 0x4E5, 0x4F5,
2324 0x505, 0x515, 0x525, 0x535, 0x545, 0x555, 0x565, 0x575,
2325 0x585, 0x595, 0x5A5, 0x5B5, 0x5C5, 0x5D5, 0x5E6, 0x5F6,
2326 0x606, 0x616, 0x626, 0x636, 0x646, 0x656, 0x666, 0x676,
2327 0x686, 0x696, 0x6A6, 0x6B6, 0x6C6, 0x6D6, 0x6E6, 0x6F7,
2328 0x707, 0x717, 0x727, 0x737, 0x747, 0x757, 0x767, 0x777,
2329 0x787, 0x797, 0x7A7, 0x7B7, 0x7C7, 0x7D7, 0x7E7, 0x7F7,
2330 0x808, 0x818, 0x828, 0x838, 0x848, 0x858, 0x868, 0x878,
2331 0x888, 0x898, 0x8A8, 0x8B8, 0x8C8, 0x8D8, 0x8E8, 0x8F8,
2332 0x908, 0x919, 0x929, 0x939, 0x949, 0x959, 0x969, 0x979,
2333 0x989, 0x999, 0x9A9, 0x9B9, 0x9C9, 0x9D9, 0x9E9, 0x9F9,
2334 0xA09, 0xA19, 0xA2A, 0xA3A, 0xA4A, 0xA5A, 0xA6A, 0xA7A,
2335 0xA8A, 0xA9A, 0xAAA, 0xABA, 0xACA, 0xADA, 0xAEA, 0xAFA,
2336 0xB0A, 0xB1A, 0xB2A, 0xB3B, 0xB4B, 0xB5B, 0xB6B, 0xB7B,
2337 0xB8B, 0xB9B, 0xBAB, 0xBBB, 0xBCB, 0xBDB, 0xBEB, 0xBFB,
2338 0xC0B, 0xC1B, 0xC2B, 0xC3B, 0xC4C, 0xC5C, 0xC6C, 0xC7C,
2339 0xC8C, 0xC9C, 0xCAC, 0xCBC, 0xCCC, 0xCDC, 0xCEC, 0xCFC,
2340 0xD0C, 0xD1C, 0xD2C, 0xD3C, 0xD4C, 0xD5D, 0xD6D, 0xD7D,
2341 0xD8D, 0xD9D, 0xDAD, 0xDBD, 0xDCD, 0xDDD, 0xDED, 0xDFD,
2342 0xE0D, 0xE1D, 0xE2D, 0xE3D, 0xE4D, 0xE5D, 0xE6E, 0xE7E,
2343 0xE8E, 0xE9E, 0xEAE, 0xEBE, 0xECE, 0xEDE, 0xEEE, 0xEFE,
2344 0xF0E, 0xF1E, 0xF2E, 0xF3E, 0xF4E, 0xF5E, 0xF6E, 0xF7F,
2345 0xF8F, 0xF9F, 0xFAF, 0xFBF, 0xFCF, 0xFDF, 0xFEF, 0xFFF,
2346};
2347
2348void mdp4_rgb_igc_lut_setup(int num)
2349{
2350 unsigned char *base;
2351 int i, voff, off;
2352 uint32 data, val;
2353
2354 voff = MDP4_RGB_OFF * num;
2355 base = MDP_BASE + MDP4_RGB_BASE + voff + 0x5000;
2356
2357 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2358 off = 0;
2359 for (i = 0; i < 256; i++) {
2360 val = igc_rgb_lut[i];
2361 data = (val << 16 | val); /* color 0 and 1 */
2362 outpdw(base + off, data);
2363 outpdw(base + off + 0x800, val); /* color 2 */
2364 off += 4;
2365 }
2366 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2367}
2368
2369uint32 mdp4_rgb_igc_lut_cvt(uint32 ndx)
2370{
2371 return igc_rgb_lut[ndx & 0x0ff];
2372}
2373
2374uint32_t mdp4_ss_table_value(int8_t value, int8_t index)
2375{
2376 uint32_t out = 0x0;
2377 int8_t level = -1;
2378 uint32_t mask = 0xffffffff;
2379
2380 if (value < 0) {
2381 if (value == -128)
2382 value = 127;
2383 else
2384 value = -value;
2385 out = 0x11111111;
2386 } else {
2387 out = 0x88888888;
2388 mask = 0x0fffffff;
2389 }
2390
2391 if (value == 0)
2392 level = 0;
2393 else {
2394 while (value > 0 && level < 7) {
2395 level++;
2396 value -= 16;
2397 }
2398 }
2399
2400 if (level == 0) {
2401 if (index == 0)
2402 out = 0x0;
2403 else
2404 out = 0x20000000;
2405 } else {
2406 out += (0x11111111 * level);
2407 if (index == 1)
2408 out &= mask;
2409 }
2410
2411 return out;
2412}
2413
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2414static uint32_t mdp4_csc_block2base(uint32_t block)
2415{
2416 uint32_t base = 0x0;
2417 switch (block) {
2418 case MDP_BLOCK_OVERLAY_1:
2419 base = 0x1A000;
2420 break;
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2421 case MDP_BLOCK_OVERLAY_2:
2422 base = (mdp_rev >= MDP_REV_44) ? 0x8A000 : 0x0;
2423 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2424 case MDP_BLOCK_VG_1:
2425 base = 0x24000;
2426 break;
2427 case MDP_BLOCK_VG_2:
2428 base = 0x34000;
2429 break;
2430 case MDP_BLOCK_DMA_P:
2431 base = 0x93000;
2432 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2433 case MDP_BLOCK_DMA_S:
2434 base = (mdp_rev >= MDP_REV_42) ? 0xA3000 : 0x0;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2435 default:
2436 break;
2437 }
2438 return base;
2439}
2440
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2441int mdp4_csc_enable(struct mdp_csc_cfg_data *config)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2442{
2443 uint32_t output, base, temp, mask;
2444
2445 switch (config->block) {
2446 case MDP_BLOCK_DMA_P:
2447 base = 0x90070;
2448 output = (config->csc_data.flags << 3) & (0x08);
2449 temp = (config->csc_data.flags << 10) & (0x1800);
2450 output |= temp;
2451 mask = 0x08 | 0x1800;
2452 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2453 case MDP_BLOCK_DMA_S:
2454 base = 0xA0028;
2455 output = (config->csc_data.flags << 3) & (0x08);
2456 temp = (config->csc_data.flags << 10) & (0x1800);
2457 output |= temp;
2458 mask = 0x08 | 0x1800;
2459 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2460 case MDP_BLOCK_VG_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2461 base = 0x20058;
2462 output = (config->csc_data.flags << 11) & (0x800);
2463 temp = (config->csc_data.flags << 8) & (0x600);
2464 output |= temp;
2465 mask = 0x800 | 0x600;
2466 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2467 case MDP_BLOCK_VG_2:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2468 base = 0x30058;
2469 output = (config->csc_data.flags << 11) & (0x800);
2470 temp = (config->csc_data.flags << 8) & (0x600);
2471 output |= temp;
2472 mask = 0x800 | 0x600;
2473 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2474 case MDP_BLOCK_OVERLAY_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2475 base = 0x18200;
2476 output = config->csc_data.flags;
2477 mask = 0x07;
2478 break;
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2479 case MDP_BLOCK_OVERLAY_2:
2480 base = 0x88200;
2481 output = config->csc_data.flags;
2482 mask = 0x07;
2483 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2484 default:
2485 pr_err("%s - CSC block does not exist on MDP_BLOCK = %d\n",
2486 __func__, config->block);
2487 return -EINVAL;
2488 }
2489
2490 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2491 temp = inpdw(MDP_BASE + base) & ~mask;
2492 output |= temp;
2493 outpdw(MDP_BASE + base, output);
2494 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2495 return 0;
2496}
2497
2498#define CSC_MV_OFF 0x400
2499#define CSC_BV_OFF 0x500
2500#define CSC_LV_OFF 0x600
2501#define CSC_POST_OFF 0x80
2502
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2503void mdp4_csc_write(struct mdp_csc_cfg *data, uint32_t base)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2504{
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2505 int i;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2506 uint32_t *off;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2507
2508 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2509 off = (uint32_t *) ((uint32_t) base + CSC_MV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2510 for (i = 0; i < 9; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2511 outpdw(off, data->csc_mv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2512 off++;
2513 }
2514
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2515 off = (uint32_t *) ((uint32_t) base + CSC_BV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2516 for (i = 0; i < 3; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2517 outpdw(off, data->csc_pre_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2518 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2519 data->csc_post_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2520 off++;
2521 }
2522
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2523 off = (uint32_t *) ((uint32_t) base + CSC_LV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2524 for (i = 0; i < 6; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2525 outpdw(off, data->csc_pre_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2526 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2527 data->csc_post_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2528 off++;
2529 }
2530 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2531}
2532
2533int mdp4_csc_config(struct mdp_csc_cfg_data *config)
2534{
2535 int ret = 0;
2536 uint32_t base;
2537
2538 base = mdp4_csc_block2base(config->block);
2539 if (!base) {
2540 pr_warn("%s: Block type %d isn't supported by CSC.\n",
2541 __func__, config->block);
2542 return -EINVAL;
2543 }
2544
2545 mdp4_csc_write(&config->csc_data, (uint32_t) (MDP_BASE + base));
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2546
2547 ret = mdp4_csc_enable(config);
2548
2549 return ret;
2550}
2551
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2552void mdp4_init_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2553{
2554 struct mdp_buf_type *buf;
2555
2556 if (mix_num == MDP4_MIXER0)
2557 buf = mfd->ov0_wb_buf;
2558 else
2559 buf = mfd->ov1_wb_buf;
2560
2561 buf->ihdl = NULL;
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2562 buf->write_addr = 0;
2563 buf->read_addr = 0;
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2564}
2565
2566u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2567{
2568 struct mdp_buf_type *buf;
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2569 ion_phys_addr_t addr, read_addr = 0;
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2570 size_t buffer_size;
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]2571 unsigned long len;
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2572
2573 if (mix_num == MDP4_MIXER0)
2574 buf = mfd->ov0_wb_buf;
2575 else
2576 buf = mfd->ov1_wb_buf;
2577
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2578 if (buf->write_addr || !IS_ERR_OR_NULL(buf->ihdl))
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2579 return 0;
2580
2581 if (!buf->size) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2582 pr_err("%s:%d In valid size\n", __func__, __LINE__);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2583 return -EINVAL;
2584 }
2585
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2586 buffer_size = roundup(mfd->panel_info.xres * \
2587 mfd->panel_info.yres * 3 * 2, SZ_4K);
2588
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2589 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanama3b168b2012-03-26 11:13:11 -0700[diff] [blame]2590 pr_info("%s:%d ion based allocation mfd->mem_hid 0x%x\n",
2591 __func__, __LINE__, mfd->mem_hid);
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2592 buf->ihdl = ion_alloc(mfd->iclient, buffer_size, SZ_4K,
Ravishangar Kalyanama3b168b2012-03-26 11:13:11 -0700[diff] [blame]2593 mfd->mem_hid);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2594 if (!IS_ERR_OR_NULL(buf->ihdl)) {
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2595 if (mdp_iommu_split_domain) {
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2596 if (ion_map_iommu(mfd->iclient, buf->ihdl,
2597 DISPLAY_READ_DOMAIN, GEN_POOL, SZ_4K,
2598 0, &read_addr, &len, 0, 0)) {
2599 pr_err("ion_map_iommu() read failed\n");
2600 return -ENOMEM;
2601 }
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2602 if (mfd->mem_hid & ION_SECURE) {
2603 if (ion_phys(mfd->iclient, buf->ihdl,
2604 &addr, (size_t *)&len)) {
2605 pr_err("%s:%d: ion_phys map failed\n",
2606 __func__, __LINE__);
2607 return -ENOMEM;
2608 }
2609 } else {
2610 if (ion_map_iommu(mfd->iclient,
2611 buf->ihdl, DISPLAY_WRITE_DOMAIN,
2612 GEN_POOL, SZ_4K, 0, &addr, &len,
2613 0, 0)) {
2614 pr_err("ion_map_iommu() failed\n");
2615 return -ENOMEM;
2616 }
2617 }
2618 } else {
2619 if (ion_map_iommu(mfd->iclient, buf->ihdl,
2620 DISPLAY_READ_DOMAIN, GEN_POOL, SZ_4K,
2621 0, &addr, &len, 0, 0)) {
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2622 pr_err("ion_map_iommu() write failed\n");
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2623 return -ENOMEM;
2624 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2625 }
2626 } else {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2627 pr_err("%s:%d: ion_alloc failed\n", __func__,
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2628 __LINE__);
2629 return -ENOMEM;
2630 }
2631 } else {
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2632 addr = allocate_contiguous_memory_nomap(buffer_size,
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2633 mfd->mem_hid, 4);
2634 }
2635 if (addr) {
2636 pr_info("allocating %d bytes at %x for mdp writeback\n",
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2637 buffer_size, (u32) addr);
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2638 buf->write_addr = addr;
2639
2640 if (read_addr)
2641 buf->read_addr = read_addr;
2642 else
2643 buf->read_addr = buf->write_addr;
2644
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2645 return 0;
2646 } else {
2647 pr_err("%s cannot allocate memory for mdp writeback!\n",
2648 __func__);
2649 return -ENOMEM;
2650 }
2651}
2652
2653void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2654{
2655 struct mdp_buf_type *buf;
2656
2657 if (mix_num == MDP4_MIXER0)
2658 buf = mfd->ov0_wb_buf;
2659 else
2660 buf = mfd->ov1_wb_buf;
2661
2662 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2663 if (!IS_ERR_OR_NULL(buf->ihdl)) {
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2664 if (mdp_iommu_split_domain) {
2665 if (!(mfd->mem_hid & ION_SECURE))
2666 ion_unmap_iommu(mfd->iclient, buf->ihdl,
2667 DISPLAY_WRITE_DOMAIN, GEN_POOL);
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2668 ion_unmap_iommu(mfd->iclient, buf->ihdl,
2669 DISPLAY_READ_DOMAIN, GEN_POOL);
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2670 } else {
2671 ion_unmap_iommu(mfd->iclient, buf->ihdl,
2672 DISPLAY_READ_DOMAIN, GEN_POOL);
2673 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2674 ion_free(mfd->iclient, buf->ihdl);
Jeff Ohlstein9cb0ead2011-12-16 13:30:08 -0800[diff] [blame]2675 pr_debug("%s:%d free writeback imem\n", __func__,
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2676 __LINE__);
2677 buf->ihdl = NULL;
2678 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2679 } else {
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2680 if (buf->write_addr) {
2681 free_contiguous_memory_by_paddr(buf->write_addr);
Jeff Ohlstein9cb0ead2011-12-16 13:30:08 -0800[diff] [blame]2682 pr_debug("%s:%d free writeback pmem\n", __func__,
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2683 __LINE__);
2684 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2685 }
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2686 buf->write_addr = 0;
2687 buf->read_addr = 0;
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2688}
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2689
2690static int mdp4_update_pcc_regs(uint32_t offset,
2691 struct mdp_pcc_cfg_data *cfg_ptr)
2692{
2693 int ret = -1;
2694
2695 if (offset && cfg_ptr) {
2696
2697 outpdw(offset, cfg_ptr->r.c);
2698 outpdw(offset + 0x30, cfg_ptr->g.c);
2699 outpdw(offset + 0x60, cfg_ptr->b.c);
2700 offset += 4;
2701
2702 outpdw(offset, cfg_ptr->r.r);
2703 outpdw(offset + 0x30, cfg_ptr->g.r);
2704 outpdw(offset + 0x60, cfg_ptr->b.r);
2705 offset += 4;
2706
2707 outpdw(offset, cfg_ptr->r.g);
2708 outpdw(offset + 0x30, cfg_ptr->g.g);
2709 outpdw(offset + 0x60, cfg_ptr->b.g);
2710 offset += 4;
2711
2712 outpdw(offset, cfg_ptr->r.b);
2713 outpdw(offset + 0x30, cfg_ptr->g.b);
2714 outpdw(offset + 0x60, cfg_ptr->b.b);
2715 offset += 4;
2716
2717 outpdw(offset, cfg_ptr->r.rr);
2718 outpdw(offset + 0x30, cfg_ptr->g.rr);
2719 outpdw(offset + 0x60, cfg_ptr->b.rr);
2720 offset += 4;
2721
2722 outpdw(offset, cfg_ptr->r.gg);
2723 outpdw(offset + 0x30, cfg_ptr->g.gg);
2724 outpdw(offset + 0x60, cfg_ptr->b.gg);
2725 offset += 4;
2726
2727 outpdw(offset, cfg_ptr->r.bb);
2728 outpdw(offset + 0x30, cfg_ptr->g.bb);
2729 outpdw(offset + 0x60, cfg_ptr->b.bb);
2730 offset += 4;
2731
2732 outpdw(offset, cfg_ptr->r.rg);
2733 outpdw(offset + 0x30, cfg_ptr->g.rg);
2734 outpdw(offset + 0x60, cfg_ptr->b.rg);
2735 offset += 4;
2736
2737 outpdw(offset, cfg_ptr->r.gb);
2738 outpdw(offset + 0x30, cfg_ptr->g.gb);
2739 outpdw(offset + 0x60, cfg_ptr->b.gb);
2740 offset += 4;
2741
2742 outpdw(offset, cfg_ptr->r.rb);
2743 outpdw(offset + 0x30, cfg_ptr->g.rb);
2744 outpdw(offset + 0x60, cfg_ptr->b.rb);
2745 offset += 4;
2746
2747 outpdw(offset, cfg_ptr->r.rgb_0);
2748 outpdw(offset + 0x30, cfg_ptr->g.rgb_0);
2749 outpdw(offset + 0x60, cfg_ptr->b.rgb_0);
2750 offset += 4;
2751
2752 outpdw(offset, cfg_ptr->r.rgb_1);
2753 outpdw(offset + 0x30, cfg_ptr->g.rgb_1);
2754 outpdw(offset + 0x60, cfg_ptr->b.rgb_1);
2755
2756 ret = 0;
2757 }
2758
2759 return ret;
2760}
2761
2762static int mdp4_read_pcc_regs(uint32_t offset,
2763 struct mdp_pcc_cfg_data *cfg_ptr)
2764{
2765 int ret = -1;
2766
2767 if (offset && cfg_ptr) {
2768 cfg_ptr->r.c = inpdw(offset);
2769 cfg_ptr->g.c = inpdw(offset + 0x30);
2770 cfg_ptr->b.c = inpdw(offset + 0x60);
2771 offset += 4;
2772
2773 cfg_ptr->r.r = inpdw(offset);
2774 cfg_ptr->g.r = inpdw(offset + 0x30);
2775 cfg_ptr->b.r = inpdw(offset + 0x60);
2776 offset += 4;
2777
2778 cfg_ptr->r.g = inpdw(offset);
2779 cfg_ptr->g.g = inpdw(offset + 0x30);
2780 cfg_ptr->b.g = inpdw(offset + 0x60);
2781 offset += 4;
2782
2783 cfg_ptr->r.b = inpdw(offset);
2784 cfg_ptr->g.b = inpdw(offset + 0x30);
2785 cfg_ptr->b.b = inpdw(offset + 0x60);
2786 offset += 4;
2787
2788 cfg_ptr->r.rr = inpdw(offset);
2789 cfg_ptr->g.rr = inpdw(offset + 0x30);
2790 cfg_ptr->b.rr = inpdw(offset + 0x60);
2791 offset += 4;
2792
2793 cfg_ptr->r.gg = inpdw(offset);
2794 cfg_ptr->g.gg = inpdw(offset + 0x30);
2795 cfg_ptr->b.gg = inpdw(offset + 0x60);
2796 offset += 4;
2797
2798 cfg_ptr->r.bb = inpdw(offset);
2799 cfg_ptr->g.bb = inpdw(offset + 0x30);
2800 cfg_ptr->b.bb = inpdw(offset + 0x60);
2801 offset += 4;
2802
2803 cfg_ptr->r.rg = inpdw(offset);
2804 cfg_ptr->g.rg = inpdw(offset + 0x30);
2805 cfg_ptr->b.rg = inpdw(offset + 0x60);
2806 offset += 4;
2807
2808 cfg_ptr->r.gb = inpdw(offset);
2809 cfg_ptr->g.gb = inpdw(offset + 0x30);
2810 cfg_ptr->b.gb = inpdw(offset + 0x60);
2811 offset += 4;
2812
2813 cfg_ptr->r.rb = inpdw(offset);
2814 cfg_ptr->g.rb = inpdw(offset + 0x30);
2815 cfg_ptr->b.rb = inpdw(offset + 0x60);
2816 offset += 4;
2817
2818 cfg_ptr->r.rgb_0 = inpdw(offset);
2819 cfg_ptr->g.rgb_0 = inpdw(offset + 0x30);
2820 cfg_ptr->b.rgb_0 = inpdw(offset + 0x60);
2821 offset += 4;
2822
2823 cfg_ptr->r.rgb_1 = inpdw(offset);
2824 cfg_ptr->g.rgb_1 = inpdw(offset + 0x30);
2825 cfg_ptr->b.rgb_1 = inpdw(offset + 0x60);
2826
2827 ret = 0;
2828 }
2829
2830 return ret;
2831}
2832
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2833
2834#define MDP_PCC_OFFSET 0xA000
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2835#define MDP_DMA_GC_OFFSET 0x8800
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2836#define MDP_LM_GC_OFFSET 0x4800
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2837
2838#define MDP_DMA_P_OP_MODE_OFFSET 0x70
2839#define MDP_DMA_S_OP_MODE_OFFSET 0x28
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2840#define MDP_LM_OP_MODE_OFFSET 0x14
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2841
2842#define DMA_PCC_R2_OFFSET 0x100
2843
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2844#define MDP_GC_COLOR_OFFSET 0x100
2845#define MDP_GC_PARMS_OFFSET 0x80
2846
2847#define MDP_AR_GC_MAX_STAGES 16
2848
2849static uint32_t mdp_pp_block2pcc(uint32_t block)
2850{
2851 uint32_t valid = 0;
2852
2853 switch (block) {
2854 case MDP_BLOCK_DMA_P:
2855 case MDP_BLOCK_DMA_S:
2856 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2857 break;
2858
2859 default:
2860 break;
2861 }
2862
2863 return valid;
2864}
2865
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2866int mdp4_pcc_cfg(struct mdp_pcc_cfg_data *cfg_ptr)
2867{
2868 int ret = -1;
2869 uint32_t pcc_offset = 0, mdp_cfg_offset = 0;
2870 uint32_t mdp_dma_op_mode = 0;
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2871 uint32_t blockbase;
2872
2873 if (!mdp_pp_block2pcc(cfg_ptr->block))
2874 return ret;
2875
2876 blockbase = mdp_block2base(cfg_ptr->block);
2877 if (!blockbase)
2878 return ret;
2879
2880 blockbase += (uint32_t) MDP_BASE;
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2881
2882 switch (cfg_ptr->block) {
2883 case MDP_BLOCK_DMA_P:
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2884 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2885 pcc_offset = blockbase + MDP_PCC_OFFSET;
2886 mdp_cfg_offset = blockbase;
2887 mdp_dma_op_mode = blockbase +
2888 (MDP_BLOCK_DMA_P == cfg_ptr->block ?
2889 MDP_DMA_P_OP_MODE_OFFSET
2890 : MDP_DMA_S_OP_MODE_OFFSET);
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2891 break;
2892
2893 default:
2894 break;
2895 }
2896
2897 if (0x8 & cfg_ptr->ops)
2898 pcc_offset += DMA_PCC_R2_OFFSET;
2899
2900 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2901
2902 switch ((0x6 & cfg_ptr->ops)>>1) {
2903 case 0x1:
2904 ret = mdp4_read_pcc_regs(pcc_offset, cfg_ptr);
2905 break;
2906
2907 case 0x2:
2908 ret = mdp4_update_pcc_regs(pcc_offset, cfg_ptr);
2909 break;
2910
2911 default:
2912 break;
2913 }
2914
2915 if (0x8 & cfg_ptr->ops)
2916 outpdw(mdp_dma_op_mode,
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]2917 ((inpdw(mdp_dma_op_mode) & ~(0x1<<10)) |
2918 ((0x8 & cfg_ptr->ops)<<10)));
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2919
2920 outpdw(mdp_cfg_offset,
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]2921 ((inpdw(mdp_cfg_offset) & ~(0x1<<29)) |
2922 ((cfg_ptr->ops & 0x1)<<29)));
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2923
2924 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2925
2926 return ret;
2927}
2928
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2929static uint32_t mdp_pp_block2argc(uint32_t block)
2930{
2931 uint32_t valid = 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2932
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2933 switch (block) {
2934 case MDP_BLOCK_DMA_P:
2935 case MDP_BLOCK_DMA_S:
2936 case MDP_BLOCK_OVERLAY_0:
2937 case MDP_BLOCK_OVERLAY_1:
2938 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2939 break;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2940
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2941 case MDP_BLOCK_OVERLAY_2:
2942 valid = (mdp_rev >= MDP_REV_44) ? 1 : 0;
2943 break;
2944
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2945 default:
2946 break;
2947 }
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2948
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2949 return valid;
2950}
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2951
2952static int update_ar_gc_lut(uint32_t *offset, struct mdp_pgc_lut_data *lut_data)
2953{
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2954 int count = 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2955
2956 uint32_t *c0_offset = offset;
2957 uint32_t *c0_params_offset = (uint32_t *)((uint32_t)c0_offset
2958 + MDP_GC_PARMS_OFFSET);
2959
2960 uint32_t *c1_offset = (uint32_t *)((uint32_t)offset
2961 + MDP_GC_COLOR_OFFSET);
2962
2963 uint32_t *c1_params_offset = (uint32_t *)((uint32_t)c1_offset
2964 + MDP_GC_PARMS_OFFSET);
2965
2966 uint32_t *c2_offset = (uint32_t *)((uint32_t)offset
2967 + 2*MDP_GC_COLOR_OFFSET);
2968
2969 uint32_t *c2_params_offset = (uint32_t *)((uint32_t)c2_offset
2970 +MDP_GC_PARMS_OFFSET);
2971
2972
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2973 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2974 for (count = 0; count < MDP_AR_GC_MAX_STAGES; count++) {
2975 if (count < lut_data->num_r_stages) {
2976 outpdw(c0_offset+count,
2977 ((0xfff & lut_data->r_data[count].x_start)
2978 | 0x10000));
2979
2980 outpdw(c0_params_offset+count,
2981 ((0x7fff & lut_data->r_data[count].slope)
2982 | ((0xffff
2983 & lut_data->r_data[count].offset)
2984 << 16)));
2985 } else
2986 outpdw(c0_offset+count, 0);
2987
2988 if (count < lut_data->num_b_stages) {
2989 outpdw(c1_offset+count,
2990 ((0xfff & lut_data->b_data[count].x_start)
2991 | 0x10000));
2992
2993 outpdw(c1_params_offset+count,
2994 ((0x7fff & lut_data->b_data[count].slope)
2995 | ((0xffff
2996 & lut_data->b_data[count].offset)
2997 << 16)));
2998 } else
2999 outpdw(c1_offset+count, 0);
3000
3001 if (count < lut_data->num_g_stages) {
3002 outpdw(c2_offset+count,
3003 ((0xfff & lut_data->g_data[count].x_start)
3004 | 0x10000));
3005
3006 outpdw(c2_params_offset+count,
3007 ((0x7fff & lut_data->g_data[count].slope)
3008 | ((0xffff
3009 & lut_data->g_data[count].offset)
3010 << 16)));
3011 } else
3012 outpdw(c2_offset+count, 0);
3013 }
3014
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3015 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3016
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3017 return 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3018}
3019
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3020static int mdp4_argc_process_write_req(uint32_t *offset,
3021 struct mdp_pgc_lut_data *pgc_ptr)
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3022{
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3023 int ret = -1;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3024 struct mdp_ar_gc_lut_data r[MDP_AR_GC_MAX_STAGES];
3025 struct mdp_ar_gc_lut_data g[MDP_AR_GC_MAX_STAGES];
3026 struct mdp_ar_gc_lut_data b[MDP_AR_GC_MAX_STAGES];
3027
3028 ret = copy_from_user(&r[0], pgc_ptr->r_data,
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3029 pgc_ptr->num_r_stages * sizeof(struct mdp_ar_gc_lut_data));
3030
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3031 if (!ret) {
3032 ret = copy_from_user(&g[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3033 pgc_ptr->g_data,
3034 pgc_ptr->num_g_stages
3035 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3036 if (!ret)
3037 ret = copy_from_user(&b[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3038 pgc_ptr->b_data,
3039 pgc_ptr->num_b_stages
3040 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3041 }
3042
3043 if (ret)
3044 return ret;
3045
3046 pgc_ptr->r_data = &r[0];
3047 pgc_ptr->g_data = &g[0];
3048 pgc_ptr->b_data = &b[0];
3049
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3050 ret = update_ar_gc_lut(offset, pgc_ptr);
3051 return ret;
3052}
3053
3054int mdp4_argc_cfg(struct mdp_pgc_lut_data *pgc_ptr)
3055{
3056 int ret = -1;
3057 uint32_t *offset = 0, *pgc_enable_offset = 0, lshift_bits = 0;
3058 uint32_t blockbase;
3059
3060 if (!mdp_pp_block2argc(pgc_ptr->block))
3061 return ret;
3062
3063 blockbase = mdp_block2base(pgc_ptr->block);
3064 if (!blockbase)
3065 return ret;
3066
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3067 blockbase += (uint32_t) MDP_BASE;
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3068 ret = 0;
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3069
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3070 switch (pgc_ptr->block) {
3071 case MDP_BLOCK_DMA_P:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3072 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3073 offset = (uint32_t *)(blockbase + MDP_DMA_GC_OFFSET);
3074 pgc_enable_offset = (uint32_t *) blockbase;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3075 lshift_bits = 28;
3076 break;
3077
3078 case MDP_BLOCK_OVERLAY_0:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3079 case MDP_BLOCK_OVERLAY_1:
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]3080 case MDP_BLOCK_OVERLAY_2:
3081 offset = (uint32_t *)(blockbase + MDP_LM_GC_OFFSET);
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]3082 pgc_enable_offset = (uint32_t *)(blockbase
3083 + MDP_LM_OP_MODE_OFFSET);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3084 lshift_bits = 2;
3085 break;
3086
3087 default:
3088 ret = -1;
3089 break;
3090 }
3091
3092 if (!ret) {
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3093
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3094 switch ((0x6 & pgc_ptr->flags)>>1) {
3095 case 0x1:
3096 ret = -ENOTTY;
3097 break;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3098
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3099 case 0x2:
3100 ret = mdp4_argc_process_write_req(offset, pgc_ptr);
3101 break;
3102
3103 default:
3104 break;
3105 }
3106
3107 if (!ret) {
3108 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]3109 outpdw(pgc_enable_offset, (inpdw(pgc_enable_offset) &
3110 ~(0x1<<lshift_bits)) |
3111 ((0x1 & pgc_ptr->flags) << lshift_bits));
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]3112 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF,
3113 FALSE);
3114 }
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]3115 }
3116
3117 return ret;
3118}
3119
Carl Vanderlipacde4b62011-12-16 15:50:56 -0800[diff] [blame]3120static uint32_t mdp4_pp_block2igc(uint32_t block)
3121{
3122 uint32_t valid = 0;
3123 switch (block) {
3124 case MDP_BLOCK_VG_1:
3125 valid = 0x1;
3126 break;
3127 case MDP_BLOCK_VG_2:
3128 valid = 0x1;
3129 break;
3130 case MDP_BLOCK_RGB_1:
3131 valid = 0x1;
3132 break;
3133 case MDP_BLOCK_RGB_2:
3134 valid = 0x1;
3135 break;
3136 case MDP_BLOCK_DMA_P:
3137 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
3138 break;
3139 case MDP_BLOCK_DMA_S:
3140 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
3141 break;
3142 default:
3143 break;
3144 }
3145 return valid;
3146}
3147
3148static int mdp4_igc_lut_write(struct mdp_igc_lut_data *cfg, uint32_t en_off,
3149 uint32_t lut_off)
3150{
3151 int i;
3152 uint32_t base, *off_low, *off_high;
3153 uint32_t low[cfg->len];
3154 uint32_t high[cfg->len];
3155
3156 base = mdp_block2base(cfg->block);
3157
3158 if (cfg->len != 256)
3159 return -EINVAL;
3160
3161 off_low = (uint32_t *)(MDP_BASE + base + lut_off);
3162 off_high = (uint32_t *)(MDP_BASE + base + lut_off + 0x800);
3163 if (copy_from_user(&low, cfg->c0_c1_data, cfg->len * sizeof(uint32_t)))
3164 return -EFAULT;
3165 if (copy_from_user(&high, cfg->c2_data, cfg->len * sizeof(uint32_t)))
3166 return -EFAULT;
3167
3168 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3169 for (i = 0; i < cfg->len; i++) {
3170 MDP_OUTP(off_low++, low[i]);
3171 /*low address write should occur before high address write*/
3172 wmb();
3173 MDP_OUTP(off_high++, high[i]);
3174 }
3175 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3176 return 0;
3177}
3178
3179static int mdp4_igc_lut_ctrl(struct mdp_igc_lut_data *cfg)
3180{
3181 uint32_t mask, out;
3182 uint32_t base = mdp_block2base(cfg->block);
3183 int8_t shift = 0;
3184
3185 switch (cfg->block) {
3186 case MDP_BLOCK_DMA_P:
3187 case MDP_BLOCK_DMA_S:
3188 base = base;
3189 shift = 30;
3190 break;
3191 case MDP_BLOCK_VG_1:
3192 case MDP_BLOCK_VG_2:
3193 case MDP_BLOCK_RGB_1:
3194 case MDP_BLOCK_RGB_2:
3195 base += 0x58;
3196 shift = 16;
3197 break;
3198 default:
3199 return -EINVAL;
3200
3201 }
3202 out = 1<<shift;
3203 mask = ~out;
3204 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3205 out = inpdw(MDP_BASE + base) & mask;
3206 MDP_OUTP(MDP_BASE + base, out | ((cfg->ops & 0x1)<<shift));
3207 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3208
3209 return 0;
3210}
3211
3212static int mdp4_igc_lut_write_cfg(struct mdp_igc_lut_data *cfg)
3213{
3214 int ret = 0;
3215
3216 switch (cfg->block) {
3217 case MDP_BLOCK_DMA_P:
3218 case MDP_BLOCK_DMA_S:
3219 ret = mdp4_igc_lut_write(cfg, 0x00, 0x9000);
3220 break;
3221 case MDP_BLOCK_VG_1:
3222 case MDP_BLOCK_VG_2:
3223 case MDP_BLOCK_RGB_1:
3224 case MDP_BLOCK_RGB_2:
3225 ret = mdp4_igc_lut_write(cfg, 0x58, 0x5000);
3226 break;
3227 default:
3228 ret = -EINVAL;
3229 }
3230
3231 return ret;
3232}
3233
3234int mdp4_igc_lut_config(struct mdp_igc_lut_data *cfg)
3235{
3236 int ret = 0;
3237
3238 if (!mdp4_pp_block2igc(cfg->block)) {
3239 ret = -ENOTTY;
3240 goto error;
3241 }
3242
3243 switch ((cfg->ops & 0x6) >> 1) {
3244 case 0x1:
3245 pr_info("%s: IGC LUT read not supported\n", __func__);
3246 break;
3247 case 0x2:
3248 ret = mdp4_igc_lut_write_cfg(cfg);
3249 if (ret)
3250 goto error;
3251 break;
3252 default:
3253 break;
3254 }
3255
3256 ret = mdp4_igc_lut_ctrl(cfg);
3257
3258error:
3259 return ret;
3260}
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3261
3262#define QSEED_TABLE_1_COUNT 2
3263#define QSEED_TABLE_2_COUNT 1024
3264
3265static uint32_t mdp4_pp_block2qseed(uint32_t block)
3266{
3267 uint32_t valid = 0;
3268 switch (block) {
3269 case MDP_BLOCK_VG_1:
3270 case MDP_BLOCK_VG_2:
3271 valid = 0x1;
3272 break;
3273 default:
3274 break;
3275 }
3276 return valid;
3277}
3278
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3279static int mdp4_qseed_access_cfg(struct mdp_qseed_cfg_data *cfg)
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3280{
3281 int i, ret = 0;
3282 uint32_t base = (uint32_t) (MDP_BASE + mdp_block2base(cfg->block));
3283 uint32_t *values;
3284
3285 if ((cfg->table_num != 1) && (cfg->table_num != 2)) {
3286 ret = -ENOTTY;
3287 goto error;
3288 }
3289
3290 if (((cfg->table_num == 1) && (cfg->len != QSEED_TABLE_1_COUNT)) ||
3291 ((cfg->table_num == 2) && (cfg->len != QSEED_TABLE_2_COUNT))) {
3292 ret = -EINVAL;
3293 goto error;
3294 }
3295
3296 values = kmalloc(cfg->len * sizeof(uint32_t), GFP_KERNEL);
3297 if (!values) {
3298 ret = -ENOMEM;
3299 goto error;
3300 }
3301
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3302 base += (cfg->table_num == 1) ? MDP4_QSEED_TABLE1_OFF :
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3303 MDP4_QSEED_TABLE2_OFF;
3304
3305 if (cfg->ops & MDP_PP_OPS_WRITE) {
3306 ret = copy_from_user(values, cfg->data,
3307 sizeof(uint32_t) * cfg->len);
3308 if (ret) {
3309 pr_warn("%s: Error copying from user, %d", __func__,
3310 ret);
3311 ret = -EINVAL;
3312 goto err_mem;
3313 }
3314 for (i = 0; i < cfg->len; i++) {
Carl Vanderlip382b00b2012-05-16 16:45:07 -0700[diff] [blame^]3315 if (!(base & 0x3FF))
3316 wmb();
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3317 MDP_OUTP(base , values[i]);
3318 base += sizeof(uint32_t);
3319 }
3320 } else if (cfg->ops & MDP_PP_OPS_READ) {
3321 for (i = 0; i < cfg->len; i++) {
3322 values[i] = inpdw(base);
Carl Vanderlip382b00b2012-05-16 16:45:07 -0700[diff] [blame^]3323 if (!(base & 0x3FF))
3324 rmb();
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3325 base += sizeof(uint32_t);
3326 }
3327 ret = copy_to_user(cfg->data, values,
3328 sizeof(uint32_t) * cfg->len);
3329 if (ret) {
3330 pr_warn("%s: Error copying to user, %d", __func__, ret);
3331 ret = -EINVAL;
3332 goto err_mem;
3333 }
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3334 }
3335
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3336err_mem:
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3337 kfree(values);
3338error:
3339 return ret;
3340}
3341
3342int mdp4_qseed_cfg(struct mdp_qseed_cfg_data *cfg)
3343{
3344 int ret = 0;
3345
3346 if (!mdp4_pp_block2qseed(cfg->block)) {
3347 ret = -ENOTTY;
3348 goto error;
3349 }
3350
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3351 if ((cfg->ops & MDP_PP_OPS_READ) && (cfg->ops & MDP_PP_OPS_WRITE)) {
3352 ret = -EPERM;
3353 pr_warn("%s: Cannot read and write on the same request\n",
3354 __func__);
3355 goto error;
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3356 }
3357
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3358 ret = mdp4_qseed_access_cfg(cfg);
3359
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3360error:
3361 return ret;
3362}