blob: 61b5228386aa3db7f4ba1c2ce5dff6f3b6863238 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/spinlock.h>
Stephen Boyd387ac2e2011-09-28 10:29:43 -070015#include <asm/mach-types.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070016
17DEFINE_RAW_SPINLOCK(l2_access_lock);
18
19u32 set_get_l2_indirect_reg(u32 reg_addr, u32 val)
20{
21 unsigned long flags;
22 u32 ret_val;
Stephen Boyd387ac2e2011-09-28 10:29:43 -070023 /* CP15 registers are not emulated on RUMI3. */
24 if (machine_is_msm8960_rumi3())
25 return 0;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070026
27 raw_spin_lock_irqsave(&l2_access_lock, flags);
28
Stephen Boyd387ac2e2011-09-28 10:29:43 -070029 mb();
30 asm volatile ("mcr p15, 3, %[l2cpselr], c15, c0, 6\n\t"
31 "mcr p15, 3, %[l2cpdr], c15, c0, 7\n\t"
32 :
33 : [l2cpselr]"r" (reg_addr), [l2cpdr]"r" (val)
34 );
35 isb();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036 /* Ensure the value took */
37 asm volatile ("mrc p15, 3, %0, c15, c0, 7" : "=r" (ret_val));
38
39 raw_spin_unlock_irqrestore(&l2_access_lock, flags);
40
41 return ret_val;
42}
43
44void set_l2_indirect_reg(u32 reg_addr, u32 val)
45{
46 unsigned long flags;
Stephen Boyd387ac2e2011-09-28 10:29:43 -070047 /* CP15 registers are not emulated on RUMI3. */
48 if (machine_is_msm8960_rumi3())
49 return;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070050
51 raw_spin_lock_irqsave(&l2_access_lock, flags);
Stephen Boyd387ac2e2011-09-28 10:29:43 -070052 mb();
53 asm volatile ("mcr p15, 3, %[l2cpselr], c15, c0, 6\n\t"
54 "mcr p15, 3, %[l2cpdr], c15, c0, 7\n\t"
55 :
56 : [l2cpselr]"r" (reg_addr), [l2cpdr]"r" (val)
57 );
58 isb();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070059 raw_spin_unlock_irqrestore(&l2_access_lock, flags);
60}
61
62u32 get_l2_indirect_reg(u32 reg_addr)
63{
64 u32 val;
65 unsigned long flags;
Stephen Boyd387ac2e2011-09-28 10:29:43 -070066 /* CP15 registers are not emulated on RUMI3. */
67 if (machine_is_msm8960_rumi3())
68 return 0;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069
70 raw_spin_lock_irqsave(&l2_access_lock, flags);
Stephen Boyd387ac2e2011-09-28 10:29:43 -070071 asm volatile ("mcr p15, 3, %[l2cpselr], c15, c0, 6\n\t"
72 "mrc p15, 3, %[l2cpdr], c15, c0, 7\n\t"
73 : [l2cpdr]"=r" (val)
74 : [l2cpselr]"r" (reg_addr)
75 );
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076 raw_spin_unlock_irqrestore(&l2_access_lock, flags);
77
78 return val;
79}