Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-tegra/platsmp.c |
| 3 | * |
| 4 | * Copyright (C) 2002 ARM Ltd. |
| 5 | * All Rights Reserved |
| 6 | * |
| 7 | * Copyright (C) 2009 Palm |
| 8 | * All Rights Reserved |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/errno.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/jiffies.h> |
| 19 | #include <linux/smp.h> |
| 20 | #include <linux/io.h> |
| 21 | |
| 22 | #include <asm/cacheflush.h> |
| 23 | #include <mach/hardware.h> |
| 24 | #include <asm/mach-types.h> |
| 25 | #include <asm/localtimer.h> |
| 26 | #include <asm/smp_scu.h> |
| 27 | |
| 28 | #include <mach/iomap.h> |
| 29 | |
| 30 | extern void tegra_secondary_startup(void); |
| 31 | |
| 32 | static DEFINE_SPINLOCK(boot_lock); |
| 33 | static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); |
| 34 | |
| 35 | #define EVP_CPU_RESET_VECTOR \ |
| 36 | (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) |
| 37 | #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \ |
| 38 | (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c) |
| 39 | #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \ |
| 40 | (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344) |
| 41 | |
| 42 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 43 | { |
| 44 | trace_hardirqs_off(); |
| 45 | |
| 46 | /* |
| 47 | * if any interrupts are already enabled for the primary |
| 48 | * core (e.g. timer irq), then they will not have been enabled |
| 49 | * for us: do so |
| 50 | */ |
| 51 | gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100); |
| 52 | |
| 53 | /* |
| 54 | * Synchronise with the boot thread. |
| 55 | */ |
| 56 | spin_lock(&boot_lock); |
| 57 | spin_unlock(&boot_lock); |
| 58 | } |
| 59 | |
| 60 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 61 | { |
| 62 | unsigned long old_boot_vector; |
| 63 | unsigned long boot_vector; |
| 64 | unsigned long timeout; |
| 65 | u32 reg; |
| 66 | |
| 67 | /* |
| 68 | * set synchronisation state between this boot processor |
| 69 | * and the secondary one |
| 70 | */ |
| 71 | spin_lock(&boot_lock); |
| 72 | |
| 73 | |
| 74 | /* set the reset vector to point to the secondary_startup routine */ |
| 75 | |
| 76 | boot_vector = virt_to_phys(tegra_secondary_startup); |
| 77 | old_boot_vector = readl(EVP_CPU_RESET_VECTOR); |
| 78 | writel(boot_vector, EVP_CPU_RESET_VECTOR); |
| 79 | |
| 80 | /* enable cpu clock on cpu1 */ |
| 81 | reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |
| 82 | writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX); |
| 83 | |
| 84 | reg = (1<<13) | (1<<9) | (1<<5) | (1<<1); |
| 85 | writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); |
| 86 | |
| 87 | smp_wmb(); |
| 88 | flush_cache_all(); |
| 89 | |
| 90 | /* unhalt the cpu */ |
| 91 | writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14); |
| 92 | |
| 93 | timeout = jiffies + (1 * HZ); |
| 94 | while (time_before(jiffies, timeout)) { |
| 95 | if (readl(EVP_CPU_RESET_VECTOR) != boot_vector) |
| 96 | break; |
| 97 | udelay(10); |
| 98 | } |
| 99 | |
| 100 | /* put the old boot vector back */ |
| 101 | writel(old_boot_vector, EVP_CPU_RESET_VECTOR); |
| 102 | |
| 103 | /* |
| 104 | * now the secondary core is starting up let it run its |
| 105 | * calibrations, then wait for it to finish |
| 106 | */ |
| 107 | spin_unlock(&boot_lock); |
| 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Initialise the CPU possible map early - this describes the CPUs |
| 114 | * which may be present or become present in the system. |
| 115 | */ |
| 116 | void __init smp_init_cpus(void) |
| 117 | { |
| 118 | unsigned int i, ncores = scu_get_core_count(scu_base); |
| 119 | |
| 120 | for (i = 0; i < ncores; i++) |
| 121 | cpu_set(i, cpu_possible_map); |
| 122 | } |
| 123 | |
| 124 | void __init smp_prepare_cpus(unsigned int max_cpus) |
| 125 | { |
| 126 | unsigned int ncores = scu_get_core_count(scu_base); |
| 127 | unsigned int cpu = smp_processor_id(); |
| 128 | int i; |
| 129 | |
| 130 | smp_store_cpu_info(cpu); |
| 131 | |
| 132 | /* |
| 133 | * are we trying to boot more cores than exist? |
| 134 | */ |
| 135 | if (max_cpus > ncores) |
| 136 | max_cpus = ncores; |
| 137 | |
| 138 | /* |
| 139 | * Initialise the present map, which describes the set of CPUs |
| 140 | * actually populated at the present time. |
| 141 | */ |
| 142 | for (i = 0; i < max_cpus; i++) |
| 143 | set_cpu_present(i, true); |
| 144 | |
| 145 | /* |
| 146 | * Initialise the SCU if there are more than one CPU and let |
| 147 | * them know where to start. Note that, on modern versions of |
| 148 | * MILO, the "poke" doesn't actually do anything until each |
| 149 | * individual core is sent a soft interrupt to get it out of |
| 150 | * WFI |
| 151 | */ |
| 152 | if (max_cpus > 1) { |
| 153 | percpu_timer_setup(); |
| 154 | scu_enable(scu_base); |
| 155 | } |
| 156 | } |