| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /*+M************************************************************************* | 
|  | 2 | * Perceptive Solutions, Inc. PSI-240I device driver proc support for Linux. | 
|  | 3 | * | 
|  | 4 | * Copyright (c) 1997 Perceptive Solutions, Inc. | 
|  | 5 | * | 
|  | 6 | * This program is free software; you can redistribute it and/or modify | 
|  | 7 | * it under the terms of the GNU General Public License as published by | 
|  | 8 | * the Free Software Foundation; either version 2, or (at your option) | 
|  | 9 | * any later version. | 
|  | 10 | * | 
|  | 11 | * This program is distributed in the hope that it will be useful, | 
|  | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 
|  | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
|  | 14 | * GNU General Public License for more details. | 
|  | 15 | * | 
|  | 16 | * You should have received a copy of the GNU General Public License | 
|  | 17 | * along with this program; see the file COPYING.  If not, write to | 
|  | 18 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | 
|  | 19 | * | 
|  | 20 | * | 
|  | 21 | *	File Name:	psi_chip.h | 
|  | 22 | * | 
|  | 23 | *	Description:	This file contains the interface defines and | 
|  | 24 | *					error codes. | 
|  | 25 | * | 
|  | 26 | *-M*************************************************************************/ | 
|  | 27 | #ifndef PSI_CHIP | 
|  | 28 | #define PSI_CHIP | 
|  | 29 |  | 
|  | 30 | /************************************************/ | 
|  | 31 | /*		Misc konstants							*/ | 
|  | 32 | /************************************************/ | 
|  | 33 | #define	CHIP_MAXDRIVES			8 | 
|  | 34 |  | 
|  | 35 | /************************************************/ | 
|  | 36 | /*		Chip I/O addresses						*/ | 
|  | 37 | /************************************************/ | 
|  | 38 | #define	CHIP_ADRS_0				0x0130 | 
|  | 39 | #define	CHIP_ADRS_1				0x0150 | 
|  | 40 | #define	CHIP_ADRS_2				0x0190 | 
|  | 41 | #define	CHIP_ADRS_3				0x0210 | 
|  | 42 | #define	CHIP_ADRS_4				0x0230 | 
|  | 43 | #define	CHIP_ADRS_5				0x0250 | 
|  | 44 |  | 
|  | 45 | /************************************************/ | 
|  | 46 | /*		EEPROM locations		*/ | 
|  | 47 | /************************************************/ | 
|  | 48 | #define	CHIP_EEPROM_BIOS		0x0000		// BIOS base address | 
|  | 49 | #define	CHIP_EEPROM_DATA		0x2000	   	// SETUP data base address | 
|  | 50 | #define	CHIP_EEPROM_FACTORY		0x2400	   	// FACTORY data base address | 
|  | 51 | #define	CHIP_EEPROM_SETUP		0x3000	   	// SETUP PROGRAM base address | 
|  | 52 |  | 
|  | 53 | #define	CHIP_EEPROM_SIZE		32768U	   	// size of the entire EEPROM | 
|  | 54 | #define	CHIP_EEPROM_BIOS_SIZE	8192	   	// size of the BIOS in bytes | 
|  | 55 | #define	CHIP_EEPROM_DATA_SIZE	4096	   	// size of factory, setup, log data block in bytes | 
|  | 56 | #define	CHIP_EEPROM_SETUP_SIZE	20480U	   	// size of the setup program in bytes | 
|  | 57 |  | 
|  | 58 | /************************************************/ | 
|  | 59 | /*		Chip Interrupts							*/ | 
|  | 60 | /************************************************/ | 
|  | 61 | #define	CHIP_IRQ_10				0x72 | 
|  | 62 | #define	CHIP_IRQ_11				0x73 | 
|  | 63 | #define	CHIP_IRQ_12				0x74 | 
|  | 64 |  | 
|  | 65 | /************************************************/ | 
|  | 66 | /*		Chip Setup addresses		*/ | 
|  | 67 | /************************************************/ | 
|  | 68 | #define	CHIP_SETUP_BASE			0x0000C000L | 
|  | 69 |  | 
|  | 70 | /************************************************/ | 
|  | 71 | /*		Chip Register address offsets	*/ | 
|  | 72 | /************************************************/ | 
|  | 73 | #define	REG_DATA				0x00 | 
|  | 74 | #define	REG_ERROR				0x01 | 
|  | 75 | #define	REG_SECTOR_COUNT		0x02 | 
|  | 76 | #define	REG_LBA_0				0x03 | 
|  | 77 | #define	REG_LBA_8				0x04 | 
|  | 78 | #define	REG_LBA_16				0x05 | 
|  | 79 | #define	REG_LBA_24				0x06 | 
|  | 80 | #define	REG_STAT_CMD			0x07 | 
|  | 81 | #define	REG_SEL_FAIL			0x08 | 
|  | 82 | #define	REG_IRQ_STATUS			0x09 | 
|  | 83 | #define	REG_ADDRESS				0x0A | 
|  | 84 | #define	REG_FAIL				0x0C | 
|  | 85 | #define	REG_ALT_STAT		   	0x0E | 
|  | 86 | #define	REG_DRIVE_ADRS			0x0F | 
|  | 87 |  | 
|  | 88 | /************************************************/ | 
|  | 89 | /*		Chip RAM locations		*/ | 
|  | 90 | /************************************************/ | 
|  | 91 | #define	CHIP_DEVICE				0x8000 | 
|  | 92 | #define	CHIP_DEVICE_0			0x8000 | 
|  | 93 | #define CHIP_DEVICE_1			0x8008 | 
|  | 94 | #define	CHIP_DEVICE_2			0x8010 | 
|  | 95 | #define	CHIP_DEVICE_3			0x8018 | 
|  | 96 | #define	CHIP_DEVICE_4			0x8020 | 
|  | 97 | #define	CHIP_DEVICE_5			0x8028 | 
|  | 98 | #define	CHIP_DEVICE_6			0x8030 | 
|  | 99 | #define	CHIP_DEVICE_7			0x8038 | 
|  | 100 | typedef struct | 
|  | 101 | { | 
|  | 102 | UCHAR	channel;		// channel of this device (0-8). | 
|  | 103 | UCHAR	spt;			// Sectors Per Track. | 
|  | 104 | ULONG	spc;			// Sectors Per Cylinder. | 
|  | 105 | }	CHIP_DEVICE_N; | 
|  | 106 |  | 
|  | 107 | #define	CHIP_CONFIG				0x8100		// address of boards configuration. | 
|  | 108 | typedef struct | 
|  | 109 | { | 
|  | 110 | UCHAR		irq;			// interrupt request channel number | 
|  | 111 | UCHAR		numDrives;		// Number of accessible drives | 
|  | 112 | UCHAR		fastFormat;	 	// Boolean for fast format enable | 
|  | 113 | }	CHIP_CONFIG_N; | 
|  | 114 |  | 
|  | 115 | #define	CHIP_MAP				0x8108 		// eight byte device type map. | 
|  | 116 |  | 
|  | 117 |  | 
|  | 118 | #define	CHIP_RAID				0x8120 		// array of RAID signature structures and LBA | 
|  | 119 | #define	CHIP_RAID_1				0x8120 | 
|  | 120 | #define CHIP_RAID_2				0x8130 | 
|  | 121 | #define	CHIP_RAID_3				0x8140 | 
|  | 122 | #define	CHIP_RAID_4				0x8150 | 
|  | 123 |  | 
|  | 124 | /************************************************/ | 
|  | 125 | /*		Chip Register Masks		*/ | 
|  | 126 | /************************************************/ | 
|  | 127 | #define	CHIP_ID					0x7B | 
|  | 128 | #define	SEL_RAM					0x8000 | 
|  | 129 | #define	MASK_FAIL				0x80 | 
|  | 130 |  | 
|  | 131 | /************************************************/ | 
|  | 132 | /*		Chip cable select bits		*/ | 
|  | 133 | /************************************************/ | 
|  | 134 | #define	SECTORSXFER				8 | 
|  | 135 |  | 
|  | 136 | /************************************************/ | 
|  | 137 | /*		Chip cable select bits		*/ | 
|  | 138 | /************************************************/ | 
|  | 139 | #define	SEL_NONE				0x00 | 
|  | 140 | #define	SEL_1					0x01 | 
|  | 141 | #define	SEL_2					0x02 | 
|  | 142 | #define	SEL_3					0x04 | 
|  | 143 | #define	SEL_4					0x08 | 
|  | 144 |  | 
|  | 145 | /************************************************/ | 
|  | 146 | /*		Programmable Interrupt Controller*/ | 
|  | 147 | /************************************************/ | 
|  | 148 | #define	PIC1					0x20		// first 8259 base port address | 
|  | 149 | #define	PIC2					0xA0		// second 8259 base port address | 
|  | 150 | #define	INT_OCW1				1			// Operation Control Word 1: IRQ mask | 
|  | 151 | #define	EOI						0x20		// non-specific end-of-interrupt | 
|  | 152 |  | 
|  | 153 | /************************************************/ | 
|  | 154 | /*		Device/Geometry controls				*/ | 
|  | 155 | /************************************************/ | 
|  | 156 | #define GEOMETRY_NONE		 	0x0			// No device | 
|  | 157 | #define GEOMETRY_AUTO			0x1			// Geometry set automatically | 
|  | 158 | #define GEOMETRY_USER		 	0x2			// User supplied geometry | 
|  | 159 |  | 
|  | 160 | #define	DEVICE_NONE				0x0			// No device present | 
|  | 161 | #define	DEVICE_INACTIVE			0x1			// device present but not registered active | 
|  | 162 | #define	DEVICE_ATAPI			0x2			// ATAPI device (CD_ROM, Tape, Etc...) | 
|  | 163 | #define	DEVICE_DASD_NONLBA		0x3			// Non LBA incompatible device | 
|  | 164 | #define	DEVICE_DASD_LBA			0x4			// LBA compatible device | 
|  | 165 |  | 
|  | 166 | /************************************************/ | 
|  | 167 | /*		Setup Structure Definitions	*/ | 
|  | 168 | /************************************************/ | 
|  | 169 | typedef struct							// device setup parameters | 
|  | 170 | { | 
|  | 171 | UCHAR			geometryControl;	// geometry control flags | 
|  | 172 | UCHAR		   	device;				// device code | 
|  | 173 | USHORT			sectors;			// number of sectors per track | 
|  | 174 | USHORT			heads;				// number of heads | 
|  | 175 | USHORT			cylinders;			// number of cylinders for this device | 
|  | 176 | ULONG			blocks;				// number of blocks on device | 
|  | 177 | USHORT			spare1; | 
|  | 178 | USHORT			spare2; | 
|  | 179 | } SETUP_DEVICE, *PSETUP_DEVICE; | 
|  | 180 |  | 
|  | 181 | typedef struct		// master setup structure | 
|  | 182 | { | 
|  | 183 | USHORT 			startupDelay; | 
|  | 184 | USHORT 			promptBIOS; | 
|  | 185 | USHORT 			fastFormat; | 
|  | 186 | USHORT			spare2; | 
|  | 187 | USHORT			spare3; | 
|  | 188 | USHORT			spare4; | 
|  | 189 | USHORT			spare5; | 
|  | 190 | USHORT			spare6; | 
|  | 191 | SETUP_DEVICE	setupDevice[8]; | 
|  | 192 | }	SETUP, *PSETUP; | 
|  | 193 |  | 
|  | 194 | #endif | 
|  | 195 |  |