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review.evervolv.com / android_kernel_htc_msm8960 / 3c5fd9c77d609b51c0bab682c9d40cbb496ec6f1 / . / include / asm-mips / asmmacro.h
blob: 7a881755800f94a4be165b989a9f2f54fb6ffaa1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_ASMMACRO_H
9#define _ASM_ASMMACRO_H
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]11#include <asm/hazards.h>
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]12
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]13#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]14#include <asm/asmmacro-32.h>
15#endif
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]16#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]17#include <asm/asmmacro-64.h>
18#endif
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]19#ifdef CONFIG_MIPS_MT_SMTC
20#include <asm/mipsmtregs.h>
21#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]22
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]23#ifdef CONFIG_MIPS_MT_SMTC
24 .macro local_irq_enable reg=t0
25 mfc0 \reg, CP0_TCSTATUS
26 ori \reg, \reg, TCSTATUS_IXMT
27 xori \reg, \reg, TCSTATUS_IXMT
28 mtc0 \reg, CP0_TCSTATUS
Ralf Baechle4277ff52006-06-03 22:40:15 +0100[diff] [blame]29 _ehb
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]30 .endm
31
32 .macro local_irq_disable reg=t0
33 mfc0 \reg, CP0_TCSTATUS
34 ori \reg, \reg, TCSTATUS_IXMT
35 mtc0 \reg, CP0_TCSTATUS
Ralf Baechle4277ff52006-06-03 22:40:15 +0100[diff] [blame]36 _ehb
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]37 .endm
38#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]39 .macro local_irq_enable reg=t0
40 mfc0 \reg, CP0_STATUS
41 ori \reg, \reg, 1
42 mtc0 \reg, CP0_STATUS
43 irq_enable_hazard
44 .endm
45
46 .macro local_irq_disable reg=t0
47 mfc0 \reg, CP0_STATUS
48 ori \reg, \reg, 1
49 xori \reg, \reg, 1
50 mtc0 \reg, CP0_STATUS
51 irq_disable_hazard
52 .endm
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]53#endif /* CONFIG_MIPS_MT_SMTC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]54
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]55/*
56 * Temporary until all gas have MT ASE support
57 */
58 .macro DMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]59 .word 0x41600bc1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]60 .endm
61
62 .macro EMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]63 .word 0x41600be1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]64 .endm
65
66 .macro DVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]67 .word 0x41600001 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]68 .endm
69
70 .macro EVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]71 .word 0x41600021 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]72 .endm
73
74 .macro MFTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]75 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]76 .endm
77
78 .macro MTTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]79 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]80 .endm
81
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]82#endif /* _ASM_ASMMACRO_H */