| Russell King | f6af5da | 2005-09-14 23:10:48 +0100 | [diff] [blame] | 1 | #ifndef __ASM_HARDWARE_TWD_H |
| 2 | #define __ASM_HARDWARE_TWD_H |
| 3 | |
| Catalin Marinas | 93c2904 | 2008-02-04 17:32:57 +0100 | [diff] [blame] | 4 | #define TWD_TIMER_LOAD 0x00 |
| Russell King | f6af5da | 2005-09-14 23:10:48 +0100 | [diff] [blame] | 5 | #define TWD_TIMER_COUNTER 0x04 |
| 6 | #define TWD_TIMER_CONTROL 0x08 |
| 7 | #define TWD_TIMER_INTSTAT 0x0C |
| 8 | |
| 9 | #define TWD_WDOG_LOAD 0x20 |
| 10 | #define TWD_WDOG_COUNTER 0x24 |
| 11 | #define TWD_WDOG_CONTROL 0x28 |
| 12 | #define TWD_WDOG_INTSTAT 0x2C |
| 13 | #define TWD_WDOG_RESETSTAT 0x30 |
| 14 | #define TWD_WDOG_DISABLE 0x34 |
| 15 | |
| Catalin Marinas | 93c2904 | 2008-02-04 17:32:57 +0100 | [diff] [blame] | 16 | #define TWD_TIMER_CONTROL_ENABLE (1 << 0) |
| 17 | #define TWD_TIMER_CONTROL_ONESHOT (0 << 1) |
| 18 | #define TWD_TIMER_CONTROL_PERIODIC (1 << 1) |
| 19 | #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) |
| 20 | |
| Russell King | f6af5da | 2005-09-14 23:10:48 +0100 | [diff] [blame] | 21 | #endif |