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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
Paul Mundte5723e02006-09-27 17:38:11 +090022 * SH7710
Linus Torvalds1da177e2005-04-16 15:20:36 -070023 * ---------------------------------------------------------------------------
24 */
25
Markus Brunner3ea6bc32007-08-20 08:59:33 +090026#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
27 !defined(CONFIG_CPU_SUBTYPE_SH7727)
Paul Mundtd95fb132006-09-27 13:30:08 +090028#define TMU_TOCR 0xfffffe90 /* Byte access */
29#endif
30
Markus Brunner3ea6bc32007-08-20 08:59:33 +090031#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7720)
Nobuhiro Iwamatsu75f016a2007-07-06 10:26:03 +090033#define TMU_012_TSTR 0xa412fe92 /* Byte access */
Linus Torvalds1da177e2005-04-16 15:20:36 -070034
35#define TMU0_TCOR 0xa412fe94 /* Long access */
36#define TMU0_TCNT 0xa412fe98 /* Long access */
37#define TMU0_TCR 0xa412fe9c /* Word access */
38
39#define TMU1_TCOR 0xa412fea0 /* Long access */
40#define TMU1_TCNT 0xa412fea4 /* Long access */
41#define TMU1_TCR 0xa412fea8 /* Word access */
42
43#define TMU2_TCOR 0xa412feac /* Long access */
44#define TMU2_TCNT 0xa412feb0 /* Long access */
45#define TMU2_TCR 0xa412feb4 /* Word access */
46
47#else
Nobuhiro Iwamatsu75f016a2007-07-06 10:26:03 +090048#define TMU_012_TSTR 0xfffffe92 /* Byte access */
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50#define TMU0_TCOR 0xfffffe94 /* Long access */
51#define TMU0_TCNT 0xfffffe98 /* Long access */
52#define TMU0_TCR 0xfffffe9c /* Word access */
53
54#define TMU1_TCOR 0xfffffea0 /* Long access */
55#define TMU1_TCNT 0xfffffea4 /* Long access */
56#define TMU1_TCR 0xfffffea8 /* Word access */
57
58#define TMU2_TCOR 0xfffffeac /* Long access */
59#define TMU2_TCNT 0xfffffeb0 /* Long access */
60#define TMU2_TCR 0xfffffeb4 /* Word access */
Markus Brunner3ea6bc32007-08-20 08:59:33 +090061#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
62 !defined(CONFIG_CPU_SUBTYPE_SH7727)
Linus Torvalds1da177e2005-04-16 15:20:36 -070063#define TMU2_TCPR2 0xfffffeb8 /* Long access */
64#endif
65#endif
66
67#endif /* __ASM_CPU_SH3_TIMER_H */
68