David S. Miller | 3eb8057 | 2009-01-21 21:30:23 -0800 | [diff] [blame^] | 1 | /* pcr.c: Generic sparc64 performance counter infrastructure. |
| 2 | * |
| 3 | * Copyright (C) 2009 David S. Miller (davem@davemloft.net) |
| 4 | */ |
| 5 | #include <linux/kernel.h> |
| 6 | #include <linux/module.h> |
| 7 | #include <linux/init.h> |
| 8 | #include <linux/irq.h> |
| 9 | |
| 10 | #include <asm/pil.h> |
| 11 | #include <asm/pcr.h> |
| 12 | |
| 13 | /* This code is shared between various users of the performance |
| 14 | * counters. Users will be oprofile, pseudo-NMI watchdog, and the |
| 15 | * perf_counter support layer. |
| 16 | */ |
| 17 | |
| 18 | /* Performance counter interrupts run unmasked at PIL level 15. |
| 19 | * Therefore we can't do things like wakeups and other work |
| 20 | * that expects IRQ disabling to be adhered to in locking etc. |
| 21 | * |
| 22 | * Therefore in such situations we defer the work by signalling |
| 23 | * a lower level cpu IRQ. |
| 24 | */ |
| 25 | void deferred_pcr_work_irq(int irq, struct pt_regs *regs) |
| 26 | { |
| 27 | clear_softint(1 << PIL_DEFERRED_PCR_WORK); |
| 28 | } |
| 29 | |
| 30 | void schedule_deferred_pcr_work(void) |
| 31 | { |
| 32 | set_softint(1 << PIL_DEFERRED_PCR_WORK); |
| 33 | } |
| 34 | |
| 35 | const struct pcr_ops *pcr_ops; |
| 36 | EXPORT_SYMBOL_GPL(pcr_ops); |
| 37 | |
| 38 | static u64 direct_pcr_read(void) |
| 39 | { |
| 40 | u64 val; |
| 41 | |
| 42 | read_pcr(val); |
| 43 | return val; |
| 44 | } |
| 45 | |
| 46 | static void direct_pcr_write(u64 val) |
| 47 | { |
| 48 | write_pcr(val); |
| 49 | } |
| 50 | |
| 51 | static const struct pcr_ops direct_pcr_ops = { |
| 52 | .read = direct_pcr_read, |
| 53 | .write = direct_pcr_write, |
| 54 | }; |
| 55 | |
| 56 | static void n2_pcr_write(u64 val) |
| 57 | { |
| 58 | unsigned long ret; |
| 59 | |
| 60 | ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val); |
| 61 | if (val != HV_EOK) |
| 62 | write_pcr(val); |
| 63 | } |
| 64 | |
| 65 | static const struct pcr_ops n2_pcr_ops = { |
| 66 | .read = direct_pcr_read, |
| 67 | .write = n2_pcr_write, |
| 68 | }; |
| 69 | |
| 70 | static unsigned long perf_hsvc_group; |
| 71 | static unsigned long perf_hsvc_major; |
| 72 | static unsigned long perf_hsvc_minor; |
| 73 | |
| 74 | static int __init register_perf_hsvc(void) |
| 75 | { |
| 76 | if (tlb_type == hypervisor) { |
| 77 | switch (sun4v_chip_type) { |
| 78 | case SUN4V_CHIP_NIAGARA1: |
| 79 | perf_hsvc_group = HV_GRP_NIAG_PERF; |
| 80 | break; |
| 81 | |
| 82 | case SUN4V_CHIP_NIAGARA2: |
| 83 | perf_hsvc_group = HV_GRP_N2_CPU; |
| 84 | break; |
| 85 | |
| 86 | default: |
| 87 | return -ENODEV; |
| 88 | } |
| 89 | |
| 90 | |
| 91 | perf_hsvc_major = 1; |
| 92 | perf_hsvc_minor = 0; |
| 93 | if (sun4v_hvapi_register(perf_hsvc_group, |
| 94 | perf_hsvc_major, |
| 95 | &perf_hsvc_minor)) { |
| 96 | printk("perfmon: Could not register hvapi.\n"); |
| 97 | return -ENODEV; |
| 98 | } |
| 99 | } |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static void __init unregister_perf_hsvc(void) |
| 104 | { |
| 105 | if (tlb_type != hypervisor) |
| 106 | return; |
| 107 | sun4v_hvapi_unregister(perf_hsvc_group); |
| 108 | } |
| 109 | |
| 110 | int __init pcr_arch_init(void) |
| 111 | { |
| 112 | int err = register_perf_hsvc(); |
| 113 | |
| 114 | if (err) |
| 115 | return err; |
| 116 | |
| 117 | switch (tlb_type) { |
| 118 | case hypervisor: |
| 119 | pcr_ops = &n2_pcr_ops; |
| 120 | break; |
| 121 | |
| 122 | case spitfire: |
| 123 | case cheetah: |
| 124 | case cheetah_plus: |
| 125 | pcr_ops = &direct_pcr_ops; |
| 126 | break; |
| 127 | |
| 128 | default: |
| 129 | err = -ENODEV; |
| 130 | goto out_unregister; |
| 131 | } |
| 132 | |
| 133 | return 0; |
| 134 | |
| 135 | out_unregister: |
| 136 | unregister_perf_hsvc(); |
| 137 | return err; |
| 138 | } |
| 139 | |
| 140 | arch_initcall(pcr_arch_init); |