blob: 12170cfcff4ef0c3f4fde707951d07ca007ef4ce [file] [log] [blame]
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -07001/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
Wey-Yi Guy8d801082010-03-17 13:34:36 -070029#include <linux/etherdevice.h>
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070030#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-io.h"
38#include "iwl-helpers.h"
39#include "iwl-agn-hw.h"
40#include "iwl-agn.h"
Johannes Berg1fa61b22010-04-28 08:44:52 -070041#include "iwl-sta.h"
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070042
43static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
44{
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47}
48
Wey-Yi Guy743e0152010-09-04 09:00:14 -070049static void iwlagn_set_tx_status(struct iwl_priv *priv,
50 struct ieee80211_tx_info *info,
51 struct iwl5000_tx_resp *tx_resp,
52 int txq_id, bool is_agg)
53{
54 u16 status = le16_to_cpu(tx_resp->status.status);
55
56 info->status.rates[0].count = tx_resp->failure_frame + 1;
57 if (is_agg)
58 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
59 info->flags |= iwl_tx_status_to_mac80211(status);
60 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
61 info);
62
63 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
64 "0x%x retries %d\n",
65 txq_id,
66 iwl_get_tx_fail_reason(status), status,
67 le32_to_cpu(tx_resp->rate_n_flags),
68 tx_resp->failure_frame);
69}
70
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070071static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
72 struct iwl_ht_agg *agg,
73 struct iwl5000_tx_resp *tx_resp,
74 int txq_id, u16 start_idx)
75{
76 u16 status;
77 struct agg_tx_status *frame_status = &tx_resp->status;
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070078 struct ieee80211_hdr *hdr = NULL;
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070079 int i, sh, idx;
80 u16 seq;
81
82 if (agg->wait_for_ba)
83 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
84
85 agg->frame_count = tx_resp->frame_count;
86 agg->start_idx = start_idx;
Wey-Yi Guy743e0152010-09-04 09:00:14 -070087 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070088 agg->bitmap = 0;
89
90 /* # frames attempted by Tx command */
91 if (agg->frame_count == 1) {
92 /* Only one frame was attempted; no block-ack will arrive */
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070093 idx = start_idx;
94
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -070095 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
96 agg->frame_count, agg->start_idx, idx);
Wey-Yi Guy743e0152010-09-04 09:00:14 -070097 iwlagn_set_tx_status(priv,
98 IEEE80211_SKB_CB(
99 priv->txq[txq_id].txb[idx].skb),
100 tx_resp, txq_id, true);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700101 agg->wait_for_ba = 0;
102 } else {
103 /* Two or more frames were attempted; expect block-ack */
104 u64 bitmap = 0;
Daniel Halperinf668da22010-05-25 10:22:49 -0700105
106 /*
107 * Start is the lowest frame sent. It may not be the first
108 * frame in the batch; we figure this out dynamically during
109 * the following loop.
110 */
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700111 int start = agg->start_idx;
112
113 /* Construct bit-map of pending frames within Tx window */
114 for (i = 0; i < agg->frame_count; i++) {
115 u16 sc;
116 status = le16_to_cpu(frame_status[i].status);
117 seq = le16_to_cpu(frame_status[i].sequence);
118 idx = SEQ_TO_INDEX(seq);
119 txq_id = SEQ_TO_QUEUE(seq);
120
121 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
122 AGG_TX_STATE_ABORT_MSK))
123 continue;
124
125 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
126 agg->frame_count, txq_id, idx);
127
128 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
129 if (!hdr) {
130 IWL_ERR(priv,
131 "BUG_ON idx doesn't point to valid skb"
132 " idx=%d, txq_id=%d\n", idx, txq_id);
133 return -1;
134 }
135
136 sc = le16_to_cpu(hdr->seq_ctrl);
137 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
138 IWL_ERR(priv,
139 "BUG_ON idx doesn't match seq control"
140 " idx=%d, seq_idx=%d, seq=%d\n",
141 idx, SEQ_TO_SN(sc),
142 hdr->seq_ctrl);
143 return -1;
144 }
145
146 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
147 i, idx, SEQ_TO_SN(sc));
148
Daniel Halperinf668da22010-05-25 10:22:49 -0700149 /*
150 * sh -> how many frames ahead of the starting frame is
151 * the current one?
152 *
153 * Note that all frames sent in the batch must be in a
154 * 64-frame window, so this number should be in [0,63].
155 * If outside of this window, then we've found a new
156 * "first" frame in the batch and need to change start.
157 */
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700158 sh = idx - start;
Daniel Halperinf668da22010-05-25 10:22:49 -0700159
160 /*
161 * If >= 64, out of window. start must be at the front
162 * of the circular buffer, idx must be near the end of
163 * the buffer, and idx is the new "first" frame. Shift
164 * the indices around.
165 */
166 if (sh >= 64) {
167 /* Shift bitmap by start - idx, wrapped */
168 sh = 0x100 - idx + start;
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700169 bitmap = bitmap << sh;
Daniel Halperinf668da22010-05-25 10:22:49 -0700170 /* Now idx is the new start so sh = 0 */
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700171 sh = 0;
172 start = idx;
Daniel Halperinf668da22010-05-25 10:22:49 -0700173 /*
174 * If <= -64 then wraps the 256-pkt circular buffer
175 * (e.g., start = 255 and idx = 0, sh should be 1)
176 */
177 } else if (sh <= -64) {
178 sh = 0x100 - start + idx;
179 /*
180 * If < 0 but > -64, out of window. idx is before start
181 * but not wrapped. Shift the indices around.
182 */
183 } else if (sh < 0) {
184 /* Shift by how far start is ahead of idx */
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700185 sh = start - idx;
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700186 bitmap = bitmap << sh;
Daniel Halperinf668da22010-05-25 10:22:49 -0700187 /* Now idx is the new start so sh = 0 */
188 start = idx;
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700189 sh = 0;
190 }
Daniel Halperinf668da22010-05-25 10:22:49 -0700191 /* Sequence number start + sh was sent in this batch */
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700192 bitmap |= 1ULL << sh;
193 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
194 start, (unsigned long long)bitmap);
195 }
196
Daniel Halperinf668da22010-05-25 10:22:49 -0700197 /*
198 * Store the bitmap and possibly the new start, if we wrapped
199 * the buffer above
200 */
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700201 agg->bitmap = bitmap;
202 agg->start_idx = start;
203 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
204 agg->frame_count, agg->start_idx,
205 (unsigned long long)agg->bitmap);
206
207 if (bitmap)
208 agg->wait_for_ba = 1;
209 }
210 return 0;
211}
212
Wey-Yi Guy04569cb2010-03-31 17:57:28 -0700213void iwl_check_abort_status(struct iwl_priv *priv,
214 u8 frame_count, u32 status)
215{
216 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
Wey-Yi Guy65550632010-06-24 13:18:35 -0700217 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
218 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
219 queue_work(priv->workqueue, &priv->tx_flush);
Wey-Yi Guy04569cb2010-03-31 17:57:28 -0700220 }
221}
222
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700223static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
224 struct iwl_rx_mem_buffer *rxb)
225{
226 struct iwl_rx_packet *pkt = rxb_addr(rxb);
227 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
228 int txq_id = SEQ_TO_QUEUE(sequence);
229 int index = SEQ_TO_INDEX(sequence);
230 struct iwl_tx_queue *txq = &priv->txq[txq_id];
231 struct ieee80211_tx_info *info;
232 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
233 u32 status = le16_to_cpu(tx_resp->status.status);
234 int tid;
235 int sta_id;
236 int freed;
Reinette Chatre9c5ac092010-05-05 02:26:06 -0700237 unsigned long flags;
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700238
239 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
240 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
241 "is out of range [0-%d] %d %d\n", txq_id,
242 index, txq->q.n_bd, txq->q.write_ptr,
243 txq->q.read_ptr);
244 return;
245 }
246
Johannes Bergff0d91c2010-05-17 02:37:34 -0700247 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700248 memset(&info->status, 0, sizeof(info->status));
249
250 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
251 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
252
Reinette Chatre9c5ac092010-05-05 02:26:06 -0700253 spin_lock_irqsave(&priv->sta_lock, flags);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700254 if (txq->sched_retry) {
255 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
Reinette Chatre9c5ac092010-05-05 02:26:06 -0700256 struct iwl_ht_agg *agg;
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700257
258 agg = &priv->stations[sta_id].tid[tid].agg;
Wey-Yi Guyc6c996b2010-08-23 07:57:06 -0700259 /*
260 * If the BT kill count is non-zero, we'll get this
261 * notification again.
262 */
263 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
264 priv->cfg->advanced_bt_coexist) {
265 IWL_WARN(priv, "receive reply tx with bt_kill\n");
266 }
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700267 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
268
269 /* check if BAR is needed */
270 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
271 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
272
273 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
274 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
275 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
276 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
277 scd_ssn , index, txq_id, txq->swq_id);
278
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700279 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700280 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
281
282 if (priv->mac80211_registered &&
283 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
284 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
285 if (agg->state == IWL_AGG_OFF)
286 iwl_wake_queue(priv, txq_id);
287 else
288 iwl_wake_queue(priv, txq->swq_id);
289 }
290 }
291 } else {
292 BUG_ON(txq_id != txq->swq_id);
Wey-Yi Guy743e0152010-09-04 09:00:14 -0700293 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700294 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700295 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
296
297 if (priv->mac80211_registered &&
298 (iwl_queue_space(&txq->q) > txq->q.low_mark))
299 iwl_wake_queue(priv, txq_id);
300 }
301
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700302 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700303
Wey-Yi Guy04569cb2010-03-31 17:57:28 -0700304 iwl_check_abort_status(priv, tx_resp->frame_count, status);
Reinette Chatre9c5ac092010-05-05 02:26:06 -0700305 spin_unlock_irqrestore(&priv->sta_lock, flags);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700306}
307
308void iwlagn_rx_handler_setup(struct iwl_priv *priv)
309{
310 /* init calibration handlers */
311 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
312 iwlagn_rx_calib_result;
313 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
314 iwlagn_rx_calib_complete;
315 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
316}
317
318void iwlagn_setup_deferred_work(struct iwl_priv *priv)
319{
320 /* in agn, the tx power calibration is done in uCode */
321 priv->disable_tx_power_cal = 1;
322}
323
324int iwlagn_hw_valid_rtc_data_addr(u32 addr)
325{
326 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
327 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
328}
329
330int iwlagn_send_tx_power(struct iwl_priv *priv)
331{
332 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
333 u8 tx_ant_cfg_cmd;
334
335 /* half dBm need to multiply */
336 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
337
338 if (priv->tx_power_lmt_in_half_dbm &&
339 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
340 /*
341 * For the newer devices which using enhanced/extend tx power
342 * table in EEPROM, the format is in half dBm. driver need to
343 * convert to dBm format before report to mac80211.
344 * By doing so, there is a possibility of 1/2 dBm resolution
345 * lost. driver will perform "round-up" operation before
346 * reporting, but it will cause 1/2 dBm tx power over the
347 * regulatory limit. Perform the checking here, if the
348 * "tx_power_user_lmt" is higher than EEPROM value (in
349 * half-dBm format), lower the tx power based on EEPROM
350 */
351 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
352 }
353 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
354 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
355
356 if (IWL_UCODE_API(priv->ucode_ver) == 1)
357 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
358 else
359 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
360
361 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
362 sizeof(tx_power_cmd), &tx_power_cmd,
363 NULL);
364}
365
366void iwlagn_temperature(struct iwl_priv *priv)
367{
368 /* store temperature from statistics (in Celsius) */
Wey-Yi Guyf3aebee2010-06-14 17:09:54 -0700369 priv->temperature =
Wey-Yi Guy325322e2010-07-14 08:07:27 -0700370 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700371 iwl_tt_handler(priv);
372}
373
374u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
375{
376 struct iwl_eeprom_calib_hdr {
377 u8 version;
378 u8 pa_type;
379 u16 voltage;
380 } *hdr;
381
382 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
Wey-Yi Guy7944f8e2010-04-06 21:10:33 -0700383 EEPROM_CALIB_ALL);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700384 return hdr->version;
385
386}
387
388/*
389 * EEPROM
390 */
391static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
392{
393 u16 offset = 0;
394
395 if ((address & INDIRECT_ADDRESS) == 0)
396 return address;
397
398 switch (address & INDIRECT_TYPE_MSK) {
399 case INDIRECT_HOST:
Wey-Yi Guy7944f8e2010-04-06 21:10:33 -0700400 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700401 break;
402 case INDIRECT_GENERAL:
Wey-Yi Guy7944f8e2010-04-06 21:10:33 -0700403 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700404 break;
405 case INDIRECT_REGULATORY:
Wey-Yi Guy7944f8e2010-04-06 21:10:33 -0700406 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700407 break;
408 case INDIRECT_CALIBRATION:
Wey-Yi Guy7944f8e2010-04-06 21:10:33 -0700409 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700410 break;
411 case INDIRECT_PROCESS_ADJST:
Wey-Yi Guy7944f8e2010-04-06 21:10:33 -0700412 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700413 break;
414 case INDIRECT_OTHERS:
Wey-Yi Guy7944f8e2010-04-06 21:10:33 -0700415 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
Wey-Yi Guye04ed0a2010-03-16 17:47:58 -0700416 break;
417 default:
418 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
419 address & INDIRECT_TYPE_MSK);
420 break;
421 }
422
423 /* translate the offset from words to byte */
424 return (address & ADDRESS_MSK) + (offset << 1);
425}
426
427const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
428 size_t offset)
429{
430 u32 address = eeprom_indirect_address(priv, offset);
431 BUG_ON(address >= priv->cfg->eeprom_size);
432 return &priv->eeprom[address];
433}
Wey-Yi Guy348ee7c2010-03-16 12:37:27 -0700434
435struct iwl_mod_params iwlagn_mod_params = {
436 .amsdu_size_8K = 1,
437 .restart_fw = 1,
438 /* the rest are 0 by default */
439};
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700440
441void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
442{
443 unsigned long flags;
444 int i;
445 spin_lock_irqsave(&rxq->lock, flags);
446 INIT_LIST_HEAD(&rxq->rx_free);
447 INIT_LIST_HEAD(&rxq->rx_used);
448 /* Fill the rx_used queue with _all_ of the Rx buffers */
449 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
450 /* In the reset function, these buffers may have been allocated
451 * to an SKB, so we need to unmap and free potential storage */
452 if (rxq->pool[i].page != NULL) {
453 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
454 PAGE_SIZE << priv->hw_params.rx_page_order,
455 PCI_DMA_FROMDEVICE);
456 __iwl_free_pages(priv, rxq->pool[i].page);
457 rxq->pool[i].page = NULL;
458 }
459 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
460 }
461
Zhu Yi6aac74b2010-03-22 19:33:41 -0700462 for (i = 0; i < RX_QUEUE_SIZE; i++)
463 rxq->queue[i] = NULL;
464
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700465 /* Set us so that we have processed and used all buffers, but have
466 * not restocked the Rx queue with fresh buffers */
467 rxq->read = rxq->write = 0;
468 rxq->write_actual = 0;
469 rxq->free_count = 0;
470 spin_unlock_irqrestore(&rxq->lock, flags);
471}
472
473int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
474{
475 u32 rb_size;
476 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
477 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
478
479 if (!priv->cfg->use_isr_legacy)
480 rb_timeout = RX_RB_TIMEOUT;
481
482 if (priv->cfg->mod_params->amsdu_size_8K)
483 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
484 else
485 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
486
487 /* Stop Rx DMA */
488 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
489
490 /* Reset driver's Rx queue write index */
491 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
492
493 /* Tell device where to find RBD circular buffer in DRAM */
494 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
Emmanuel Grumbachd5b25c92010-06-07 13:21:46 -0700495 (u32)(rxq->bd_dma >> 8));
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700496
497 /* Tell device where in DRAM to update its Rx status */
498 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
499 rxq->rb_stts_dma >> 4);
500
501 /* Enable Rx DMA
502 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
503 * the credit mechanism in 5000 HW RX FIFO
504 * Direct rx interrupts to hosts
505 * Rx buffer size 4 or 8k
506 * RB timeout 0x10
507 * 256 RBDs
508 */
509 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
510 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
511 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
512 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
513 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
514 rb_size|
515 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
516 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
517
518 /* Set interrupt coalescing timer to default (2048 usecs) */
519 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
520
521 return 0;
522}
523
524int iwlagn_hw_nic_init(struct iwl_priv *priv)
525{
526 unsigned long flags;
527 struct iwl_rx_queue *rxq = &priv->rxq;
528 int ret;
529
530 /* nic_init */
531 spin_lock_irqsave(&priv->lock, flags);
532 priv->cfg->ops->lib->apm_ops.init(priv);
533
534 /* Set interrupt coalescing calibration timer to default (512 usecs) */
535 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
536
537 spin_unlock_irqrestore(&priv->lock, flags);
538
539 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
540
541 priv->cfg->ops->lib->apm_ops.config(priv);
542
543 /* Allocate the RX queue, or reset if it is already allocated */
544 if (!rxq->bd) {
545 ret = iwl_rx_queue_alloc(priv);
546 if (ret) {
547 IWL_ERR(priv, "Unable to initialize Rx queue\n");
548 return -ENOMEM;
549 }
550 } else
551 iwlagn_rx_queue_reset(priv, rxq);
552
Wey-Yi Guy54b81552010-03-17 13:34:35 -0700553 iwlagn_rx_replenish(priv);
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700554
555 iwlagn_rx_init(priv, rxq);
556
557 spin_lock_irqsave(&priv->lock, flags);
558
559 rxq->need_update = 1;
560 iwl_rx_queue_update_write_ptr(priv, rxq);
561
562 spin_unlock_irqrestore(&priv->lock, flags);
563
Zhu Yi470058e2010-04-02 13:38:54 -0700564 /* Allocate or reset and init all Tx and Command queues */
565 if (!priv->txq) {
566 ret = iwlagn_txq_ctx_alloc(priv);
567 if (ret)
568 return ret;
569 } else
570 iwlagn_txq_ctx_reset(priv);
Wey-Yi Guy74bcdb32010-03-17 13:34:34 -0700571
572 set_bit(STATUS_INIT, &priv->status);
573
574 return 0;
575}
Wey-Yi Guy54b81552010-03-17 13:34:35 -0700576
577/**
578 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
579 */
580static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
581 dma_addr_t dma_addr)
582{
583 return cpu_to_le32((u32)(dma_addr >> 8));
584}
585
586/**
587 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
588 *
589 * If there are slots in the RX queue that need to be restocked,
590 * and we have free pre-allocated buffers, fill the ranks as much
591 * as we can, pulling from rx_free.
592 *
593 * This moves the 'write' index forward to catch up with 'processed', and
594 * also updates the memory address in the firmware to reference the new
595 * target buffer.
596 */
597void iwlagn_rx_queue_restock(struct iwl_priv *priv)
598{
599 struct iwl_rx_queue *rxq = &priv->rxq;
600 struct list_head *element;
601 struct iwl_rx_mem_buffer *rxb;
602 unsigned long flags;
Wey-Yi Guy54b81552010-03-17 13:34:35 -0700603
604 spin_lock_irqsave(&rxq->lock, flags);
Wey-Yi Guy54b81552010-03-17 13:34:35 -0700605 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
Zhu Yi6aac74b2010-03-22 19:33:41 -0700606 /* The overwritten rxb must be a used one */
607 rxb = rxq->queue[rxq->write];
608 BUG_ON(rxb && rxb->page);
609
Wey-Yi Guy54b81552010-03-17 13:34:35 -0700610 /* Get next free Rx buffer, remove from free list */
611 element = rxq->rx_free.next;
612 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
613 list_del(element);
614
615 /* Point to Rx buffer via next RBD in circular buffer */
616 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
617 rxb->page_dma);
618 rxq->queue[rxq->write] = rxb;
619 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
620 rxq->free_count--;
621 }
622 spin_unlock_irqrestore(&rxq->lock, flags);
623 /* If the pre-allocated buffer pool is dropping low, schedule to
624 * refill it */
625 if (rxq->free_count <= RX_LOW_WATERMARK)
626 queue_work(priv->workqueue, &priv->rx_replenish);
627
628
629 /* If we've added more space for the firmware to place data, tell it.
630 * Increment device's write pointer in multiples of 8. */
631 if (rxq->write_actual != (rxq->write & ~0x7)) {
632 spin_lock_irqsave(&rxq->lock, flags);
633 rxq->need_update = 1;
634 spin_unlock_irqrestore(&rxq->lock, flags);
635 iwl_rx_queue_update_write_ptr(priv, rxq);
636 }
637}
638
639/**
640 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
641 *
642 * When moving to rx_free an SKB is allocated for the slot.
643 *
644 * Also restock the Rx queue via iwl_rx_queue_restock.
645 * This is called as a scheduled work item (except for during initialization)
646 */
647void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
648{
649 struct iwl_rx_queue *rxq = &priv->rxq;
650 struct list_head *element;
651 struct iwl_rx_mem_buffer *rxb;
652 struct page *page;
653 unsigned long flags;
654 gfp_t gfp_mask = priority;
655
656 while (1) {
657 spin_lock_irqsave(&rxq->lock, flags);
658 if (list_empty(&rxq->rx_used)) {
659 spin_unlock_irqrestore(&rxq->lock, flags);
660 return;
661 }
662 spin_unlock_irqrestore(&rxq->lock, flags);
663
664 if (rxq->free_count > RX_LOW_WATERMARK)
665 gfp_mask |= __GFP_NOWARN;
666
667 if (priv->hw_params.rx_page_order > 0)
668 gfp_mask |= __GFP_COMP;
669
670 /* Alloc a new receive buffer */
671 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
672 if (!page) {
673 if (net_ratelimit())
674 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
675 "order: %d\n",
676 priv->hw_params.rx_page_order);
677
678 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
679 net_ratelimit())
680 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
681 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
682 rxq->free_count);
683 /* We don't reschedule replenish work here -- we will
684 * call the restock method and if it still needs
685 * more buffers it will schedule replenish */
686 return;
687 }
688
689 spin_lock_irqsave(&rxq->lock, flags);
690
691 if (list_empty(&rxq->rx_used)) {
692 spin_unlock_irqrestore(&rxq->lock, flags);
693 __free_pages(page, priv->hw_params.rx_page_order);
694 return;
695 }
696 element = rxq->rx_used.next;
697 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
698 list_del(element);
699
700 spin_unlock_irqrestore(&rxq->lock, flags);
701
Zhu Yi6aac74b2010-03-22 19:33:41 -0700702 BUG_ON(rxb->page);
Wey-Yi Guy54b81552010-03-17 13:34:35 -0700703 rxb->page = page;
704 /* Get physical address of the RB */
705 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
706 PAGE_SIZE << priv->hw_params.rx_page_order,
707 PCI_DMA_FROMDEVICE);
708 /* dma address must be no more than 36 bits */
709 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
710 /* and also 256 byte aligned! */
711 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
712
713 spin_lock_irqsave(&rxq->lock, flags);
714
715 list_add_tail(&rxb->list, &rxq->rx_free);
716 rxq->free_count++;
717 priv->alloc_rxb_page++;
718
719 spin_unlock_irqrestore(&rxq->lock, flags);
720 }
721}
722
723void iwlagn_rx_replenish(struct iwl_priv *priv)
724{
725 unsigned long flags;
726
727 iwlagn_rx_allocate(priv, GFP_KERNEL);
728
729 spin_lock_irqsave(&priv->lock, flags);
730 iwlagn_rx_queue_restock(priv);
731 spin_unlock_irqrestore(&priv->lock, flags);
732}
733
734void iwlagn_rx_replenish_now(struct iwl_priv *priv)
735{
736 iwlagn_rx_allocate(priv, GFP_ATOMIC);
737
738 iwlagn_rx_queue_restock(priv);
739}
740
741/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
742 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
743 * This free routine walks the list of POOL entries and if SKB is set to
744 * non NULL it is unmapped and freed
745 */
746void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
747{
748 int i;
749 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
750 if (rxq->pool[i].page != NULL) {
751 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
752 PAGE_SIZE << priv->hw_params.rx_page_order,
753 PCI_DMA_FROMDEVICE);
754 __iwl_free_pages(priv, rxq->pool[i].page);
755 rxq->pool[i].page = NULL;
756 }
757 }
758
759 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
Emmanuel Grumbachd5b25c92010-06-07 13:21:46 -0700760 rxq->bd_dma);
Wey-Yi Guy54b81552010-03-17 13:34:35 -0700761 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
762 rxq->rb_stts, rxq->rb_stts_dma);
763 rxq->bd = NULL;
764 rxq->rb_stts = NULL;
765}
766
767int iwlagn_rxq_stop(struct iwl_priv *priv)
768{
769
770 /* stop Rx DMA */
771 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
772 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
773 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
774
775 return 0;
776}
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700777
778int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
779{
780 int idx = 0;
781 int band_offset = 0;
782
783 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
784 if (rate_n_flags & RATE_MCS_HT_MSK) {
785 idx = (rate_n_flags & 0xff);
786 return idx;
787 /* Legacy rate format, search for match in table */
788 } else {
789 if (band == IEEE80211_BAND_5GHZ)
790 band_offset = IWL_FIRST_OFDM_RATE;
791 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
792 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
793 return idx - band_offset;
794 }
795
796 return -1;
797}
798
799/* Calc max signal level (dBm) among 3 possible receivers */
800static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
801 struct iwl_rx_phy_res *rx_resp)
802{
803 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
804}
805
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700806static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
807{
808 u32 decrypt_out = 0;
809
810 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
811 RX_RES_STATUS_STATION_FOUND)
812 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
813 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
814
815 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
816
817 /* packet was not encrypted */
818 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
819 RX_RES_STATUS_SEC_TYPE_NONE)
820 return decrypt_out;
821
822 /* packet was encrypted with unknown alg */
823 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
824 RX_RES_STATUS_SEC_TYPE_ERR)
825 return decrypt_out;
826
827 /* decryption was not done in HW */
828 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
829 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
830 return decrypt_out;
831
832 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
833
834 case RX_RES_STATUS_SEC_TYPE_CCMP:
835 /* alg is CCM: check MIC only */
836 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
837 /* Bad MIC */
838 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
839 else
840 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
841
842 break;
843
844 case RX_RES_STATUS_SEC_TYPE_TKIP:
845 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
846 /* Bad TTAK */
847 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
848 break;
849 }
850 /* fall through if TTAK OK */
851 default:
852 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
853 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
854 else
855 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
856 break;
Joe Perchesee289b62010-05-17 22:47:34 -0700857 }
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700858
859 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
860 decrypt_in, decrypt_out);
861
862 return decrypt_out;
863}
864
865static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
866 struct ieee80211_hdr *hdr,
867 u16 len,
868 u32 ampdu_status,
869 struct iwl_rx_mem_buffer *rxb,
870 struct ieee80211_rx_status *stats)
871{
872 struct sk_buff *skb;
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700873 __le16 fc = hdr->frame_control;
874
875 /* We only process data packets if the interface is open */
876 if (unlikely(!priv->is_open)) {
877 IWL_DEBUG_DROP_LIMIT(priv,
878 "Dropping packet while interface is not open.\n");
879 return;
880 }
881
882 /* In case of HW accelerated crypto and bad decryption, drop */
883 if (!priv->cfg->mod_params->sw_crypto &&
884 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
885 return;
886
Zhu Yiecdf94b2010-03-29 16:42:26 +0800887 skb = dev_alloc_skb(128);
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700888 if (!skb) {
Zhu Yiecdf94b2010-03-29 16:42:26 +0800889 IWL_ERR(priv, "dev_alloc_skb failed\n");
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700890 return;
891 }
892
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700893 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
894
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700895 iwl_update_stats(priv, false, fc, len);
896 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
897
898 ieee80211_rx(priv->hw, skb);
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700899 priv->alloc_rxb_page--;
900 rxb->page = NULL;
901}
902
903/* Called for REPLY_RX (legacy ABG frames), or
904 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
905void iwlagn_rx_reply_rx(struct iwl_priv *priv,
906 struct iwl_rx_mem_buffer *rxb)
907{
908 struct ieee80211_hdr *header;
909 struct ieee80211_rx_status rx_status;
910 struct iwl_rx_packet *pkt = rxb_addr(rxb);
911 struct iwl_rx_phy_res *phy_res;
912 __le32 rx_pkt_status;
Emmanuel Grumbach2fb291e2010-06-07 13:21:47 -0700913 struct iwl_rx_mpdu_res_start *amsdu;
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700914 u32 len;
915 u32 ampdu_status;
916 u32 rate_n_flags;
917
918 /**
919 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
920 * REPLY_RX: physical layer info is in this buffer
921 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
922 * command and cached in priv->last_phy_res
923 *
924 * Here we set up local variables depending on which command is
925 * received.
926 */
927 if (pkt->hdr.cmd == REPLY_RX) {
928 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
929 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
930 + phy_res->cfg_phy_cnt);
931
932 len = le16_to_cpu(phy_res->byte_count);
933 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
934 phy_res->cfg_phy_cnt + len);
935 ampdu_status = le32_to_cpu(rx_pkt_status);
936 } else {
Johannes Berg05d57522010-03-31 08:59:17 -0700937 if (!priv->_agn.last_phy_res_valid) {
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700938 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
939 return;
940 }
Johannes Berg05d57522010-03-31 08:59:17 -0700941 phy_res = &priv->_agn.last_phy_res;
Emmanuel Grumbach2fb291e2010-06-07 13:21:47 -0700942 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700943 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
944 len = le16_to_cpu(amsdu->byte_count);
945 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
946 ampdu_status = iwlagn_translate_rx_status(priv,
947 le32_to_cpu(rx_pkt_status));
948 }
949
950 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
951 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
952 phy_res->cfg_phy_cnt);
953 return;
954 }
955
956 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
957 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
958 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
959 le32_to_cpu(rx_pkt_status));
960 return;
961 }
962
963 /* This will be used in several places later */
964 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
965
966 /* rx_status carries information about the packet to mac80211 */
967 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
968 rx_status.freq =
969 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
970 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
971 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
972 rx_status.rate_idx =
973 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
974 rx_status.flag = 0;
975
976 /* TSF isn't reliable. In order to allow smooth user experience,
977 * this W/A doesn't propagate it to the mac80211 */
978 /*rx_status.flag |= RX_FLAG_TSFT;*/
979
980 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
981
982 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
983 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
984
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700985 iwl_dbg_log_rx_data_frame(priv, len, header);
Johannes Berged1b6e92010-03-18 09:58:27 -0700986 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
987 rx_status.signal, (unsigned long long)rx_status.mactime);
Wey-Yi Guy8d801082010-03-17 13:34:36 -0700988
989 /*
990 * "antenna number"
991 *
992 * It seems that the antenna field in the phy flags value
993 * is actually a bit field. This is undefined by radiotap,
994 * it wants an actual antenna number but I always get "7"
995 * for most legacy frames I receive indicating that the
996 * same frame was received on all three RX chains.
997 *
998 * I think this field should be removed in favor of a
999 * new 802.11n radiotap field "RX chains" that is defined
1000 * as a bitmask.
1001 */
1002 rx_status.antenna =
1003 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1004 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1005
1006 /* set the preamble flag if appropriate */
1007 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1008 rx_status.flag |= RX_FLAG_SHORTPRE;
1009
1010 /* Set up the HT phy flags */
1011 if (rate_n_flags & RATE_MCS_HT_MSK)
1012 rx_status.flag |= RX_FLAG_HT;
1013 if (rate_n_flags & RATE_MCS_HT40_MSK)
1014 rx_status.flag |= RX_FLAG_40MHZ;
1015 if (rate_n_flags & RATE_MCS_SGI_MSK)
1016 rx_status.flag |= RX_FLAG_SHORT_GI;
1017
1018 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1019 rxb, &rx_status);
1020}
1021
1022/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1023 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1024void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
Johannes Berg05d57522010-03-31 08:59:17 -07001025 struct iwl_rx_mem_buffer *rxb)
Wey-Yi Guy8d801082010-03-17 13:34:36 -07001026{
1027 struct iwl_rx_packet *pkt = rxb_addr(rxb);
Johannes Berg05d57522010-03-31 08:59:17 -07001028 priv->_agn.last_phy_res_valid = true;
1029 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
Wey-Yi Guy8d801082010-03-17 13:34:36 -07001030 sizeof(struct iwl_rx_phy_res));
1031}
Johannes Bergb6e4c552010-04-06 04:12:42 -07001032
1033static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
Johannes Berg1dda6d22010-04-29 04:43:06 -07001034 struct ieee80211_vif *vif,
1035 enum ieee80211_band band,
1036 struct iwl_scan_channel *scan_ch)
Johannes Bergb6e4c552010-04-06 04:12:42 -07001037{
1038 const struct ieee80211_supported_band *sband;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001039 u16 passive_dwell = 0;
1040 u16 active_dwell = 0;
Abhijeet Kolekar14023642010-06-02 21:15:10 -07001041 int added = 0;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001042 u16 channel = 0;
1043
1044 sband = iwl_get_hw_mode(priv, band);
1045 if (!sband) {
1046 IWL_ERR(priv, "invalid band\n");
1047 return added;
1048 }
1049
1050 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
Johannes Berg1dda6d22010-04-29 04:43:06 -07001051 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
Johannes Bergb6e4c552010-04-06 04:12:42 -07001052
1053 if (passive_dwell <= active_dwell)
1054 passive_dwell = active_dwell + 1;
1055
Abhijeet Kolekar14023642010-06-02 21:15:10 -07001056 channel = iwl_get_single_channel_number(priv, band);
Johannes Bergb6e4c552010-04-06 04:12:42 -07001057 if (channel) {
1058 scan_ch->channel = cpu_to_le16(channel);
1059 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1060 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1061 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1062 /* Set txpower levels to defaults */
1063 scan_ch->dsp_atten = 110;
1064 if (band == IEEE80211_BAND_5GHZ)
1065 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1066 else
1067 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1068 added++;
1069 } else
1070 IWL_ERR(priv, "no valid channel found\n");
1071 return added;
1072}
1073
1074static int iwl_get_channels_for_scan(struct iwl_priv *priv,
Johannes Berg1dda6d22010-04-29 04:43:06 -07001075 struct ieee80211_vif *vif,
Johannes Bergb6e4c552010-04-06 04:12:42 -07001076 enum ieee80211_band band,
1077 u8 is_active, u8 n_probes,
1078 struct iwl_scan_channel *scan_ch)
1079{
1080 struct ieee80211_channel *chan;
1081 const struct ieee80211_supported_band *sband;
1082 const struct iwl_channel_info *ch_info;
1083 u16 passive_dwell = 0;
1084 u16 active_dwell = 0;
1085 int added, i;
1086 u16 channel;
1087
1088 sband = iwl_get_hw_mode(priv, band);
1089 if (!sband)
1090 return 0;
1091
1092 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
Johannes Berg1dda6d22010-04-29 04:43:06 -07001093 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
Johannes Bergb6e4c552010-04-06 04:12:42 -07001094
1095 if (passive_dwell <= active_dwell)
1096 passive_dwell = active_dwell + 1;
1097
1098 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1099 chan = priv->scan_request->channels[i];
1100
1101 if (chan->band != band)
1102 continue;
1103
Shanyu Zhao81e95432010-07-28 13:40:27 -07001104 channel = chan->hw_value;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001105 scan_ch->channel = cpu_to_le16(channel);
1106
1107 ch_info = iwl_get_channel_info(priv, band, channel);
1108 if (!is_channel_valid(ch_info)) {
1109 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1110 channel);
1111 continue;
1112 }
1113
1114 if (!is_active || is_channel_passive(ch_info) ||
1115 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1116 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1117 else
1118 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1119
1120 if (n_probes)
1121 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1122
1123 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1124 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1125
1126 /* Set txpower levels to defaults */
1127 scan_ch->dsp_atten = 110;
1128
1129 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1130 * power level:
1131 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1132 */
1133 if (band == IEEE80211_BAND_5GHZ)
1134 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1135 else
1136 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1137
1138 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1139 channel, le32_to_cpu(scan_ch->type),
1140 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1141 "ACTIVE" : "PASSIVE",
1142 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1143 active_dwell : passive_dwell);
1144
1145 scan_ch++;
1146 added++;
1147 }
1148
1149 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1150 return added;
1151}
1152
Johannes Berg3eecce52010-09-13 14:46:33 +02001153int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
Johannes Bergb6e4c552010-04-06 04:12:42 -07001154{
1155 struct iwl_host_cmd cmd = {
1156 .id = REPLY_SCAN_CMD,
1157 .len = sizeof(struct iwl_scan_cmd),
1158 .flags = CMD_SIZE_HUGE,
1159 };
1160 struct iwl_scan_cmd *scan;
Johannes Berga194e322010-08-27 08:53:46 -07001161 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
Johannes Bergb6e4c552010-04-06 04:12:42 -07001162 u32 rate_flags = 0;
1163 u16 cmd_len;
1164 u16 rx_chain = 0;
1165 enum ieee80211_band band;
1166 u8 n_probes = 0;
1167 u8 rx_ant = priv->hw_params.valid_rx_ant;
1168 u8 rate;
1169 bool is_active = false;
1170 int chan_mod;
1171 u8 active_chains;
Johannes Berg0e1654f2010-05-18 02:48:36 -07001172 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
Johannes Berg3eecce52010-09-13 14:46:33 +02001173 int ret;
1174
1175 lockdep_assert_held(&priv->mutex);
Johannes Bergb6e4c552010-04-06 04:12:42 -07001176
Johannes Berga194e322010-08-27 08:53:46 -07001177 if (vif)
1178 ctx = iwl_rxon_ctx_from_vif(vif);
1179
Johannes Bergb6e4c552010-04-06 04:12:42 -07001180 if (!priv->scan_cmd) {
1181 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1182 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1183 if (!priv->scan_cmd) {
1184 IWL_DEBUG_SCAN(priv,
1185 "fail to allocate memory for scan\n");
Johannes Berg3eecce52010-09-13 14:46:33 +02001186 return -ENOMEM;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001187 }
1188 }
1189 scan = priv->scan_cmd;
1190 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1191
1192 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1193 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1194
Johannes Berg246ed352010-08-23 10:46:32 +02001195 if (iwl_is_any_associated(priv)) {
Johannes Bergb6e4c552010-04-06 04:12:42 -07001196 u16 interval = 0;
1197 u32 extra;
1198 u32 suspend_time = 100;
1199 u32 scan_suspend_time = 100;
1200 unsigned long flags;
1201
1202 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1203 spin_lock_irqsave(&priv->lock, flags);
John W. Linvillea6e492b2010-07-22 15:24:56 -04001204 if (priv->is_internal_short_scan)
1205 interval = 0;
1206 else
1207 interval = vif->bss_conf.beacon_int;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001208 spin_unlock_irqrestore(&priv->lock, flags);
1209
1210 scan->suspend_time = 0;
1211 scan->max_out_time = cpu_to_le32(200 * 1024);
1212 if (!interval)
1213 interval = suspend_time;
1214
1215 extra = (suspend_time / interval) << 22;
1216 scan_suspend_time = (extra |
1217 ((suspend_time % interval) * 1024));
1218 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1219 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1220 scan_suspend_time, interval);
1221 }
1222
1223 if (priv->is_internal_short_scan) {
1224 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1225 } else if (priv->scan_request->n_ssids) {
1226 int i, p = 0;
1227 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1228 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1229 /* always does wildcard anyway */
1230 if (!priv->scan_request->ssids[i].ssid_len)
1231 continue;
1232 scan->direct_scan[p].id = WLAN_EID_SSID;
1233 scan->direct_scan[p].len =
1234 priv->scan_request->ssids[i].ssid_len;
1235 memcpy(scan->direct_scan[p].ssid,
1236 priv->scan_request->ssids[i].ssid,
1237 priv->scan_request->ssids[i].ssid_len);
1238 n_probes++;
1239 p++;
1240 }
1241 is_active = true;
1242 } else
1243 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1244
1245 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
Johannes Berga194e322010-08-27 08:53:46 -07001246 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001247 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1248
1249 switch (priv->scan_band) {
1250 case IEEE80211_BAND_2GHZ:
1251 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
Johannes Berg246ed352010-08-23 10:46:32 +02001252 chan_mod = le32_to_cpu(
1253 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1254 RXON_FLG_CHANNEL_MODE_MSK)
Johannes Bergb6e4c552010-04-06 04:12:42 -07001255 >> RXON_FLG_CHANNEL_MODE_POS;
1256 if (chan_mod == CHANNEL_MODE_PURE_40) {
1257 rate = IWL_RATE_6M_PLCP;
1258 } else {
1259 rate = IWL_RATE_1M_PLCP;
1260 rate_flags = RATE_MCS_CCK_MSK;
1261 }
Johannes Bergd44ae692010-08-23 07:56:56 -07001262 /*
1263 * Internal scans are passive, so we can indiscriminately set
1264 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1265 */
1266 if (priv->cfg->advanced_bt_coexist)
1267 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
Reinette Chatread41ee32010-04-30 15:13:00 -07001268 scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001269 break;
1270 case IEEE80211_BAND_5GHZ:
1271 rate = IWL_RATE_6M_PLCP;
1272 /*
Reinette Chatread41ee32010-04-30 15:13:00 -07001273 * If active scanning is requested but a certain channel is
1274 * marked passive, we can do active scanning if we detect
1275 * transmissions.
1276 *
1277 * There is an issue with some firmware versions that triggers
1278 * a sysassert on a "good CRC threshold" of zero (== disabled),
1279 * on a radar channel even though this means that we should NOT
1280 * send probes.
1281 *
1282 * The "good CRC threshold" is the number of frames that we
1283 * need to receive during our dwell time on a channel before
1284 * sending out probes -- setting this to a huge value will
1285 * mean we never reach it, but at the same time work around
1286 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1287 * here instead of IWL_GOOD_CRC_TH_DISABLED.
Johannes Bergb6e4c552010-04-06 04:12:42 -07001288 */
Reinette Chatread41ee32010-04-30 15:13:00 -07001289 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1290 IWL_GOOD_CRC_TH_NEVER;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001291 break;
1292 default:
Johannes Berg3eecce52010-09-13 14:46:33 +02001293 IWL_WARN(priv, "Invalid scan band\n");
1294 return -EIO;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001295 }
1296
1297 band = priv->scan_band;
1298
Johannes Berg0e1654f2010-05-18 02:48:36 -07001299 if (priv->cfg->scan_rx_antennas[band])
1300 rx_ant = priv->cfg->scan_rx_antennas[band];
Johannes Berge7cb4952010-04-13 01:04:35 -07001301
Johannes Berg0e1654f2010-05-18 02:48:36 -07001302 if (priv->cfg->scan_tx_antennas[band])
1303 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1304
Wey-Yi Guybee008b2010-08-23 07:57:04 -07001305 if (priv->cfg->advanced_bt_coexist && priv->bt_full_concurrent) {
1306 /* operated as 1x1 in full concurrency mode */
1307 scan_tx_antennas =
1308 first_antenna(priv->cfg->scan_tx_antennas[band]);
1309 }
1310
Johannes Berg0e1654f2010-05-18 02:48:36 -07001311 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1312 scan_tx_antennas);
Johannes Bergb6e4c552010-04-06 04:12:42 -07001313 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1314 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1315
1316 /* In power save mode use one chain, otherwise use all chains */
1317 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1318 /* rx_ant has been set to all valid chains previously */
1319 active_chains = rx_ant &
1320 ((u8)(priv->chain_noise_data.active_chains));
1321 if (!active_chains)
1322 active_chains = rx_ant;
1323
1324 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1325 priv->chain_noise_data.active_chains);
1326
1327 rx_ant = first_antenna(active_chains);
1328 }
Wey-Yi Guybee008b2010-08-23 07:57:04 -07001329 if (priv->cfg->advanced_bt_coexist && priv->bt_full_concurrent) {
1330 /* operated as 1x1 in full concurrency mode */
1331 rx_ant = first_antenna(rx_ant);
1332 }
1333
Johannes Bergb6e4c552010-04-06 04:12:42 -07001334 /* MIMO is not used here, but value is required */
1335 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1336 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1337 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1338 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1339 scan->rx_chain = cpu_to_le16(rx_chain);
1340 if (!priv->is_internal_short_scan) {
1341 cmd_len = iwl_fill_probe_req(priv,
1342 (struct ieee80211_mgmt *)scan->data,
Johannes Berg3a0b9aa2010-05-12 03:33:12 -07001343 vif->addr,
Johannes Bergb6e4c552010-04-06 04:12:42 -07001344 priv->scan_request->ie,
1345 priv->scan_request->ie_len,
1346 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1347 } else {
Johannes Berg3a0b9aa2010-05-12 03:33:12 -07001348 /* use bcast addr, will not be transmitted but must be valid */
Johannes Bergb6e4c552010-04-06 04:12:42 -07001349 cmd_len = iwl_fill_probe_req(priv,
1350 (struct ieee80211_mgmt *)scan->data,
Johannes Berg3a0b9aa2010-05-12 03:33:12 -07001351 iwl_bcast_addr, NULL, 0,
Johannes Bergb6e4c552010-04-06 04:12:42 -07001352 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1353
1354 }
1355 scan->tx_cmd.len = cpu_to_le16(cmd_len);
Johannes Bergb6e4c552010-04-06 04:12:42 -07001356
1357 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1358 RXON_FILTER_BCON_AWARE_MSK);
1359
1360 if (priv->is_internal_short_scan) {
1361 scan->channel_count =
Johannes Berg1dda6d22010-04-29 04:43:06 -07001362 iwl_get_single_channel_for_scan(priv, vif, band,
Johannes Bergb6e4c552010-04-06 04:12:42 -07001363 (void *)&scan->data[le16_to_cpu(
1364 scan->tx_cmd.len)]);
1365 } else {
1366 scan->channel_count =
Johannes Berg1dda6d22010-04-29 04:43:06 -07001367 iwl_get_channels_for_scan(priv, vif, band,
Johannes Bergb6e4c552010-04-06 04:12:42 -07001368 is_active, n_probes,
1369 (void *)&scan->data[le16_to_cpu(
1370 scan->tx_cmd.len)]);
1371 }
1372 if (scan->channel_count == 0) {
1373 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
Johannes Berg3eecce52010-09-13 14:46:33 +02001374 return -EIO;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001375 }
1376
1377 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1378 scan->channel_count * sizeof(struct iwl_scan_channel);
1379 cmd.data = scan;
1380 scan->len = cpu_to_le16(cmd.len);
1381
Johannes Berg3eecce52010-09-13 14:46:33 +02001382 if (priv->cfg->ops->hcmd->set_pan_params) {
1383 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1384 if (ret)
1385 return ret;
1386 }
1387
Johannes Bergb6e4c552010-04-06 04:12:42 -07001388 set_bit(STATUS_SCAN_HW, &priv->status);
Johannes Berg3eecce52010-09-13 14:46:33 +02001389 ret = iwl_send_cmd_sync(priv, &cmd);
1390 if (ret) {
1391 clear_bit(STATUS_SCAN_HW, &priv->status);
1392 if (priv->cfg->ops->hcmd->set_pan_params)
1393 priv->cfg->ops->hcmd->set_pan_params(priv);
1394 }
Johannes Berg52a02d12010-08-27 09:44:50 -07001395
Johannes Berg3eecce52010-09-13 14:46:33 +02001396 return ret;
Johannes Bergb6e4c552010-04-06 04:12:42 -07001397}
Johannes Berg1fa61b22010-04-28 08:44:52 -07001398
1399int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1400 struct ieee80211_vif *vif, bool add)
1401{
Johannes Bergfd1af152010-04-30 11:30:43 -07001402 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1403
Johannes Berg1fa61b22010-04-28 08:44:52 -07001404 if (add)
Johannes Berga194e322010-08-27 08:53:46 -07001405 return iwl_add_bssid_station(priv, vif_priv->ctx,
1406 vif->bss_conf.bssid, true,
Johannes Bergfd1af152010-04-30 11:30:43 -07001407 &vif_priv->ibss_bssid_sta_id);
1408 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1409 vif->bss_conf.bssid);
Johannes Berg1fa61b22010-04-28 08:44:52 -07001410}
Johannes Berg1ff504e2010-05-03 01:22:42 -07001411
1412void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1413 int sta_id, int tid, int freed)
1414{
Johannes Berga24d52f2010-08-06 16:17:53 +02001415 lockdep_assert_held(&priv->sta_lock);
Reinette Chatre9c5ac092010-05-05 02:26:06 -07001416
Johannes Berg1ff504e2010-05-03 01:22:42 -07001417 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1418 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1419 else {
1420 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1421 priv->stations[sta_id].tid[tid].tfds_in_queue,
1422 freed);
1423 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1424 }
1425}
Wey-Yi Guy716c74b2010-06-24 13:22:36 -07001426
1427#define IWL_FLUSH_WAIT_MS 2000
1428
1429int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1430{
1431 struct iwl_tx_queue *txq;
1432 struct iwl_queue *q;
1433 int cnt;
1434 unsigned long now = jiffies;
1435 int ret = 0;
1436
1437 /* waiting for all the tx frames complete might take a while */
1438 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
Johannes Berg13bb9482010-08-23 10:46:33 +02001439 if (cnt == priv->cmd_queue)
Wey-Yi Guy716c74b2010-06-24 13:22:36 -07001440 continue;
1441 txq = &priv->txq[cnt];
1442 q = &txq->q;
1443 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1444 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1445 msleep(1);
1446
1447 if (q->read_ptr != q->write_ptr) {
1448 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1449 ret = -ETIMEDOUT;
1450 break;
1451 }
1452 }
1453 return ret;
1454}
1455
1456#define IWL_TX_QUEUE_MSK 0xfffff
1457
1458/**
1459 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1460 *
1461 * pre-requirements:
1462 * 1. acquire mutex before calling
1463 * 2. make sure rf is on and not in exit state
1464 */
1465int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1466{
1467 struct iwl_txfifo_flush_cmd flush_cmd;
1468 struct iwl_host_cmd cmd = {
1469 .id = REPLY_TXFIFO_FLUSH,
1470 .len = sizeof(struct iwl_txfifo_flush_cmd),
1471 .flags = CMD_SYNC,
1472 .data = &flush_cmd,
1473 };
1474
1475 might_sleep();
1476
1477 memset(&flush_cmd, 0, sizeof(flush_cmd));
1478 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1479 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1480 if (priv->cfg->sku & IWL_SKU_N)
1481 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1482
1483 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1484 flush_cmd.fifo_control);
1485 flush_cmd.flush_control = cpu_to_le16(flush_control);
1486
1487 return iwl_send_cmd(priv, &cmd);
1488}
Wey-Yi Guy65550632010-06-24 13:18:35 -07001489
1490void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1491{
1492 mutex_lock(&priv->mutex);
1493 ieee80211_stop_queues(priv->hw);
1494 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1495 IWL_ERR(priv, "flush request fail\n");
1496 goto done;
1497 }
1498 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1499 iwlagn_wait_tx_queue_empty(priv);
1500done:
1501 ieee80211_wake_queues(priv->hw);
1502 mutex_unlock(&priv->mutex);
1503}
Wey-Yi Guyb6e116e2010-08-23 07:57:14 -07001504
1505/*
1506 * BT coex
1507 */
1508/*
1509 * Macros to access the lookup table.
1510 *
1511 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1512* wifi_prio, wifi_txrx and wifi_sh_ant_req.
1513 *
1514 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1515 *
1516 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1517 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1518 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1519 *
1520 * These macros encode that format.
1521 */
1522#define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1523 wifi_txrx, wifi_sh_ant_req) \
1524 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1525 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1526
1527#define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1528 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1529#define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1530 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1531 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1532 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1533 wifi_sh_ant_req))))
1534#define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1535 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1536 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1537 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1538 wifi_sh_ant_req))
1539#define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1540 wifi_req, wifi_prio, wifi_txrx, \
1541 wifi_sh_ant_req) \
1542 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1543 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1544 wifi_sh_ant_req))
1545
1546#define LUT_WLAN_KILL_OP(lut, op, val) \
1547 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1548#define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1549 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1550 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1551 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1552#define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1553 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1554 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1555 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1556#define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1557 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1558 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1559 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1560
1561#define LUT_ANT_SWITCH_OP(lut, op, val) \
1562 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1563#define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1564 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1565 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1566 wifi_req, wifi_prio, wifi_txrx, \
1567 wifi_sh_ant_req))))
1568#define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1569 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1570 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1571 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1572#define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1573 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1574 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1575 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1576
1577static const __le32 iwlagn_def_3w_lookup[12] = {
1578 cpu_to_le32(0xaaaaaaaa),
1579 cpu_to_le32(0xaaaaaaaa),
1580 cpu_to_le32(0xaeaaaaaa),
1581 cpu_to_le32(0xaaaaaaaa),
1582 cpu_to_le32(0xcc00ff28),
1583 cpu_to_le32(0x0000aaaa),
1584 cpu_to_le32(0xcc00aaaa),
1585 cpu_to_le32(0x0000aaaa),
1586 cpu_to_le32(0xc0004000),
1587 cpu_to_le32(0x00004000),
1588 cpu_to_le32(0xf0005000),
1589 cpu_to_le32(0xf0004000),
1590};
1591
1592static const __le32 iwlagn_concurrent_lookup[12] = {
1593 cpu_to_le32(0xaaaaaaaa),
1594 cpu_to_le32(0xaaaaaaaa),
1595 cpu_to_le32(0xaaaaaaaa),
1596 cpu_to_le32(0xaaaaaaaa),
1597 cpu_to_le32(0xaaaaaaaa),
1598 cpu_to_le32(0xaaaaaaaa),
1599 cpu_to_le32(0xaaaaaaaa),
1600 cpu_to_le32(0xaaaaaaaa),
1601 cpu_to_le32(0x00000000),
1602 cpu_to_le32(0x00000000),
1603 cpu_to_le32(0x00000000),
1604 cpu_to_le32(0x00000000),
1605};
1606
1607void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1608{
1609 struct iwlagn_bt_cmd bt_cmd = {
1610 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1611 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1612 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1613 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1614 };
1615
1616 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1617 sizeof(bt_cmd.bt3_lookup_table));
1618
1619 bt_cmd.prio_boost = priv->cfg->bt_prio_boost;
1620 bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1621 bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1622 bt_cmd.valid = priv->bt_valid;
1623
1624 /*
1625 * Configure BT coex mode to "no coexistence" when the
1626 * user disabled BT coexistence, we have no interface
1627 * (might be in monitor mode), or the interface is in
1628 * IBSS mode (no proper uCode support for coex then).
1629 */
1630 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1631 bt_cmd.flags = 0;
1632 } else {
1633 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1634 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1635 if (priv->bt_ch_announce)
1636 bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1637 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1638 }
1639 if (priv->bt_full_concurrent)
1640 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1641 sizeof(iwlagn_concurrent_lookup));
1642 else
1643 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1644 sizeof(iwlagn_def_3w_lookup));
1645
1646 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1647 bt_cmd.flags ? "active" : "disabled",
1648 priv->bt_full_concurrent ?
1649 "full concurrency" : "3-wire");
1650
1651 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1652 IWL_ERR(priv, "failed to send BT Coex Config\n");
1653
1654 /*
1655 * When we are doing a restart, need to also reconfigure BT
1656 * SCO to the device. If not doing a restart, bt_sco_active
1657 * will always be false, so there's no need to have an extra
1658 * variable to check for it.
1659 */
1660 if (priv->bt_sco_active) {
1661 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1662
1663 if (priv->bt_sco_active)
1664 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1665 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1666 sizeof(sco_cmd), &sco_cmd))
1667 IWL_ERR(priv, "failed to send BT SCO command\n");
1668 }
1669}
1670
1671static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1672{
1673 struct iwl_priv *priv =
1674 container_of(work, struct iwl_priv, bt_traffic_change_work);
Johannes Berg8bd413e2010-08-23 10:46:40 +02001675 struct iwl_rxon_context *ctx;
Wey-Yi Guyb6e116e2010-08-23 07:57:14 -07001676 int smps_request = -1;
1677
1678 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1679 priv->bt_traffic_load);
1680
1681 switch (priv->bt_traffic_load) {
1682 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1683 smps_request = IEEE80211_SMPS_AUTOMATIC;
1684 break;
1685 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1686 smps_request = IEEE80211_SMPS_DYNAMIC;
1687 break;
1688 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1689 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1690 smps_request = IEEE80211_SMPS_STATIC;
1691 break;
1692 default:
1693 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1694 priv->bt_traffic_load);
1695 break;
1696 }
1697
1698 mutex_lock(&priv->mutex);
1699
1700 if (priv->cfg->ops->lib->update_chain_flags)
1701 priv->cfg->ops->lib->update_chain_flags(priv);
1702
Johannes Berg8bd413e2010-08-23 10:46:40 +02001703 if (smps_request != -1) {
1704 for_each_context(priv, ctx) {
1705 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1706 ieee80211_request_smps(ctx->vif, smps_request);
1707 }
1708 }
Wey-Yi Guyb6e116e2010-08-23 07:57:14 -07001709
1710 mutex_unlock(&priv->mutex);
1711}
1712
1713static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1714 struct iwl_bt_uart_msg *uart_msg)
1715{
1716 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1717 "Update Req = 0x%X",
1718 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1719 BT_UART_MSG_FRAME1MSGTYPE_POS,
1720 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1721 BT_UART_MSG_FRAME1SSN_POS,
1722 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1723 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1724
1725 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1726 "Chl_SeqN = 0x%X, In band = 0x%X",
1727 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1728 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1729 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1730 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1731 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1732 BT_UART_MSG_FRAME2CHLSEQN_POS,
1733 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1734 BT_UART_MSG_FRAME2INBAND_POS);
1735
1736 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1737 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1738 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1739 BT_UART_MSG_FRAME3SCOESCO_POS,
1740 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1741 BT_UART_MSG_FRAME3SNIFF_POS,
1742 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1743 BT_UART_MSG_FRAME3A2DP_POS,
1744 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1745 BT_UART_MSG_FRAME3ACL_POS,
1746 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1747 BT_UART_MSG_FRAME3MASTER_POS,
1748 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1749 BT_UART_MSG_FRAME3OBEX_POS);
1750
1751 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1752 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1753 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1754
1755 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1756 "eSCO Retransmissions = 0x%X",
1757 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1758 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1759 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1760 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1761 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1762 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1763
1764 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1765 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1766 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1767 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1768 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1769
1770 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1771 "0x%X, Connectable = 0x%X",
1772 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1773 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1774 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1775 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1776 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1777 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1778}
1779
1780static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
1781 struct iwl_bt_uart_msg *uart_msg)
1782{
1783 u8 kill_ack_msk;
1784 __le32 bt_kill_ack_msg[2] = {
1785 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
1786
1787 kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
1788 BT_UART_MSG_FRAME3SNIFF_MSK |
1789 BT_UART_MSG_FRAME3SCOESCO_MSK) &
1790 uart_msg->frame3) == 0) ? 1 : 0;
1791 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
1792 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1793 priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
1794 /* schedule to send runtime bt_config */
1795 queue_work(priv->workqueue, &priv->bt_runtime_config);
1796 }
1797
1798}
1799
1800void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1801 struct iwl_rx_mem_buffer *rxb)
1802{
1803 unsigned long flags;
1804 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1805 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1806 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1807 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1808 u8 last_traffic_load;
1809
1810 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1811 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
1812 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
1813 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
1814 coex->bt_ci_compliance);
1815 iwlagn_print_uartmsg(priv, uart_msg);
1816
1817 last_traffic_load = priv->notif_bt_traffic_load;
1818 priv->notif_bt_traffic_load = coex->bt_traffic_load;
1819 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1820 if (priv->bt_status != coex->bt_status ||
1821 last_traffic_load != coex->bt_traffic_load) {
1822 if (coex->bt_status) {
1823 /* BT on */
1824 if (!priv->bt_ch_announce)
1825 priv->bt_traffic_load =
1826 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1827 else
1828 priv->bt_traffic_load =
1829 coex->bt_traffic_load;
1830 } else {
1831 /* BT off */
1832 priv->bt_traffic_load =
1833 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1834 }
1835 priv->bt_status = coex->bt_status;
1836 queue_work(priv->workqueue,
1837 &priv->bt_traffic_change_work);
1838 }
1839 if (priv->bt_sco_active !=
1840 (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
1841 priv->bt_sco_active = uart_msg->frame3 &
1842 BT_UART_MSG_FRAME3SCOESCO_MSK;
1843 if (priv->bt_sco_active)
1844 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1845 iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
1846 sizeof(sco_cmd), &sco_cmd, NULL);
1847 }
1848 }
1849
1850 iwlagn_set_kill_ack_msk(priv, uart_msg);
1851
1852 /* FIXME: based on notification, adjust the prio_boost */
1853
1854 spin_lock_irqsave(&priv->lock, flags);
1855 priv->bt_ci_compliance = coex->bt_ci_compliance;
1856 spin_unlock_irqrestore(&priv->lock, flags);
1857}
1858
1859void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1860{
1861 iwlagn_rx_handler_setup(priv);
1862 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1863 iwlagn_bt_coex_profile_notif;
1864}
1865
1866void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1867{
1868 iwlagn_setup_deferred_work(priv);
1869
1870 INIT_WORK(&priv->bt_traffic_change_work,
1871 iwlagn_bt_traffic_change_work);
1872}
1873
1874void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1875{
1876 cancel_work_sync(&priv->bt_traffic_change_work);
1877}