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review.evervolv.com / android_kernel_htc_msm8960 / 3f2bc4d6eb5a4fada842462ba22bb6bbb41d00c7 / . / arch / arm / mach-msm / board-fsm9xxx.c
blob: 3fbd97e731003e367f3383f6a1ba628ee92e55a4 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame^]1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/gpio.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/mfd/pmic8058.h>
20#include <linux/regulator/pmic8058-regulator.h>
21#include <linux/i2c.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmapool.h>
24#include <linux/regulator/pm8058-xo.h>
25
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/setup.h>
29
30#include <mach/mpp.h>
31#include <mach/board.h>
32#include <mach/memory.h>
33#include <mach/msm_iomap.h>
34#include <mach/dma.h>
35#include <mach/sirc.h>
36#include <mach/pmic.h>
37
38#include <mach/vreg.h>
39#include <mach/socinfo.h>
40#include "devices.h"
41#include "timer.h"
42#include "pm.h"
43#include "spm.h"
44#include <linux/regulator/consumer.h>
45#include <linux/regulator/machine.h>
46#include <linux/msm_adc.h>
47#include <linux/pmic8058-xoadc.h>
48#include <linux/m_adcproc.h>
49#include <linux/platform_data/qcom_crypto_device.h>
50
51#define PMIC_GPIO_INT 144
52#define PMIC_VREG_WLAN_LEVEL 2900
53#define PMIC_GPIO_SD_DET 165
54
55#define GPIO_EPHY_RST_N 37
56
57#define GPIO_GRFC_FTR0_0 136 /* GRFC 20 */
58#define GPIO_GRFC_FTR0_1 137 /* GRFC 21 */
59#define GPIO_GRFC_FTR1_0 145 /* GRFC 22 */
60#define GPIO_GRFC_FTR1_1 93 /* GRFC 19 */
61#define GPIO_GRFC_2 110
62#define GPIO_GRFC_3 109
63#define GPIO_GRFC_4 108
64#define GPIO_GRFC_5 107
65#define GPIO_GRFC_6 106
66#define GPIO_GRFC_7 105
67#define GPIO_GRFC_8 104
68#define GPIO_GRFC_9 103
69#define GPIO_GRFC_10 102
70#define GPIO_GRFC_11 101
71#define GPIO_GRFC_13 99
72#define GPIO_GRFC_14 98
73#define GPIO_GRFC_15 97
74#define GPIO_GRFC_16 96
75#define GPIO_GRFC_17 95
76#define GPIO_GRFC_18 94
77#define GPIO_GRFC_24 150
78#define GPIO_GRFC_25 151
79#define GPIO_GRFC_26 152
80#define GPIO_GRFC_27 153
81#define GPIO_GRFC_28 154
82#define GPIO_GRFC_29 155
83
84#define FPGA_SDCC_STATUS 0x8E0001A8
85
86/* Macros assume PMIC GPIOs start at 0 */
87#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_MSM_GPIOS)
88#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_MSM_GPIOS)
89
90#define PMIC_GPIO_5V_PA_PWR 21 /* PMIC GPIO Number 22 */
91#define PMIC_GPIO_4_2V_PA_PWR 22 /* PMIC GPIO Number 23 */
92#define PMIC_MPP_3 2 /* PMIC MPP Number 3 */
93#define PMIC_MPP_6 5 /* PMIC MPP Number 6 */
94#define PMIC_MPP_7 6 /* PMIC MPP Number 7 */
95#define PMIC_MPP_10 9 /* PMIC MPP Number 10 */
96
97/*
98 * PM8058
99 */
100
101static int pm8058_gpios_init(void)
102{
103 int i;
104 int rc;
105 struct pm8058_gpio_cfg {
106 int gpio;
107 struct pm8058_gpio cfg;
108 };
109
110 struct pm8058_gpio_cfg gpio_cfgs[] = {
111 { /* 5V PA Power */
112 PMIC_GPIO_5V_PA_PWR,
113 {
114 .vin_sel = 0,
115 .direction = PM_GPIO_DIR_BOTH,
116 .output_value = 1,
117 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
118 .pull = PM_GPIO_PULL_DN,
119 .out_strength = PM_GPIO_STRENGTH_HIGH,
120 .function = PM_GPIO_FUNC_NORMAL,
121 .inv_int_pol = 0,
122 },
123 },
124 { /* 4.2V PA Power */
125 PMIC_GPIO_4_2V_PA_PWR,
126 {
127 .vin_sel = 0,
128 .direction = PM_GPIO_DIR_BOTH,
129 .output_value = 1,
130 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
131 .pull = PM_GPIO_PULL_DN,
132 .out_strength = PM_GPIO_STRENGTH_HIGH,
133 .function = PM_GPIO_FUNC_NORMAL,
134 .inv_int_pol = 0,
135 },
136 },
137 };
138
139 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
140 rc = pm8058_gpio_config(gpio_cfgs[i].gpio, &gpio_cfgs[i].cfg);
141 if (rc < 0) {
142 pr_err("%s pmic gpio config failed\n", __func__);
143 return rc;
144 }
145 }
146
147 return 0;
148}
149
150static int pm8058_mpps_init(void)
151{
152 int rc;
153
154 /* Set up MPP 3 and 6 as analog outputs at 1.25V */
155 rc = pm8058_mpp_config_analog_output(PMIC_MPP_3,
156 PM_MPP_AOUT_LVL_1V25_2, PM_MPP_AOUT_CTL_ENABLE);
157 if (rc) {
158 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
159 return rc;
160 }
161
162 rc = pm8058_mpp_config_analog_output(PMIC_MPP_6,
163 PM_MPP_AOUT_LVL_1V25_2, PM_MPP_AOUT_CTL_ENABLE);
164 if (rc) {
165 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
166 return rc;
167 }
168 return 0;
169}
170
171static struct pm8058_gpio_platform_data pm8058_gpio_data = {
172 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
173 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
174 .init = pm8058_gpios_init,
175};
176
177static struct pm8058_gpio_platform_data pm8058_mpp_data = {
178 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
179 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
180 .init = pm8058_mpps_init,
181};
182
183static struct regulator_consumer_supply pm8058_vreg_supply[PM8058_VREG_MAX] = {
184 [PM8058_VREG_ID_L3] = REGULATOR_SUPPLY("8058_l3", NULL),
185 [PM8058_VREG_ID_L8] = REGULATOR_SUPPLY("8058_l8", NULL),
186 [PM8058_VREG_ID_L9] = REGULATOR_SUPPLY("8058_l9", NULL),
187 [PM8058_VREG_ID_L14] = REGULATOR_SUPPLY("8058_l14", NULL),
188 [PM8058_VREG_ID_L15] = REGULATOR_SUPPLY("8058_l15", NULL),
189 [PM8058_VREG_ID_L18] = REGULATOR_SUPPLY("8058_l18", NULL),
190 [PM8058_VREG_ID_S4] = REGULATOR_SUPPLY("8058_s4", NULL),
191
192 [PM8058_VREG_ID_LVS0] = REGULATOR_SUPPLY("8058_lvs0", NULL),
193};
194
195#define PM8058_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
196 _always_on, _pull_down) \
197 [_id] = { \
198 .init_data = { \
199 .constraints = { \
200 .valid_modes_mask = _modes, \
201 .valid_ops_mask = _ops, \
202 .min_uV = _min_uV, \
203 .max_uV = _max_uV, \
204 .apply_uV = _apply_uV, \
205 .always_on = _always_on, \
206 }, \
207 .num_consumer_supplies = 1, \
208 .consumer_supplies = &pm8058_vreg_supply[_id], \
209 }, \
210 .pull_down_enable = _pull_down, \
211 .pin_ctrl = 0, \
212 .pin_fn = PM8058_VREG_PIN_FN_ENABLE, \
213 }
214
215#define PM8058_VREG_INIT_LDO(_id, _min_uV, _max_uV) \
216 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \
217 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \
218 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \
219 REGULATOR_CHANGE_MODE, 1, 1, 1)
220
221#define PM8058_VREG_INIT_SMPS(_id, _min_uV, _max_uV) \
222 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \
223 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \
224 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \
225 REGULATOR_CHANGE_MODE, 1, 1, 1)
226
227#define PM8058_VREG_INIT_LVS(_id, _min_uV, _max_uV) \
228 PM8058_VREG_INIT(_id, _min_uV, _min_uV, REGULATOR_MODE_NORMAL, \
229 REGULATOR_CHANGE_STATUS, 0, 0, 1)
230
231static struct pm8058_vreg_pdata pm8058_vreg_init[PM8058_VREG_MAX] = {
232 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L3, 1800000, 1800000),
233 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L8, 2200000, 2200000),
234 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L9, 2050000, 2050000),
235 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L14, 2850000, 2850000),
236 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L15, 2200000, 2200000),
237 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L18, 2200000, 2200000),
238 PM8058_VREG_INIT_LVS(PM8058_VREG_ID_LVS0, 1800000, 1800000),
239 PM8058_VREG_INIT_SMPS(PM8058_VREG_ID_S4, 1300000, 1300000),
240};
241
242#define PM8058_VREG(_id) { \
243 .name = "pm8058-regulator", \
244 .id = _id, \
245 .platform_data = &pm8058_vreg_init[_id], \
246}
247
248#ifdef CONFIG_SENSORS_MSM_ADC
249static struct resource resources_adc[] = {
250 {
251 .start = PM8058_ADC_IRQ(PMIC8058_IRQ_BASE),
252 .end = PM8058_ADC_IRQ(PMIC8058_IRQ_BASE),
253 .flags = IORESOURCE_IRQ,
254 },
255};
256
257static struct adc_access_fn xoadc_fn = {
258 pm8058_xoadc_select_chan_and_start_conv,
259 pm8058_xoadc_read_adc_code,
260 pm8058_xoadc_get_properties,
261 pm8058_xoadc_slot_request,
262 pm8058_xoadc_restore_slot,
263 pm8058_xoadc_calibrate,
264};
265
266static struct msm_adc_channels msm_adc_channels_data[] = {
267 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
268 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
269 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
270 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
271 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
272 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
273 {"fsm_therm", CHANNEL_ADC_FSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE6,
274 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
275 {"pa_therm", CHANNEL_ADC_PA_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
276 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
277};
278
279static struct msm_adc_platform_data msm_adc_pdata = {
280 .channel = msm_adc_channels_data,
281 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
282 .target_hw = FSM_9xxx,
283};
284
285static struct platform_device msm_adc_device = {
286 .name = "msm_adc",
287 .id = -1,
288 .dev = {
289 .platform_data = &msm_adc_pdata,
290 },
291};
292
293static void pmic8058_xoadc_mpp_config(void)
294{
295 int rc;
296
297 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
298 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
299 if (rc)
300 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
301
302 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
303 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
304 if (rc)
305 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
306}
307
308static struct regulator *vreg_ldo18_adc;
309
310static int pmic8058_xoadc_vreg_config(int on)
311{
312 int rc;
313
314 if (on) {
315 rc = regulator_enable(vreg_ldo18_adc);
316 if (rc)
317 pr_err("%s: Enable of regulator ldo18_adc "
318 "failed\n", __func__);
319 } else {
320 rc = regulator_disable(vreg_ldo18_adc);
321 if (rc)
322 pr_err("%s: Disable of regulator ldo18_adc "
323 "failed\n", __func__);
324 }
325
326 return rc;
327}
328
329static int pmic8058_xoadc_vreg_setup(void)
330{
331 int rc;
332
333 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
334 if (IS_ERR(vreg_ldo18_adc)) {
335 pr_err("%s: vreg get failed (%ld)\n",
336 __func__, PTR_ERR(vreg_ldo18_adc));
337 rc = PTR_ERR(vreg_ldo18_adc);
338 goto fail;
339 }
340
341 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
342 if (rc) {
343 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
344 goto fail;
345 }
346
347 return rc;
348fail:
349 regulator_put(vreg_ldo18_adc);
350 return rc;
351}
352
353static void pmic8058_xoadc_vreg_shutdown(void)
354{
355 regulator_put(vreg_ldo18_adc);
356}
357
358/* usec. For this ADC,
359 * this time represents clk rate @ txco w/ 1024 decimation ratio.
360 * Each channel has different configuration, thus at the time of starting
361 * the conversion, xoadc will return actual conversion time
362 * */
363static struct adc_properties pm8058_xoadc_data = {
364 .adc_reference = 2200, /* milli-voltage for this adc */
365 .bitresolution = 15,
366 .bipolar = 0,
367 .conversiontime = 54,
368};
369
370static struct xoadc_platform_data xoadc_pdata = {
371 .xoadc_prop = &pm8058_xoadc_data,
372 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
373 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
374 .xoadc_num = XOADC_PMIC_0,
375 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
376 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
377};
378#endif
379
380/* Put sub devices with fixed location first in sub_devices array */
381static struct mfd_cell pm8058_subdevs[] = {
382 { .name = "pm8058-mpp",
383 .platform_data = &pm8058_mpp_data,
384 .pdata_size = sizeof(pm8058_mpp_data),
385 },
386 {
387 .name = "pm8058-gpio",
388 .id = -1,
389 .platform_data = &pm8058_gpio_data,
390 .pdata_size = sizeof(pm8058_gpio_data),
391 },
392#ifdef CONFIG_SENSORS_MSM_ADC
393 {
394 .name = "pm8058-xoadc",
395 .id = -1,
396 .num_resources = ARRAY_SIZE(resources_adc),
397 .resources = resources_adc,
398 .platform_data = &xoadc_pdata,
399 .pdata_size =sizeof(xoadc_pdata),
400 },
401#endif
402 PM8058_VREG(PM8058_VREG_ID_L3),
403 PM8058_VREG(PM8058_VREG_ID_L8),
404 PM8058_VREG(PM8058_VREG_ID_L9),
405 PM8058_VREG(PM8058_VREG_ID_L14),
406 PM8058_VREG(PM8058_VREG_ID_L15),
407 PM8058_VREG(PM8058_VREG_ID_L18),
408 PM8058_VREG(PM8058_VREG_ID_S4),
409 PM8058_VREG(PM8058_VREG_ID_LVS0),
410 PM8058_XO(PM8058_XO_ID_A0),
411 PM8058_XO(PM8058_XO_ID_A1),
412};
413
414static struct pm8058_platform_data pm8058_fsm9xxx_data = {
415 .irq_base = PMIC8058_IRQ_BASE,
416
417 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
418 .sub_devices = pm8058_subdevs,
419};
420
421static struct i2c_board_info pm8058_boardinfo[] __initdata = {
422 {
423 I2C_BOARD_INFO("pm8058-core", 0x55),
424 .irq = MSM_GPIO_TO_INT(47),
425 .platform_data = &pm8058_fsm9xxx_data,
426 },
427};
428
429static int __init buses_init(void)
430{
431 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 5, GPIO_CFG_INPUT,
432 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
433 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
434 __func__, PMIC_GPIO_INT);
435
436 i2c_register_board_info(0 /* I2C_SSBI ID */, pm8058_boardinfo,
437 ARRAY_SIZE(pm8058_boardinfo));
438
439 return 0;
440}
441
442/*
443 * EPHY
444 */
445
446static struct msm_gpio phy_config_data[] = {
447 { GPIO_CFG(GPIO_EPHY_RST_N, 0, GPIO_CFG_OUTPUT,
448 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "MAC_RST_N" },
449};
450
451static int __init phy_init(void)
452{
453 msm_gpios_request_enable(phy_config_data, ARRAY_SIZE(phy_config_data));
454 gpio_direction_output(GPIO_EPHY_RST_N, 0);
455 udelay(100);
456 gpio_set_value(GPIO_EPHY_RST_N, 1);
457
458 return 0;
459}
460
461/*
462 * RF
463 */
464
465static struct msm_gpio grfc_config_data[] = {
466 { GPIO_CFG(GPIO_GRFC_FTR0_0, 7, GPIO_CFG_OUTPUT,
467 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_0" },
468 { GPIO_CFG(GPIO_GRFC_FTR0_1, 7, GPIO_CFG_OUTPUT,
469 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_1" },
470 { GPIO_CFG(GPIO_GRFC_FTR1_0, 7, GPIO_CFG_OUTPUT,
471 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_0" },
472 { GPIO_CFG(GPIO_GRFC_FTR1_1, 7, GPIO_CFG_OUTPUT,
473 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_1" },
474 { GPIO_CFG(GPIO_GRFC_2, 7, GPIO_CFG_OUTPUT,
475 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_2" },
476 { GPIO_CFG(GPIO_GRFC_3, 7, GPIO_CFG_OUTPUT,
477 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_3" },
478 { GPIO_CFG(GPIO_GRFC_4, 7, GPIO_CFG_OUTPUT,
479 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_4" },
480 { GPIO_CFG(GPIO_GRFC_5, 7, GPIO_CFG_OUTPUT,
481 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_5" },
482 { GPIO_CFG(GPIO_GRFC_6, 7, GPIO_CFG_OUTPUT,
483 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_6" },
484 { GPIO_CFG(GPIO_GRFC_7, 7, GPIO_CFG_OUTPUT,
485 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_7" },
486 { GPIO_CFG(GPIO_GRFC_8, 7, GPIO_CFG_OUTPUT,
487 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_8" },
488 { GPIO_CFG(GPIO_GRFC_9, 7, GPIO_CFG_OUTPUT,
489 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_9" },
490 { GPIO_CFG(GPIO_GRFC_10, 7, GPIO_CFG_OUTPUT,
491 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_10" },
492 { GPIO_CFG(GPIO_GRFC_11, 7, GPIO_CFG_OUTPUT,
493 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_11" },
494 { GPIO_CFG(GPIO_GRFC_13, 7, GPIO_CFG_OUTPUT,
495 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_13" },
496 { GPIO_CFG(GPIO_GRFC_14, 7, GPIO_CFG_OUTPUT,
497 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_14" },
498 { GPIO_CFG(GPIO_GRFC_15, 7, GPIO_CFG_OUTPUT,
499 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_15" },
500 { GPIO_CFG(GPIO_GRFC_16, 7, GPIO_CFG_OUTPUT,
501 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_16" },
502 { GPIO_CFG(GPIO_GRFC_17, 7, GPIO_CFG_OUTPUT,
503 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_17" },
504 { GPIO_CFG(GPIO_GRFC_18, 7, GPIO_CFG_OUTPUT,
505 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_18" },
506 { GPIO_CFG(GPIO_GRFC_24, 7, GPIO_CFG_OUTPUT,
507 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_24" },
508 { GPIO_CFG(GPIO_GRFC_25, 7, GPIO_CFG_OUTPUT,
509 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_25" },
510 { GPIO_CFG(GPIO_GRFC_26, 7, GPIO_CFG_OUTPUT,
511 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_26" },
512 { GPIO_CFG(GPIO_GRFC_27, 7, GPIO_CFG_OUTPUT,
513 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_27" },
514 { GPIO_CFG(GPIO_GRFC_28, 7, GPIO_CFG_OUTPUT,
515 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_28" },
516 { GPIO_CFG(GPIO_GRFC_29, 7, GPIO_CFG_OUTPUT,
517 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_29" },
518 { GPIO_CFG(39, 1, GPIO_CFG_OUTPUT,
519 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "PP2S_EXT_SYNC" },
520};
521
522static int __init grfc_init(void)
523{
524 msm_gpios_request_enable(grfc_config_data,
525 ARRAY_SIZE(grfc_config_data));
526
527 return 0;
528}
529
530/*
531 * UART
532 */
533
534#ifdef CONFIG_SERIAL_MSM_CONSOLE
535static struct msm_gpio uart1_config_data[] = {
536 { GPIO_CFG(138, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
537 "UART1_Rx" },
538 { GPIO_CFG(139, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
539 "UART1_Tx" },
540};
541
542static void fsm9xxx_init_uart1(void)
543{
544 msm_gpios_request_enable(uart1_config_data,
545 ARRAY_SIZE(uart1_config_data));
546
547}
548#endif
549
550/*
551 * SSBI
552 */
553
554#ifdef CONFIG_I2C_SSBI
555static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi1_pdata = {
556 .controller_type = FSM_SBI_CTRL_SSBI,
557};
558
559static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi2_pdata = {
560 .controller_type = FSM_SBI_CTRL_SSBI,
561};
562
563static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi3_pdata = {
564 .controller_type = FSM_SBI_CTRL_SSBI,
565};
566
567/* Intialize GPIO configuration for SSBI */
568static struct msm_gpio ssbi_gpio_config_data[] = {
569 { GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
570 "SSBI_1" },
571 { GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
572 "SSBI_2" },
573 { GPIO_CFG(92, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
574 "SSBI_3" },
575};
576
577static void
578fsm9xxx_init_ssbi_gpio(void)
579{
580 msm_gpios_request_enable(ssbi_gpio_config_data,
581 ARRAY_SIZE(ssbi_gpio_config_data));
582
583}
584#endif
585
586/*
587 * Crypto
588 */
589
590#define QCE_SIZE 0x10000
591
592#define QCE_0_BASE 0x80C00000
593#define QCE_1_BASE 0x80E00000
594#define QCE_2_BASE 0x81000000
595
596#define QCE_NO_HW_KEY_SUPPORT 0 /* No shared HW key with external */
597#define QCE_NO_SHARE_CE_RESOURCE 0 /* No CE resource shared with TZ */
598#define QCE_NO_CE_SHARED 0 /* CE not shared with TZ */
599#define QCE_NO_SHA_HMAC_SUPPORT 0 /* No SHA-HMAC by SHA operation */
600
601static struct resource qcrypto_resources[] = {
602 [0] = {
603 .start = QCE_0_BASE,
604 .end = QCE_0_BASE + QCE_SIZE - 1,
605 .flags = IORESOURCE_MEM,
606 },
607 [1] = {
608 .name = "crypto_channels",
609 .start = DMOV_CE1_IN_CHAN,
610 .end = DMOV_CE1_OUT_CHAN,
611 .flags = IORESOURCE_DMA,
612 },
613 [2] = {
614 .name = "crypto_crci_in",
615 .start = DMOV_CE1_IN_CRCI,
616 .end = DMOV_CE1_IN_CRCI,
617 .flags = IORESOURCE_DMA,
618 },
619 [3] = {
620 .name = "crypto_crci_out",
621 .start = DMOV_CE1_OUT_CRCI,
622 .end = DMOV_CE1_OUT_CRCI,
623 .flags = IORESOURCE_DMA,
624 },
625 [4] = {
626 .name = "crypto_crci_hash",
627 .start = DMOV_CE1_HASH_CRCI,
628 .end = DMOV_CE1_HASH_CRCI,
629 .flags = IORESOURCE_DMA,
630 },
631};
632
633static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
634 .ce_shared = QCE_NO_CE_SHARED,
635 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
636 .hw_key_support = QCE_NO_HW_KEY_SUPPORT,
637 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
638};
639
640struct platform_device qcrypto_device = {
641 .name = "qcrypto",
642 .id = 0,
643 .num_resources = ARRAY_SIZE(qcrypto_resources),
644 .resource = qcrypto_resources,
645 .dev = {
646 .coherent_dma_mask = DMA_BIT_MASK(32),
647 .platform_data = &qcrypto_ce_hw_suppport,
648 },
649};
650
651static struct resource qcedev_resources[] = {
652 [0] = {
653 .start = QCE_0_BASE,
654 .end = QCE_0_BASE + QCE_SIZE - 1,
655 .flags = IORESOURCE_MEM,
656 },
657 [1] = {
658 .name = "crypto_channels",
659 .start = DMOV_CE1_IN_CHAN,
660 .end = DMOV_CE1_OUT_CHAN,
661 .flags = IORESOURCE_DMA,
662 },
663 [2] = {
664 .name = "crypto_crci_in",
665 .start = DMOV_CE1_IN_CRCI,
666 .end = DMOV_CE1_IN_CRCI,
667 .flags = IORESOURCE_DMA,
668 },
669 [3] = {
670 .name = "crypto_crci_out",
671 .start = DMOV_CE1_OUT_CRCI,
672 .end = DMOV_CE1_OUT_CRCI,
673 .flags = IORESOURCE_DMA,
674 },
675 [4] = {
676 .name = "crypto_crci_hash",
677 .start = DMOV_CE1_HASH_CRCI,
678 .end = DMOV_CE1_HASH_CRCI,
679 .flags = IORESOURCE_DMA,
680 },
681};
682
683static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
684 .ce_shared = QCE_NO_CE_SHARED,
685 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
686 .hw_key_support = QCE_NO_HW_KEY_SUPPORT,
687 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
688};
689
690static struct platform_device qcedev_device = {
691 .name = "qce",
692 .id = 0,
693 .num_resources = ARRAY_SIZE(qcedev_resources),
694 .resource = qcedev_resources,
695 .dev = {
696 .coherent_dma_mask = DMA_BIT_MASK(32),
697 .platform_data = &qcedev_ce_hw_suppport,
698 },
699};
700
701static struct resource ota_qcrypto_resources[] = {
702 [0] = {
703 .start = QCE_1_BASE,
704 .end = QCE_1_BASE + QCE_SIZE - 1,
705 .flags = IORESOURCE_MEM,
706 },
707 [1] = {
708 .name = "crypto_channels",
709 .start = DMOV_CE2_IN_CHAN,
710 .end = DMOV_CE2_OUT_CHAN,
711 .flags = IORESOURCE_DMA,
712 },
713 [2] = {
714 .name = "crypto_crci_in",
715 .start = DMOV_CE2_IN_CRCI,
716 .end = DMOV_CE2_IN_CRCI,
717 .flags = IORESOURCE_DMA,
718 },
719 [3] = {
720 .name = "crypto_crci_out",
721 .start = DMOV_CE2_OUT_CRCI,
722 .end = DMOV_CE2_OUT_CRCI,
723 .flags = IORESOURCE_DMA,
724 },
725 [4] = {
726 .name = "crypto_crci_hash",
727 .start = DMOV_CE2_HASH_CRCI,
728 .end = DMOV_CE2_HASH_CRCI,
729 .flags = IORESOURCE_DMA,
730 },
731};
732
733struct platform_device ota_qcrypto_device = {
734 .name = "qcota",
735 .id = 0,
736 .num_resources = ARRAY_SIZE(ota_qcrypto_resources),
737 .resource = ota_qcrypto_resources,
738 .dev = {
739 .coherent_dma_mask = DMA_BIT_MASK(32),
740 },
741};
742
743/*
744 * Devices
745 */
746
747static struct platform_device *devices[] __initdata = {
748 &msm_device_smd,
749 &msm_device_dmov,
750 &msm_device_nand,
751#ifdef CONFIG_I2C_SSBI
752 &msm_device_ssbi1,
753 &msm_device_ssbi2,
754 &msm_device_ssbi3,
755#endif
756#ifdef CONFIG_SENSORS_MSM_ADC
757 &msm_adc_device,
758#endif
759#ifdef CONFIG_I2C_QUP
760 &msm_gsbi1_qup_i2c_device,
761#endif
762#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
763 &msm_device_uart1,
764#endif
765#if defined(CONFIG_QFP_FUSE)
766 &fsm_qfp_fuse_device,
767#endif
768 &qfec_device,
769 &qcrypto_device,
770 &qcedev_device,
771 &ota_qcrypto_device,
772};
773
774static struct msm_acpu_clock_platform_data fsm9xxx_clock_data = {
775 .acpu_switch_time_us = 50,
776 .vdd_switch_time_us = 62,
777};
778
779static void __init fsm9xxx_init_irq(void)
780{
781 msm_init_irq();
782 msm_init_sirc();
783}
784
785#ifdef CONFIG_MSM_SPM
786static struct msm_spm_platform_data msm_spm_data __initdata = {
787 .reg_base_addr = MSM_SAW_BASE,
788
789 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
790 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
791 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
792 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
793
794 .reg_init_values[MSM_SPM_REG_SAW_SPM_PMIC_CTL] = 0xE0F272,
795 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
796 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
797 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
798
799 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
800 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
801 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
802
803 .awake_vlevel = 0xF2,
804 .retention_vlevel = 0xE0,
805 .collapse_vlevel = 0x72,
806 .retention_mid_vlevel = 0xE0,
807 .collapse_mid_vlevel = 0xE0,
808};
809#endif
810
811static void __init fsm9xxx_init(void)
812{
813 if (socinfo_init() < 0)
814 pr_err("%s: socinfo_init() failed!\n",
815 __func__);
816
817 msm_acpu_clock_init(&fsm9xxx_clock_data);
818
819 regulator_has_full_constraints();
820
821 platform_add_devices(devices, ARRAY_SIZE(devices));
822
823#ifdef CONFIG_MSM_SPM
824 msm_spm_init(&msm_spm_data, 1);
825#endif
826 buses_init();
827 phy_init();
828 grfc_init();
829
830#ifdef CONFIG_SERIAL_MSM_CONSOLE
831 fsm9xxx_init_uart1();
832#endif
833#ifdef CONFIG_I2C_SSBI
834 fsm9xxx_init_ssbi_gpio();
835 msm_device_ssbi1.dev.platform_data = &msm_i2c_ssbi1_pdata;
836 msm_device_ssbi2.dev.platform_data = &msm_i2c_ssbi2_pdata;
837 msm_device_ssbi3.dev.platform_data = &msm_i2c_ssbi3_pdata;
838#endif
839}
840
841static void __init fsm9xxx_map_io(void)
842{
843 msm_shared_ram_phys = 0x00100000;
844 msm_map_fsm9xxx_io();
845 msm_clock_init(msm_clocks_fsm9xxx, msm_num_clocks_fsm9xxx);
846}
847
848MACHINE_START(FSM9XXX_SURF, "QCT FSM9XXX")
849 .boot_params = PHYS_OFFSET + 0x100,
850 .map_io = fsm9xxx_map_io,
851 .init_irq = fsm9xxx_init_irq,
852 .init_machine = fsm9xxx_init,
853 .timer = &msm_timer,
854MACHINE_END